Searched defs:disp (Results 1 - 10 of 10) sorted by relevance

/art/compiler/dex/quick/arm/
H A Dassemble_arm.cc1507 int32_t disp = target_disp - ((lir->offset + 4) & ~3); local
1508 if (disp < 4096) {
1509 lir->operands[1] = disp;
1554 // operands[1] should hold disp, [2] has add, [3] has tab_rec
1564 // operands[1] should hold disp, [2] has add, [3] has tab_rec
H A Dutility_arm.cc1163 LIR* ArmMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { argument
/art/compiler/dex/quick/mips/
H A Dutility_mips.cc683 LIR* MipsMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { argument
/art/compiler/utils/x86/
H A Dassembler_x86.h105 void SetDisp8(int8_t disp) { argument
107 encoding_[length_++] = static_cast<uint8_t>(disp);
110 void SetDisp32(int32_t disp) { argument
112 int disp_size = sizeof(disp);
113 memmove(&encoding_[length_], &disp, disp_size);
138 Address(Register base, int32_t disp) { argument
139 Init(base, disp);
142 Address(Register base, Offset disp) { argument
143 Init(base, disp.Int32Value());
146 Address(Register base, FrameOffset disp) { argument
151 Address(Register base, MemberOffset disp) argument
155 Init(Register base, int32_t disp) argument
171 Address(Register index, ScaleFactor scale, int32_t disp) argument
178 Address(Register base, Register index, ScaleFactor scale, int32_t disp) argument
[all...]
/art/compiler/utils/x86_64/
H A Dassembler_x86_64.h132 void SetDisp8(int8_t disp) { argument
134 encoding_[length_++] = static_cast<uint8_t>(disp);
137 void SetDisp32(int32_t disp) { argument
139 int disp_size = sizeof(disp);
140 memmove(&encoding_[length_], &disp, disp_size);
166 Address(CpuRegister base, int32_t disp) { argument
167 Init(base, disp);
170 Address(CpuRegister base, Offset disp) { argument
171 Init(base, disp.Int32Value());
174 Address(CpuRegister base, FrameOffset disp) { argument
179 Address(CpuRegister base, MemberOffset disp) argument
183 Init(CpuRegister base, int32_t disp) argument
205 Address(CpuRegister index, ScaleFactor scale, int32_t disp) argument
212 Address(CpuRegister base, CpuRegister index, ScaleFactor scale, int32_t disp) argument
[all...]
/art/compiler/dex/quick/x86/
H A Dutility_x86.cc456 0 /* scale */, 0 /* disp */);
460 0 /* scale */, 0 /* disp */);
510 // TODO: fix bug in LEA encoding when disp == 0
512 r_src.GetReg() /* index */, value /* scale */, 0 /* disp */);
516 0 /* scale */, value /* disp */);
549 LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { argument
557 return NewLIR2(opcode, r_base.GetReg(), disp);
H A Dassemble_x86.cc691 case kMem: // lir operands - 0: base, 1: disp
693 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
695 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
697 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate
699 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
702 case kThreadReg: // lir operands - 0: disp, 1: reg
709 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
711 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
714 case kRegThread: // lir operands - 0: reg, 1: disp
726 case kMemImm: // lir operands - 0: base, 1: disp,
846 ModrmForDisp(int base, int disp) argument
969 EmitDisp(uint8_t base, int32_t disp) argument
996 EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) argument
1008 EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int32_t disp) argument
1088 EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) argument
1101 EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp) argument
1112 EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg) argument
1124 EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp) argument
1130 EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t raw_index, int scale, int32_t disp) argument
1143 EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp, int32_t raw_reg) argument
1149 EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm) argument
1159 EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp, int32_t imm) argument
1171 EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) argument
1214 EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) argument
1227 EmitMemRegImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) argument
1247 EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) argument
1339 EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm) argument
1378 EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc) argument
1428 EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, int32_t cc) argument
1493 EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) argument
1502 EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) argument
1513 EmitCallThread(const X86EncodingMap* entry, int32_t disp) argument
1528 int disp; local
[all...]
/art/compiler/dex/quick/arm64/
H A Dutility_arm64.cc1397 LIR* Arm64Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { argument
/art/compiler/dex/quick/
H A Dcodegen_util.cc549 int disp = tab_rec->targets[elems]->offset - bx_offset; local
552 << std::hex << keys[elems] << ", disp: 0x"
553 << std::hex << disp; local
563 int disp = tab_rec->targets[elems]->offset - bx_offset; local
565 LOG(INFO) << " Case[" << elems << "] disp: 0x"
566 << std::hex << disp; local
H A Dgen_invoke.cc664 int32_t disp; local
666 disp = GetThreadOffset<8>(trampoline).Int32Value();
668 disp = GetThreadOffset<4>(trampoline).Int32Value();
670 cg->LoadWordDisp(cg->TargetPtrReg(kSelf), disp, cg->TargetPtrReg(kInvokeTgt));

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