Searched defs:opcode (Results 1 - 25 of 55) sorted by relevance

123

/art/compiler/dex/
H A Dpost_opt_passes.cc64 Instruction::Code opcode = mir->dalvikInsn.opcode; local
66 if (opcode == static_cast<Instruction::Code> (kMirOpPhi)) {
H A Dfrontend.cc584 int opcode = mir->dalvikInsn.opcode; local
587 opcode) != unsupport_list + unsupport_list_size) {
588 if (!MIR::DecodedInstruction::IsPseudoMirOp(opcode)) {
590 << mir->dalvikInsn.opcode;
592 VLOG(compiler) << "Unsupported extended MIR opcode : "
593 << MIRGraph::extended_mir_op_names_[opcode - kMirOpFirst];
598 if (Instruction::INVOKE_VIRTUAL == opcode ||
599 Instruction::INVOKE_SUPER == opcode ||
600 Instruction::INVOKE_DIRECT == opcode ||
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H A Dlocal_value_numbering_test.cc44 Instruction::Code opcode; member in struct:art::LocalValueNumberingTest::MIRDef
53 #define DEF_CONST(opcode, reg, value) \
54 { opcode, value, 0u, 0, { }, 1, { reg } }
55 #define DEF_CONST_WIDE(opcode, reg, value) \
56 { opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } }
57 #define DEF_CONST_STRING(opcode, reg, index) \
58 { opcode, index, 0u, 0, { }, 1, { reg } }
59 #define DEF_IGET(opcode, reg, obj, field_info) \
60 { opcode, 0u, field_info, 1, { obj }, 1, { reg } }
61 #define DEF_IGET_WIDE(opcode, re
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H A Dmir_dataflow.cc26 * instructions, where extended opcode at the MIR level are appended
915 switch (static_cast<int>(d_insn.opcode)) {
917 LOG(ERROR) << "Unexpected Extended Opcode " << d_insn.opcode;
1065 switch (static_cast<int>(mir->dalvikInsn.opcode)) {
1067 LOG(ERROR) << "Missing case for extended MIR: " << mir->dalvikInsn.opcode;
1087 if (!MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) {
1088 int flags = Instruction::FlagsOf(mir->dalvikInsn.opcode);
1270 Instruction::Code opcode = mir->dalvikInsn.opcode; local
1271 switch (opcode) {
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H A Dmir_optimization_test.cc47 Instruction::Code opcode; member in struct:art::ClassInitCheckEliminationTest::MIRDef
75 #define DEF_MIR(opcode, bb, field_info) \
76 { opcode, bb, field_info }
163 mir->dalvikInsn.opcode = def->opcode;
167 if (def->opcode >= Instruction::SGET && def->opcode <= Instruction::SPUT_SHORT) {
174 merged_df_flags |= MIRGraph::GetDataFlowAttributes(def->opcode);
H A Dvreg_analysis.cc218 if ((mir->dalvikInsn.opcode == Instruction::RETURN) ||
219 (mir->dalvikInsn.opcode == Instruction::RETURN_WIDE) ||
220 (mir->dalvikInsn.opcode == Instruction::RETURN_OBJECT)) {
253 Instruction::Code opcode = mir->dalvikInsn.opcode; local
254 int flags = MIR::DecodedInstruction::IsPseudoMirOp(opcode) ?
255 0 : Instruction::FlagsOf(mir->dalvikInsn.opcode);
265 if (move_result_mir && (move_result_mir->dalvikInsn.opcode !=
279 if (((mir->dalvikInsn.opcode != Instruction::INVOKE_STATIC) &&
280 (mir->dalvikInsn.opcode !
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H A Dglobal_value_numbering_test.cc58 Instruction::Code opcode; member in struct:art::GlobalValueNumberingTest::MIRDef
90 #define DEF_CONST(bb, opcode, reg, value) \
91 { bb, opcode, value, 0u, 0, { }, 1, { reg } }
92 #define DEF_CONST_WIDE(bb, opcode, reg, value) \
93 { bb, opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } }
94 #define DEF_CONST_STRING(bb, opcode, reg, index) \
95 { bb, opcode, index, 0u, 0, { }, 1, { reg } }
96 #define DEF_IGET(bb, opcode, reg, obj, field_info) \
97 { bb, opcode, 0u, field_info, 1, { obj }, 1, { reg } }
98 #define DEF_IGET_WIDE(bb, opcode, re
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/art/compiler/dex/quick/mips/
H A Dfp_mips.cc24 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode, argument
33 switch (opcode) {
61 LOG(FATAL) << "Unexpected opcode: " << opcode;
70 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode, argument
75 switch (opcode) {
103 LOG(FATAL) << "Unpexpected opcode: " << opcode;
116 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, argument
120 switch (opcode) {
168 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument
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H A Dassemble_mips.cc26 * opcode: MipsOpCode enum
27 * skeleton: pre-designated bit-pattern for this opcode
41 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \
44 {k3, k3s, k3e}}, opcode, flags, name, fmt, size}
463 int opcode = lir->opcode; local
465 switch (opcode) {
471 case kMipsBeq: opcode = kMipsBne; break;
472 case kMipsBne: opcode = kMipsBeq; break;
473 case kMipsBeqz: opcode
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H A Dutility_mips.cc26 int opcode; local
30 opcode = kMipsFmovd;
34 opcode = kMipsFmovs;
40 opcode = kMipsMtc1;
44 opcode = kMipsMfc1;
47 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src.GetReg(), r_dest.GetReg());
117 MipsOpCode opcode = kMipsNop; local
120 opcode = kMipsJalr;
128 return NewLIR2(opcode, rRA, r_dest_src.GetReg());
136 MipsOpCode opcode local
162 MipsOpCode opcode = kMipsNop; local
204 MipsOpCode opcode = kMipsNop; local
286 MipsOpCode opcode = kMipsNop; local
360 MipsOpCode opcode = kMipsNop; local
412 MipsOpCode opcode = kMipsNop; local
468 MipsOpCode opcode = kMipsNop; local
579 MipsOpCode opcode = kMipsNop; local
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H A Dint_mips.cc395 void MipsMir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, argument
417 void MipsMir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, argument
439 void MipsMir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, argument
441 switch (opcode) {
444 GenAddLong(opcode, rl_dest, rl_src1, rl_src2);
448 GenSubLong(opcode, rl_dest, rl_src1, rl_src2);
459 Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
630 void MipsMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, argument
633 GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
636 void MipsMir2Lir::GenArithImmOpLong(Instruction::Code opcode, argument
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/art/compiler/dex/quick/arm/
H A Dfp_arm.cc23 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, argument
32 switch (opcode) {
60 LOG(FATAL) << "Unexpected opcode: " << opcode;
69 void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode, argument
74 switch (opcode) {
102 LOG(FATAL) << "Unexpected opcode: " << opcode;
116 void ArmMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) { argument
121 switch (opcode) {
265 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument
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H A Dassemble_arm.cc24 * opcode: ArmOpcode enum
25 * skeleton: pre-designated bit-pattern for this opcode
39 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \
42 {k3, k3s, k3e}}, opcode, flags, name, fmt, size, fixup}
1073 int opcode = lir->opcode; local
1074 if (IsPseudoLirOp(opcode)) {
1075 if (UNLIKELY(opcode == kPseudoPseudoAlign4)) {
1076 // Note: size for this opcode will be either 0 or 2 depending on final alignment.
1084 const ArmEncodingMap *encoder = &EncodingMap[lir->opcode];
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H A Dtarget_arm.cc167 int opcode = lir->opcode; local
226 if (opcode == kThumbPush || opcode == kThumbPop) {
228 if ((opcode == kThumbPush) && (use_mask->Intersects(r8Mask))) {
231 } else if ((opcode == kThumbPop) && (def_mask->Intersects(r8Mask))) {
297 static char* DecodeRegList(int opcode, int vector, char* buf, size_t buf_size) { argument
304 if (opcode == kThumbPush && i == 8) {
306 } else if (opcode == kThumbPop && i == 8) {
470 DecodeRegList(lir->opcode, operan
735 GetTargetInstFlags(int opcode) argument
740 GetTargetInstName(int opcode) argument
745 GetTargetInstFmt(int opcode) argument
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H A Dutility_arm.cc224 ArmOpcode opcode = kThumbBkpt; local
227 opcode = kThumbBlxR;
230 opcode = kThumbBx;
233 LOG(FATAL) << "Bad opcode " << op;
235 return NewLIR1(opcode, r_dest_src.GetReg());
242 ArmOpcode opcode = kThumbBkpt; local
245 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR;
248 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR;
251 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR;
255 opcode
392 ArmOpcode opcode = kThumbBkpt; local
467 ArmOpcode opcode = kThumbBkpt; local
604 ArmOpcode opcode = kThumbBkpt; local
696 ArmOpcode opcode = kThumbBkpt; local
762 ArmOpcode opcode = kThumbBkpt; local
824 LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, int displacement, RegStorage r_src_dest, RegStorage r_work) argument
857 ArmOpcode opcode = kThumbBkpt; local
999 ArmOpcode opcode = kThumbBkpt; local
1144 int opcode; local
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/art/disassembler/
H A Ddisassembler_mips.cc179 std::string opcode; local
185 opcode = StringPrintf("op=%d fn=%d", op, function);
189 opcode = gMipsInstructions[i].name;
210 case 0: opcode += ".s"; break;
211 case 1: opcode += ".d"; break;
212 case 4: opcode += ".w"; break;
213 case 5: opcode += ".l"; break;
214 case 6: opcode += ".ps"; break;
215 default: opcode += ".?"; break;
259 << StringPrintf(": %08x\t%-7s ", instruction, opcode
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/art/runtime/
H A Ddex_instruction.cc62 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \
63 ((opcode == NOP) ? -1 : \
92 Code opcode = static_cast<Code>(insn & 0xFF); local
93 return FlagsOf(opcode) & Instruction::kContinue;
138 const char* opcode = kInstructionNames[Opcode()]; local
140 case k10x: os << opcode; break; local
141 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break;
142 case k11n: os << StringPrintf("%s v%d, #%+d", opcode, VRegA_11n(), VRegB_11n()); break;
143 case k11x: os << StringPrintf("%s v%d", opcode, VRegA_11x()); break;
144 case k10t: os << StringPrintf("%s %+d", opcode, VRegA_10
304 os << opcode << " {"; local
321 os << opcode << " {"; local
334 os << opcode << " {"; local
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/art/compiler/dex/quick/arm64/
H A Dassemble_arm64.cc50 * opcode: ArmOpcode enum
60 #define ENCODING_MAP(opcode, variants, a0k, a0s, a0e, a1k, a1s, a1e, a2k, a2s, a2e, \
63 {a3k, a3s, a3e}}, opcode, flags, name, fmt, 4, fixup}
654 bool opcode_is_wide = IS_WIDE(lir->opcode);
655 ArmOpcode opcode = UNWIDE(lir->opcode); local
657 if (UNLIKELY(IsPseudoLirOp(opcode))) {
662 const ArmEncodingMap *encoder = &EncodingMap[opcode];
666 DCHECK(!opcode_is_wide || IS_WIDE(encoder->opcode));
750 << "(" << UNWIDE(encoder->opcode) << ", " << encode
954 ArmOpcode opcode = UNWIDE(lir->opcode); local
965 ArmOpcode opcode = UNWIDE(lir->opcode); local
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H A Dfp_arm64.cc24 void Arm64Mir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, argument
29 switch (opcode) {
57 LOG(FATAL) << "Unexpected opcode: " << opcode;
66 void Arm64Mir2Lir::GenArithOpDouble(Instruction::Code opcode, argument
71 switch (opcode) {
105 LOG(FATAL) << "Unexpected opcode: " << opcode;
119 void Arm64Mir2Lir::GenConversion(Instruction::Code opcode, argument
126 switch (opcode) {
251 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument
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/art/compiler/dex/quick/
H A Dmir_to_lir-inl.h44 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0, argument
48 insn->opcode = opcode;
56 if ((opcode == kPseudoTargetLabel) || (opcode == kPseudoSafepointPC) ||
57 (opcode == kPseudoExportedPC)) {
69 inline LIR* Mir2Lir::NewLIR0(int opcode) { argument
70 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND))
71 << GetTargetInstName(opcode) << " " << opcod
79 NewLIR1(int opcode, int dest) argument
89 NewLIR2(int opcode, int dest, int src1) argument
99 NewLIR2NoDest(int opcode, int src, int info) argument
109 NewLIR3(int opcode, int dest, int src1, int src2) argument
119 NewLIR4(int opcode, int dest, int src1, int src2, int info) argument
129 NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2) argument
162 int opcode = lir->opcode; local
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H A Ddex_file_method_inliner.cc111 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode));
112 if (Instruction::FormatOf(invoke->dalvikInsn.opcode) == Instruction::k3rc) {
115 DCHECK_EQ(Instruction::FormatOf(invoke->dalvikInsn.opcode), Instruction::k35c);
122 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode));
123 return Instruction::FormatOf(invoke->dalvikInsn.opcode) == Instruction::k3rc ||
433 if (kIntrinsicIsStatic[intrinsic.opcode] != (info->type == kStatic)) {
437 switch (intrinsic.opcode) {
505 LOG(FATAL) << "Unexpected intrinsic opcode: " << intrinsic.opcode;
543 switch (method.opcode) {
741 Instruction::Code opcode = Instruction::MOVE_FROM16; local
779 Instruction::Code opcode = static_cast<Instruction::Code>(Instruction::IGET + data.op_variant); local
831 Instruction::Code opcode = static_cast<Instruction::Code>(Instruction::IPUT + data.op_variant); local
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/art/runtime/arch/x86/
H A Dfault_handler_x86.cc101 uint8_t opcode = *pc++; local
111 switch (opcode) {
130 opcode = *pc++;
139 if (x86_64 && opcode >= 0x40 && opcode <= 0x4f) {
140 opcode = *pc++;
143 if (opcode == 0x0f) {
144 // Two byte opcode
146 opcode = *pc++;
152 switch (opcode) {
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/art/runtime/quick/
H A Dinline_method_analyser.cc97 Instruction::Code opcode = instruction->Opcode(); local
99 switch (opcode) {
102 method->opcode = kInlineOpNop;
155 result->opcode = kInlineOpReturnArg;
192 result->opcode = kInlineOpNonWideConst;
203 Instruction::Code opcode = instruction->Opcode(); local
204 DCHECK(IsInstructionIGet(opcode));
208 if (!(return_opcode == Instruction::RETURN_WIDE && opcode == Instruction::IGET_WIDE) &&
209 !(return_opcode == Instruction::RETURN_OBJECT && opcode == Instruction::IGET_OBJECT) &&
210 !(return_opcode == Instruction::RETURN && opcode !
266 Instruction::Code opcode = instruction->Opcode(); local
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H A Dinline_method_analyser.h109 // The op_variant below is opcode-Instruction::IGET for IGETs and
110 // opcode-Instruction::IPUT for IPUTs. This is because the runtime
133 InlineMethodOpcode opcode; member in struct:art::InlineMethod
155 static constexpr bool IsInstructionIGet(Instruction::Code opcode) { argument
156 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT;
159 static constexpr bool IsInstructionIPut(Instruction::Code opcode) { argument
160 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT;
163 static constexpr uint16_t IGetVariant(Instruction::Code opcode) { argument
167 IPutVariant(Instruction::Code opcode) argument
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/art/compiler/dex/quick/x86/
H A Dfp_x86.cc24 void X86Mir2Lir::GenArithOpFloat(Instruction::Code opcode, argument
33 switch (opcode) {
58 LOG(FATAL) << "Unexpected opcode: " << opcode;
75 void X86Mir2Lir::GenArithOpDouble(Instruction::Code opcode, argument
86 switch (opcode) {
111 LOG(FATAL) << "Unexpected opcode: " << opcode;
159 int opcode = is_double ? kX86Fstp64M : kX86Fstp32M; local
161 LIR *fstp = NewLIR2NoDest(opcode, rs_rX86_S
193 GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) argument
419 int opcode = is_double ? kX86Fst64M : kX86Fst32M; local
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