Searched defs:reg1 (Results 1 - 24 of 24) sorted by relevance

/external/chromium_org/third_party/webrtc/system_wrappers/interface/
H A Dasm_defines.h52 .macro streqh reg1, reg2, num
53 strheq \reg1, \reg2, \num variable
/external/chromium_org/v8/src/arm/
H A Dmacro-assembler-arm.cc199 void MacroAssembler::Swap(Register reg1, argument
204 eor(reg1, reg1, Operand(reg2), LeaveCC, cond);
205 eor(reg2, reg2, Operand(reg1), LeaveCC, cond);
206 eor(reg1, reg1, Operand(reg2), LeaveCC, cond);
208 mov(scratch, reg1, LeaveCC, cond);
209 mov(reg1, reg2, LeaveCC, cond);
3023 void MacroAssembler::JumpIfNotBothSmi(Register reg1,
3027 tst(reg1, Operan
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/external/vixl/test/
H A Dtest-utils-a64.cc148 const Register& reg1) {
149 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits());
151 int64_t result = core->xreg(reg1.code());
146 Equal64(const Register& reg0, const RegisterDump* core, const Register& reg1) argument
/external/chromium_org/third_party/mesa/src/src/mesa/program/
H A Dregister_allocate.c189 struct ra_reg *reg1 = &regs->regs[r1]; local
191 if (reg1->conflict_list_size == reg1->num_conflicts) {
192 reg1->conflict_list_size *= 2;
193 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list,
194 unsigned int, reg1->conflict_list_size);
196 reg1->conflict_list[reg1->num_conflicts++] = r2;
197 reg1
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/external/chromium_org/v8/test/cctest/
H A Dtest-utils-arm64.cc148 const Register& reg1) {
149 ASSERT(reg0.Is64Bits() && reg1.Is64Bits());
151 int64_t result = core->xreg(reg1.code());
146 Equal64(const Register& reg0, const RegisterDump* core, const Register& reg1) argument
/external/mesa3d/src/mesa/program/
H A Dregister_allocate.c189 struct ra_reg *reg1 = &regs->regs[r1]; local
191 if (reg1->conflict_list_size == reg1->num_conflicts) {
192 reg1->conflict_list_size *= 2;
193 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list,
194 unsigned int, reg1->conflict_list_size);
196 reg1->conflict_list[reg1->num_conflicts++] = r2;
197 reg1
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/external/pixman/pixman/
H A Dpixman-arm-neon-asm.h76 .macro pixldst1 op, elem_size, reg1, mem_operand, abits variable
78 op&.&elem_size {d&reg1}, [&mem_operand&, :&abits&]!
80 op&.&elem_size {d&reg1}, [&mem_operand&]!
84 .macro pixldst2 op, elem_size, reg1, reg2, mem_operand, abits variable
86 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&, :&abits&]! variable
88 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&]! variable
92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits variable
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]! variable
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]! variable
100 .macro pixldst0 op, elem_size, reg1, id variable
104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand variable
105 op&.&elem_size {d&reg1, d&reg2, d&reg3}, [&mem_operand&]! variable
108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand variable
109 op&.&elem_size {d&reg1[idx], d&reg2[idx], d&reg3[idx]}, [&mem_operand&]! variable
212 .macro pixld1_s elem_size, reg1, mem_operand variable
256 .macro pixld2_s elem_size, reg1, reg2, mem_operand variable
275 pixld1_s elem_size, reg1, mem_operand variable
280 .macro pixld0_s elem_size, reg1, idx, mem_operand variable
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H A Dpixman-arm-simd-asm.h99 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0 variable
103 op&r&cond WK&reg1, [base], #4 variable
107 op&m&cond&ia base!, {WK&reg0,WK&reg1,WK&reg2,WK&reg3} variable
112 op&r&cond WK&reg1, [base], #4 variable
114 op&m&cond&ia base!, {WK&reg0,WK&reg1}
127 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base variable
129 stm&cond&db base, {WK&reg0,WK&reg1,WK&reg2,WK&reg3} variable
131 stm&cond&db base, {WK&reg0,WK&reg1}
H A Dpixman-region.c295 PREFIX (_equal) (region_type_t *reg1, region_type_t *reg2) argument
301 if (reg1->extents.x1 != reg2->extents.x1)
304 if (reg1->extents.x2 != reg2->extents.x2)
307 if (reg1->extents.y1 != reg2->extents.y1)
310 if (reg1->extents.y2 != reg2->extents.y2)
313 if (PIXREGION_NUMRECTS (reg1) != PIXREGION_NUMRECTS (reg2))
316 rects1 = PIXREGION_RECTS (reg1);
319 for (i = 0; i != PIXREGION_NUMRECTS (reg1); i++)
749 region_type_t * reg1, /* First region in operation */
784 if (PIXREGION_NAR (reg1) || PIXREGION_NA
748 pixman_op(region_type_t * new_reg, region_type_t * reg1, region_type_t * reg2, overlap_proc_ptr overlap_func, int append_non1, int append_non2 ) argument
1157 _intersect(region_type_t * new_reg, region_type_t * reg1, region_type_t * reg2) argument
1371 _union(region_type_t *new_reg, region_type_t *reg1, region_type_t *reg2) argument
2022 _inverse(region_type_t *new_reg, region_type_t *reg1, box_type_t * inv_rect) argument
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/external/aac/libFDK/src/
H A Dfixpoint_math.cpp430 FIXP_DBL reg1, reg2, regtmp ; local
445 reg1 = invSqrtTab[ (INT)(val>>(DFRACT_BITS-1-(SQRT_BITS+1))) & SQRT_BITS_MASK ];
448 regtmp= fPow2Div2(reg1); /* a = Q^2 */
450 reg1 += (fMultDiv2(regtmp, reg1)<<4); /* Q = Q + Q*b */
455 reg1 = fMultDiv2(reg1, reg2) << 2;
460 return(reg1);
/external/chromium_org/third_party/sqlite/src/src/
H A Dbuild.c865 int reg1, reg2, reg3; local
877 reg1 = pParse->regRowid = ++pParse->nMem;
909 sqlite3VdbeAddOp2(v, OP_NewRowid, 0, reg1);
911 sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg1);
/external/qemu/tcg/
H A Dtcg.c1834 /* Allocate a register belonging to reg1 & ~reg2 */
1835 static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2) argument
1840 tcg_regset_andnot(reg_ct, reg1, reg2);
/external/valgrind/main/VEX/priv/
H A Dhost_arm64_isel.c934 HReg reg1 = iselIntExpr_R(env, e->Iex.Binop.arg1); local
936 return ARM64AMode_RR(reg1, reg2);
H A Dhost_s390_isel.c3345 HReg reg1, reg2; local
3381 reg1 = newVRegI(env);
3382 addInstr(env, s390_insn_unop(4, op, reg1, op1));
3389 addInstr(env, s390_insn_compare(4, reg1, op2, False));
/external/vixl/src/a64/
H A Dassembler-a64.cc2245 bool AreAliased(const CPURegister& reg1, const CPURegister& reg2, argument
2255 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
2282 bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, argument
2286 VIXL_ASSERT(reg1.IsValid());
2288 match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
2289 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
2290 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
2291 match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
2292 match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);
2293 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1);
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/external/chromium_org/v8/src/arm64/
H A Dassembler-arm64.cc204 Register GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2, argument
206 CPURegList regs(reg1, reg2, reg3, reg4);
217 bool AreAliased(const CPURegister& reg1, const CPURegister& reg2, argument
227 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
254 bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, argument
258 ASSERT(reg1.IsValid());
260 match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
261 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
262 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
263 match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
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H A Dfull-codegen-arm64.cc65 void EmitJumpIfEitherNotSmi(Register reg1, Register reg2, Label* target) { argument
68 __ Orr(temp, reg1, reg2);
/external/chromium_org/v8/src/mips/
H A Dmacro-assembler-mips.cc553 Register reg1,
573 // reg1 - Used to hold the capacity mask of the dictionary.
579 GetNumberHash(reg0, reg1);
582 lw(reg1, FieldMemOperand(elements, SeededNumberDictionary::kCapacityOffset));
583 sra(reg1, reg1, kSmiTagSize);
584 Subu(reg1, reg1, Operand(1));
594 and_(reg2, reg2, reg1);
618 lw(reg1, FieldMemOperan
548 LoadFromNumberDictionary(Label* miss, Register elements, Register key, Register result, Register reg0, Register reg1, Register reg2) argument
2733 Swap(Register reg1, Register reg2, Register scratch) argument
4813 JumpIfNotBothSmi(Register reg1, Register reg2, Label* on_not_both_smi) argument
4823 JumpIfEitherSmi(Register reg1, Register reg2, Label* on_either_smi) argument
5624 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
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/external/chromium_org/v8/src/x87/
H A Dlithium-codegen-x87.cc493 void LCodeGen::X87LoadForUsage(X87Register reg1, X87Register reg2) { argument
494 ASSERT(x87_stack_.Contains(reg1));
496 x87_stack_.Fxch(reg1, 1);
/external/valgrind/main/perf/
H A Dtinycc.c16262 int mod, reg1, reg2, sib_reg1;
16284 reg1 = op->reg;
16286 reg1 = 4;
16287 g(mod + (reg << 3) + reg1);
16288 if (reg1 == 4) {
16260 int mod, reg1, reg2, sib_reg1; local
/external/chromium_org/third_party/sqlite/amalgamation/
H A Dsqlite3.c77704 int reg1, reg2, reg3; local
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/external/sqlite/dist/orig/
H A Dsqlite3.c87039 int reg1, reg2, reg3; local
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/external/sqlite/dist/
H A Dsqlite3.c87059 int reg1, reg2, reg3; local
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/external/owasp/sanitizer/tools/findbugs/lib/
H A Dfindbugs.jarMETA-INF/ META-INF/MANIFEST.MF default.xsl edu/ edu/umd/ edu/umd/cs/ edu/ ...

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