/external/llvm/lib/Target/R600/ |
H A D | SIRegisterInfo.h | 36 unsigned getHWRegIndex(unsigned Reg) const override; 40 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const; 60 /// \returns The sub-register of Reg that is in Channel. 61 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
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H A D | SIRegisterInfo.cpp | 48 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const { 49 return getEncodingValue(Reg) & 0xff; 52 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { 53 assert(!TargetRegisterInfo::isVirtualRegister(Reg)); 65 if (BaseClass->contains(Reg)) { 122 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg, argument 125 unsigned Index = getHWRegIndex(Reg);
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H A D | R600RegisterInfo.cpp | 61 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const { 62 return GET_REG_INDEX(getEncodingValue(Reg)); 78 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const { 79 assert(!TargetRegisterInfo::isVirtualRegister(Reg)); 81 switch (Reg) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterPressure.h | 42 /// \param Reg is either a virtual register number or register unit number. 43 void increase(unsigned Reg, const TargetRegisterInfo *TRI, 49 /// \param Reg is either a virtual register number or register unit number. 50 void decrease(unsigned Reg, const TargetRegisterInfo *TRI, 215 bool contains(unsigned Reg) const { 216 if (TargetRegisterInfo::isVirtualRegister(Reg)) 217 return VirtRegs.count(Reg); 218 return PhysRegs.count(Reg); 221 bool insert(unsigned Reg) { 222 if (TargetRegisterInfo::isVirtualRegister(Reg)) [all...] |
H A D | FunctionLoweringInfo.h | 154 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { argument 155 if (!LiveOutRegInfo.inBounds(Reg)) 158 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 170 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth); 173 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, argument 179 LiveOutRegInfo.grow(Reg); 180 LiveOutInfo &LOI = LiveOutRegInfo[Reg]; 198 unsigned Reg = It->second; local 199 LiveOutRegInfo.grow(Reg); 200 LiveOutRegInfo[Reg] [all...] |
H A D | CallingConvLower.h | 258 bool isAllocated(unsigned Reg) const { 259 return UsedRegs[Reg/32] & (1 << (Reg&31)); 310 unsigned AllocateReg(unsigned Reg) { argument 311 if (isAllocated(Reg)) return 0; 312 MarkAllocated(Reg); 313 return Reg; 317 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument 318 if (isAllocated(Reg)) return 0; 319 MarkAllocated(Reg); 333 unsigned Reg = Regs[FirstUnalloc]; local 371 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | RegisterPressure.cpp | 151 const LiveRange *RegPressureTracker::getLiveRange(unsigned Reg) const { 152 if (TargetRegisterInfo::isVirtualRegister(Reg)) 153 return &LIS->getInterval(Reg); 154 return LIS->getCachedRegUnit(Reg); 294 unsigned Reg = P.LiveOutRegs[i]; local 295 if (TargetRegisterInfo::isVirtualRegister(Reg) 296 && !RPTracker.hasUntiedDef(Reg)) { 297 increaseSetPressure(LiveThruPressure, MRI->getPressureSets(Reg)); 343 void pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &RegUnits) { argument 344 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 431 discoverLiveIn(unsigned Reg) argument 442 discoverLiveOut(unsigned Reg) argument 501 unsigned Reg = RegOpers.Defs[i]; local 526 unsigned Reg = RegOpers.Uses[i]; local 545 unsigned Reg = RegOpers.Defs[i]; local 581 unsigned Reg = RegOpers.Uses[i]; local 606 unsigned Reg = RegOpers.Defs[i]; local 721 unsigned Reg = RegOpers.Defs[i]; local 738 unsigned Reg = RegOpers.Uses[i]; local 882 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument 919 unsigned Reg = RegOpers.Uses[i]; local [all...] |
H A D | MachineSink.cpp | 90 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, 95 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, 147 MachineSinking::AllUsesDominatedByBlock(unsigned Reg, argument 152 assert(TargetRegisterInfo::isVirtualRegister(Reg) && 156 if (MRI->use_nodbg_empty(Reg)) 175 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { 188 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { 305 unsigned Reg = MO.getReg(); local 306 if (Reg == 0) 311 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 440 isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *SuccToSinkTo) argument 493 unsigned Reg = MO.getReg(); local 621 unsigned Reg = MO.getReg(); local [all...] |
H A D | RegisterScavenging.cpp | 34 void RegScavenger::setUsed(unsigned Reg) { argument 35 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 40 bool RegScavenger::isAliasUsed(unsigned Reg) const { 41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 42 if (isUsed(*AI, *AI == Reg)) 50 I->Reg = 0; 107 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { argument 108 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 133 unsigned Reg = MO.getReg(); local 134 if (!Reg || TargetRegisterInf 205 unsigned Reg = MO.getReg(); local [all...] |
H A D | RegAllocFast.cpp | 203 // Find the location Reg would belong... 703 unsigned Reg = MO.getReg(); local 704 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 707 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { 708 if (ThroughRegs.insert(Reg)) 709 DEBUG(dbgs() << ' ' << PrintReg(Reg)); 719 unsigned Reg = MO.getReg(); local 720 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 721 markRegUsedInInstr(Reg); 733 unsigned Reg = MO.getReg(); local 758 unsigned Reg = MO.getReg(); local 774 unsigned Reg = MO.getReg(); local 849 unsigned Reg = MO.getReg(); local 915 unsigned Reg = MO.getReg(); local 965 unsigned Reg = MO.getReg(); local 987 unsigned Reg = MO.getReg(); local 1016 unsigned Reg = MO.getReg(); local [all...] |
H A D | MachineLICM.cpp | 178 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the 180 void AddToLiveIns(unsigned Reg); 198 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg' 202 unsigned Reg) const; 248 unsigned Reg, unsigned OpIdx, 437 unsigned Reg = MO.getReg(); local 438 if (!Reg) 440 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 444 if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobber 523 unsigned Reg = *I; local 544 unsigned Reg = MO.getReg(); local 573 unsigned Reg = MO.getReg(); local 590 AddToLiveIns(unsigned Reg) argument 783 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument 821 unsigned Reg = MO.getReg(); local 853 unsigned Reg = MO.getReg(); local 872 unsigned Reg = Defs.pop_back_val(); local 932 unsigned Reg = MO.getReg(); local 981 unsigned Reg = MO->getReg(); local 1054 unsigned Reg = DefMO.getReg(); local 1109 unsigned Reg = MO.getReg(); local 1186 unsigned Reg = MO.getReg(); local 1265 unsigned Reg = MRI->createVirtualRegister(RC); local 1355 unsigned Reg = MI->getOperand(Idx).getReg(); local 1369 unsigned Reg = MI->getOperand(Idx).getReg(); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 80 /// and the underlying object in Reg and Val respectively, if the function's 82 bool isCallViaRegister(MachineInstr &MI, unsigned &Reg, 94 void incCntAndSetReg(ValueType Entry, unsigned Reg); 117 /// Return type of register Reg. 118 static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) { argument 119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); 148 unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64; local 152 if (MO.isReg() && MO.getReg() == Reg) { 214 unsigned Reg; local 218 if (!isCallViaRegister(*I, Reg, Entr 246 isCallViaRegister(MachineInstr &MI, unsigned &Reg, ValueType &Val) const argument 288 unsigned Reg = ScopedHT.lookup(Entry).second; local 293 incCntAndSetReg(ValueType Entry, unsigned Reg) argument [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 71 bool contains(unsigned Reg) const { 72 unsigned InByte = Reg % 8; 73 unsigned Byte = Reg / 8; 329 unsigned getSubReg(unsigned Reg, unsigned Idx) const; 332 /// Reg so its sub-register of index SubIdx is Reg. 333 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 439 /// MCSubRegIterator enumerates all sub-registers of Reg. 440 /// If IncludeSelf is set, Reg itself is included in the list. 443 MCSubRegIterator(unsigned Reg, cons 494 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) argument 557 unsigned Reg; member in class:llvm::MCRegAliasIterator 565 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf) argument [all...] |
H A D | MCInstBuilder.h | 32 MCInstBuilder &addReg(unsigned Reg) { argument 33 Inst.addOperand(MCOperand::CreateReg(Reg));
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCNaCl.h | 22 bool baseRegNeedsLoadStoreMask(unsigned Reg);
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/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 76 bool contains(unsigned Reg) const { 77 return MC->contains(Reg); 160 /// For all Reg in SuperRC: 161 /// this->contains(Reg:Idx) 254 /// returns true if Reg is in the range used for stack slots. 260 static bool isStackSlot(unsigned Reg) { argument 261 return int(Reg) >= (1 << 30); 266 static int stackSlot2Index(unsigned Reg) { argument 267 assert(isStackSlot(Reg) && "Not a stack slot"); 268 return int(Reg 280 isPhysicalRegister(unsigned Reg) argument 287 isVirtualRegister(unsigned Reg) argument 294 virtReg2Index(unsigned Reg) argument 896 unsigned Reg; member in class:llvm::TargetRegisterInfo::PrintReg [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { argument 40 switch (Reg) { 53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { argument 55 switch (Reg) { 64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { argument 66 switch (Reg) { 75 static inline bool isCalleeSavedRegister(unsigned Reg, argument 78 if (Reg == CSRegs[i]) 138 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 164 bool isLowRegister(unsigned Reg) cons [all...] |
/external/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 101 RegOp Reg; member in union:__anon25306::SystemZOperand::__anon25307 135 Op->Reg.Kind = Kind; 136 Op->Reg.Num = Num; 178 return Kind == KindReg && Reg.Kind == RegKind; 182 return Reg.Num; 311 bool parseRegister(Register &Reg); 313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, 419 bool SystemZAsmParser::parseRegister(Register &Reg) { argument 420 Reg.StartLoc = Parser.getTok().getLoc(); 429 return Error(Reg 460 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) argument 512 Register Reg; local 528 Register Reg; local 585 Register Reg; local 652 Register Reg; local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 54 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset; 97 unsigned Reg = CSRegs[I]; local 98 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) { 140 unsigned Reg = CSI[I].getReg(); local 141 if (SystemZ::GR64BitRegClass.contains(Reg)) { 142 unsigned Offset = RegSpillOffsets[Reg]; 145 LowGPR = Reg; 161 unsigned Reg = SystemZ::ArgGPRs[FirstGPR]; local 162 unsigned Offset = RegSpillOffsets[Reg]; 186 unsigned Reg = CSI[I].getReg(); local 199 unsigned Reg = CSI[I].getReg(); local 226 unsigned Reg = CSI[I].getReg(); local 256 unsigned Reg = CSI[I].getReg(); local 282 emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, unsigned Reg, int64_t NumBytes, const TargetInstrInfo *TII) argument 335 unsigned Reg = Save.getReg(); local 382 unsigned Reg = Save.getReg(); local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 63 unsigned Reg, unsigned FrameReg, int Offset ) { 70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) 94 unsigned Reg, unsigned FrameReg, 106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) 113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) 130 unsigned Reg, int Offset) { 140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 61 InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset ) argument 92 InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS ) argument 128 InsertSPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset) argument 161 InsertSPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset, RegScavenger *RS ) argument 305 unsigned Reg = MI.getOperand(0).getReg(); local [all...] |
H A D | XCoreFrameToArgsOffsetElim.cpp | 55 unsigned Reg = OldInst->getOperand(0).getReg(); local 56 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
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/external/qemu/target-i386/ |
H A D | ops_sse.h | 21 #define Reg MMXReg macro 29 #define Reg XMMReg macro 38 void glue(helper_psrlw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) 62 void glue(helper_psraw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) 83 void glue(helper_psllw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) 107 void glue(helper_psrld, SUFFIX)(CPUX86State *env, Reg *d, Reg * 2297 #undef Reg macro [all...] |
/external/compiler-rt/lib/asan/tests/ |
H A D | asan_asm_test.cc | 34 #define DECLARE_ASM_WRITE(Type, Size, Mov, Reg) \ 39 : [ptr] "r" (ptr), [val] Reg (val) \ 44 #define DECLARE_ASM_READ(Type, Size, Mov, Reg) \ 49 : [res] Reg (res) \ 67 #define DECLARE_ASM_WRITE(Type, Size, Mov, Reg) \ 72 : [ptr] "r" (ptr), [val] Reg (val) \ 77 #define DECLARE_ASM_READ(Type, Size, Mov, Reg) \ 82 : [res] Reg (res) \
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonVarargsCallingConvention.h | 56 if (unsigned Reg = State.AllocateReg(RegList1, 6)) { 57 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg, 68 if (unsigned Reg = State.AllocateReg(RegList2, 3)) { 69 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg, 112 if (unsigned Reg = State.AllocateReg(RegList1, 6)) { 113 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg, 124 if (unsigned Reg = State.AllocateReg(RegList2, 3)) { 125 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 44 unsigned Reg; member in union:llvm::X86AddressMode::__anon25357 57 Base.Reg = 0; 65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, 91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument 93 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction. 94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); 104 /// [Reg + Offset], i.e., one with no scale or index, but with a 109 unsigned Reg, bool isKill, int Offset) { 110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 114 /// [Reg 108 addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) argument [all...] |