Searched refs:Implicit (Results 1 - 25 of 34) sorted by relevance

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/external/clang/include/clang/AST/
H A DAttr.h53 bool Implicit : 1;
78 Inherited(false), IsPackExpansion(false), Implicit(false) {}
97 bool isImplicit() const { return Implicit; }
98 void setImplicit(bool I) { Implicit = I; }
H A DLambdaCapture.h54 /// \param Implicit Whether the capture was implicit or explicit.
62 LambdaCapture(SourceLocation Loc, bool Implicit, LambdaCaptureKind Kind,
H A DDeclBase.h248 /// Implicit - Whether this declaration was implicitly generated by
250 unsigned Implicit : 1;
317 HasAttrs(false), Implicit(false), Used(false), Referenced(false),
327 HasAttrs(false), Implicit(false), Used(false), Referenced(false),
496 bool isImplicit() const { return Implicit; }
497 void setImplicit(bool I = true) { Implicit = I; }
H A DExprCXX.h483 /// \brief Implicit construction of a std::initializer_list<T> object from an
765 bool Implicit : 1;
775 Loc(L), Implicit(isImplicit) { }
785 bool isImplicit() const { return Implicit; }
786 void setImplicit(bool I) { Implicit = I; }
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h32 Implicit = 0x4, enumerator in enum:llvm::RegState::__anon24650
40 ImplicitDefine = Implicit | Define,
41 ImplicitKill = Implicit | Kill
70 flags & RegState::Implicit,
392 return B ? RegState::Implicit : 0;
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600ISelLowering.cpp173 .addReg(t0, RegState::Implicit)
174 .addReg(t1, RegState::Implicit);
195 .addReg(t0, RegState::Implicit)
196 .addReg(t1, RegState::Implicit);
H A DR600InstrInfo.cpp63 .addReg(DestReg, RegState::Define | RegState::Implicit);
463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
/external/llvm/lib/Target/R600/
H A DSILowerControlFlow.cpp414 .addReg(AMDGPU::M0, RegState::Implicit)
415 .addReg(Vec, RegState::Implicit);
436 .addReg(AMDGPU::M0, RegState::Implicit)
437 .addReg(Dst, RegState::Implicit);
H A DR600InstrInfo.cpp73 RegState::Define | RegState::Implicit);
1033 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1041 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1143 RegState::Implicit | RegState::Kill);
1176 RegState::Implicit | RegState::Kill);
H A DR600ISelLowering.cpp374 .addReg(T0, RegState::Implicit)
375 .addReg(T1, RegState::Implicit);
476 .addReg(T0, RegState::Implicit)
477 .addReg(T1, RegState::Implicit);
554 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
H A DSIInstrInfo.cpp167 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
1056 .addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
1064 .addReg(AMDGPU::VCC, RegState::Implicit);
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ISelLowering.cpp173 .addReg(t0, RegState::Implicit)
174 .addReg(t1, RegState::Implicit);
195 .addReg(t0, RegState::Implicit)
196 .addReg(t1, RegState::Implicit);
H A DR600InstrInfo.cpp63 .addReg(DestReg, RegState::Define | RegState::Implicit);
463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp1231 MIB.addReg(SrcRegS, RegState::Implicit);
4115 MIB.addReg(SrcReg, RegState::Implicit);
4146 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4148 MIB.addReg(ImplicitSReg, RegState::Implicit);
4181 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4182 MIB.addReg(SrcReg, RegState::Implicit);
4184 MIB.addReg(ImplicitSReg, RegState::Implicit);
4219 NewMIB.addReg(SrcReg, RegState::Implicit);
4238 MIB.addReg(SrcReg, RegState::Implicit);
4242 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
[all...]
H A DARMExpandPseudoInsts.cpp487 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
614 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
H A DARMFrameLowering.cpp321 .addReg(ARM::R4, RegState::Implicit)
333 .addReg(ARM::R4, RegState::Implicit)
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp111 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
525 // FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to
537 SrcReg, RegState::Implicit);
H A DMipsSEISelDAGToDAG.cpp49 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
/external/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp1667 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
1668 .addReg(X86::EDX, RegState::Define | RegState::Implicit)
1669 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
H A DX86FrameLowering.cpp711 .addReg(StackPtr, RegState::Define | RegState::Implicit)
712 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
H A DX86FastISel.cpp1083 MIB.addReg(RetRegs[i], RegState::Implicit);
3017 MIB.addReg(X86::EBX, RegState::Implicit);
3020 MIB.addReg(X86::AL, RegState::Implicit);
3024 MIB.addReg(RegArgs[i], RegState::Implicit);
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1279 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1303 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1521 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
1530 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
H A DAArch64FastISel.cpp1410 MIB.addReg(RegArgs[i], RegState::Implicit);
1641 MIB.addReg(RetRegs[i], RegState::Implicit);
/external/clang/lib/AST/
H A DExprCXX.cpp888 LambdaCapture::LambdaCapture(SourceLocation Loc, bool Implicit, argument
894 if (Implicit)
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1499 MIB.addReg(RegArgs[II], RegState::Implicit);
1616 MIB.addReg(RetRegs[i], RegState::Implicit);

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