/external/chromium_org/third_party/skia/include/core/ |
H A D | SkChecksum.h | 30 ROTL = sizeof(uintptr_t) * 8 - ROTR, enumerator in enum:SkChecksum::__anon14334 35 return ((total >> ROTR) | (total << ROTL)) ^ value;
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/external/skia/include/core/ |
H A D | SkChecksum.h | 30 ROTL = sizeof(uintptr_t) * 8 - ROTR, enumerator in enum:SkChecksum::__anon29600 35 return ((total >> ROTR) | (total << ROTL)) ^ value;
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/external/chromium_org/net/http/ |
H A D | md4.cc | 65 #define ROTL(x,n) (((x) << (n)) | ((x) >> (0x20 - n))) macro 68 #define RD1(a,b,c,d,k,s) a += F(b,c,d) + X[k]; a = ROTL(a,s) 71 #define RD2(a,b,c,d,k,s) a += G(b,c,d) + X[k] + 0x5A827999; a = ROTL(a,s) 74 #define RD3(a,b,c,d,k,s) a += H(b,c,d) + X[k] + 0x6ED9EBA1; a = ROTL(a,s)
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, local 188 return ROTL;
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H A D | SystemZISelDAGToDAG.cpp | 750 case ISD::ROTL: { 1073 case ISD::ROTL:
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 43 setOperationAction(ISD::ROTL, MVT::i32, Custom); 250 case ISD::ROTL: return LowerROTL(Op, DAG);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 43 setOperationAction(ISD::ROTL, MVT::i32, Custom); 250 case ISD::ROTL: return LowerROTL(Op, DAG);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 180 case ISD::ROTL: return "rotl";
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H A D | LegalizeVectorOps.cpp | 256 case ISD::ROTL:
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H A D | DAGCombiner.cpp | 1224 case ISD::ROTL: return visitRotate(N); 3219 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3220 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt); 3597 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3640 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3683 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL); 3688 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
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H A D | SelectionDAG.cpp | 2457 case ISD::ROTL: 3042 case ISD::ROTL: 3184 case ISD::ROTL: 6452 case ISD::ROTL:
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H A D | LegalizeIntegerTypes.cpp | 837 case ISD::ROTL: 2490 case ISD::ROTL:
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 165 setOperationAction(ISD::ROTL, MVT::i64, Legal); 168 setOperationAction(ISD::ROTL, MVT::i64, Expand); 172 setOperationAction(ISD::ROTL, MVT::i32, Legal); 175 setOperationAction(ISD::ROTL, MVT::i32, Expand); 179 setOperationAction(ISD::ROTL, MVT::i16, Expand); 181 setOperationAction(ISD::ROTL, MVT::i8, Expand);
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/external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/ |
H A D | ppc.pl | 126 $ROTL= "rotlwi"; # rotate left by immediate 150 $ROTL= "rotldi"; # rotate left by immediate 1713 $ROTL r3,r11,`$BITS/2` # rotate by $BITS/2 and store in r3
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/external/openssl/crypto/bn/asm/ |
H A D | ppc.pl | 126 $ROTL= "rotlwi"; # rotate left by immediate 150 $ROTL= "rotldi"; # rotate left by immediate 1713 $ROTL r3,r11,`$BITS/2` # rotate by $BITS/2 and store in r3
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 98 setOperationAction(ISD::ROTL, MVT::i8, Expand); 100 setOperationAction(ISD::ROTL, MVT::i16, Expand);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 397 } else if (Opcode == ISD::ROTL) { 1162 N->getOperand(0).getOpcode() != ISD::ROTL) {
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 269 // The hardware supports 32-bit ROTR, but not ROTL. 270 setOperationAction(ISD::ROTL, MVT::i32, Expand); 271 setOperationAction(ISD::ROTL, MVT::i64, Expand); 298 setOperationAction(ISD::ROTL, VT, Expand);
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/external/valgrind/main/VEX/priv/ |
H A D | guest_ppc_toIR.c | 1521 // ROTL(src32/64, rot_amt5/6) 1522 static IRExpr* /* :: Ity_I32/64 */ ROTL ( IRExpr* src, function 4505 // tmp32 = (ROTL(rS_Lo32, Imm) 4508 r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) ); 4518 // rA = (ROTL(rS, Imm) & mask) | (rA & ~mask); 4520 r = ROTL(mkexpr(rS), mkU8(sh_imm)); 4540 // tmp32 = (ROTL(rS_Lo32, Imm) 4542 r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) ); 4570 // rA = ROTL(rS, Imm) & mask 4572 ROTL(mkexp [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1412 setOperationAction(ISD::ROTL, MVT::i32, Expand);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 113 setOperationAction(ISD::ROTL , MVT::i32, Expand);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 315 setOperationAction(ISD::ROTL, MVT::i32, Expand); 316 setOperationAction(ISD::ROTL, MVT::i64, Expand);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1476 setOperationAction(ISD::ROTL , MVT::i64, Expand); 1530 setOperationAction(ISD::ROTL , MVT::i32, Expand);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 231 setOperationAction(ISD::ROTL, MVT::i32, Expand); 232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
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