Searched refs:ROTL (Results 1 - 25 of 29) sorted by relevance

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/external/chromium_org/third_party/skia/include/core/
H A DSkChecksum.h30 ROTL = sizeof(uintptr_t) * 8 - ROTR, enumerator in enum:SkChecksum::__anon14334
35 return ((total >> ROTR) | (total << ROTL)) ^ value;
/external/skia/include/core/
H A DSkChecksum.h30 ROTL = sizeof(uintptr_t) * 8 - ROTR, enumerator in enum:SkChecksum::__anon29600
35 return ((total >> ROTR) | (total << ROTL)) ^ value;
/external/chromium_org/net/http/
H A Dmd4.cc65 #define ROTL(x,n) (((x) << (n)) | ((x) >> (0x20 - n))) macro
68 #define RD1(a,b,c,d,k,s) a += F(b,c,d) + X[k]; a = ROTL(a,s)
71 #define RD2(a,b,c,d,k,s) a += G(b,c,d) + X[k] + 0x5A827999; a = ROTL(a,s)
74 #define RD3(a,b,c,d,k,s) a += H(b,c,d) + X[k] + 0x6ED9EBA1; a = ROTL(a,s)
/external/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, local
188 return ROTL;
H A DSystemZISelDAGToDAG.cpp750 case ISD::ROTL: {
1073 case ISD::ROTL:
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h311 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600ISelLowering.cpp43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
250 case ISD::ROTL: return LowerROTL(Op, DAG);
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ISelLowering.cpp43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
250 case ISD::ROTL: return LowerROTL(Op, DAG);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp180 case ISD::ROTL: return "rotl";
H A DLegalizeVectorOps.cpp256 case ISD::ROTL:
H A DDAGCombiner.cpp1224 case ISD::ROTL: return visitRotate(N);
3219 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3220 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3597 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3640 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3683 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3688 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
H A DSelectionDAG.cpp2457 case ISD::ROTL:
3042 case ISD::ROTL:
3184 case ISD::ROTL:
6452 case ISD::ROTL:
H A DLegalizeIntegerTypes.cpp837 case ISD::ROTL:
2490 case ISD::ROTL:
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp165 setOperationAction(ISD::ROTL, MVT::i64, Legal);
168 setOperationAction(ISD::ROTL, MVT::i64, Expand);
172 setOperationAction(ISD::ROTL, MVT::i32, Legal);
175 setOperationAction(ISD::ROTL, MVT::i32, Expand);
179 setOperationAction(ISD::ROTL, MVT::i16, Expand);
181 setOperationAction(ISD::ROTL, MVT::i8, Expand);
/external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/
H A Dppc.pl126 $ROTL= "rotlwi"; # rotate left by immediate
150 $ROTL= "rotldi"; # rotate left by immediate
1713 $ROTL r3,r11,`$BITS/2` # rotate by $BITS/2 and store in r3
/external/openssl/crypto/bn/asm/
H A Dppc.pl126 $ROTL= "rotlwi"; # rotate left by immediate
150 $ROTL= "rotldi"; # rotate left by immediate
1713 $ROTL r3,r11,`$BITS/2` # rotate by $BITS/2 and store in r3
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp98 setOperationAction(ISD::ROTL, MVT::i8, Expand);
100 setOperationAction(ISD::ROTL, MVT::i16, Expand);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp397 } else if (Opcode == ISD::ROTL) {
1162 N->getOperand(0).getOpcode() != ISD::ROTL) {
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp269 // The hardware supports 32-bit ROTR, but not ROTL.
270 setOperationAction(ISD::ROTL, MVT::i32, Expand);
271 setOperationAction(ISD::ROTL, MVT::i64, Expand);
298 setOperationAction(ISD::ROTL, VT, Expand);
/external/valgrind/main/VEX/priv/
H A Dguest_ppc_toIR.c1521 // ROTL(src32/64, rot_amt5/6)
1522 static IRExpr* /* :: Ity_I32/64 */ ROTL ( IRExpr* src, function
4505 // tmp32 = (ROTL(rS_Lo32, Imm)
4508 r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) );
4518 // rA = (ROTL(rS, Imm) & mask) | (rA & ~mask);
4520 r = ROTL(mkexpr(rS), mkU8(sh_imm));
4540 // tmp32 = (ROTL(rS_Lo32, Imm)
4542 r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) );
4570 // rA = ROTL(rS, Imm) & mask
4572 ROTL(mkexp
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/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1412 setOperationAction(ISD::ROTL, MVT::i32, Expand);
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp113 setOperationAction(ISD::ROTL , MVT::i32, Expand);
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp315 setOperationAction(ISD::ROTL, MVT::i32, Expand);
316 setOperationAction(ISD::ROTL, MVT::i64, Expand);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1476 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1530 setOperationAction(ISD::ROTL , MVT::i32, Expand);
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
232 setOperationAction(ISD::ROTL, MVT::i64, Expand);

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