/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 358 SmallVectorImpl<CCValAssign> &RVLocs, 364 std::reverse(RVLocs.begin(), RVLocs.end()); 529 SmallVector<CCValAssign, 16> RVLocs; local 537 getTargetMachine(), RVLocs, *DAG.getContext()); 540 AnalyzeReturnValues(CCInfo, RVLocs, Outs); 546 for (unsigned i = 0; i != RVLocs.size(); ++i) { 547 CCValAssign &VA = RVLocs[i]; 721 SmallVector<CCValAssign, 16> RVLocs; local 723 getTargetMachine(), RVLocs, *DA 357 AnalyzeReturnValues(CCState &State, SmallVectorImpl<CCValAssign> &RVLocs, const SmallVectorImpl<ArgT> &Args) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1064 const SmallVectorImpl<CCValAssign> &RVLocs, 1069 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1070 const CCValAssign &VA = RVLocs[i]; 1130 SmallVector<CCValAssign, 16> RVLocs; local 1133 getTargetMachine(), RVLocs, *DAG.getContext()); 1235 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); 1445 SmallVector<CCValAssign, 16> RVLocs; local 1446 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); 1467 SmallVector<CCValAssign, 16> RVLocs; local 1471 getTargetMachine(), RVLocs, *DA 1063 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 2028 SmallVector<CCValAssign, 16> RVLocs; local 2029 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 2033 if (RVLocs.size() == 2 && RetVT == MVT::f64) { 2036 MVT DestVT = RVLocs[0].getValVT(); 2041 .addReg(RVLocs[0].getLocReg()) 2042 .addReg(RVLocs[1].getLocReg())); 2044 UsedRegs.push_back(RVLocs[0].getLocReg()); 2045 UsedRegs.push_back(RVLocs[1].getLocReg()); 2050 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); 2051 MVT CopyVT = RVLocs[ 2194 SmallVector<CCValAssign, 16> RVLocs; local 2305 SmallVector<CCValAssign, 16> RVLocs; local [all...] |
H A D | ARMISelLowering.cpp | 1258 SmallVector<CCValAssign, 16> RVLocs; local 1260 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1266 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1267 CCValAssign VA = RVLocs[i]; 1285 VA = RVLocs[++i]; // skip ahead to next loc 1299 VA = RVLocs[++i]; // skip ahead to next loc 1303 VA = RVLocs[++i]; // skip ahead to next loc 2040 SmallVector<CCValAssign, 16> RVLocs; local 2041 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); 2086 SmallVector<CCValAssign, 16> RVLocs; local [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 190 SmallVector<CCValAssign, 16> RVLocs; local 194 DAG.getTarget(), RVLocs, *DAG.getContext()); 205 for (unsigned i = 0; i != RVLocs.size(); ++i) { 206 CCValAssign &VA = RVLocs[i]; 250 SmallVector<CCValAssign, 16> RVLocs; local 254 DAG.getTarget(), RVLocs, *DAG.getContext()); 267 for (unsigned i = 0; i != RVLocs.size(); ++i) { 268 CCValAssign &VA = RVLocs[i]; 296 if (i+1 < RVLocs.size() && RVLocs[ 936 SmallVector<CCValAssign, 16> RVLocs; local 1257 SmallVector<CCValAssign, 16> RVLocs; local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 322 SmallVector<CCValAssign, 16> RVLocs; local 326 getTargetMachine(), RVLocs, *DAG.getContext()); 335 for (unsigned i = 0; i != RVLocs.size(); ++i) { 336 CCValAssign &VA = RVLocs[i]; 373 SmallVector<CCValAssign, 16> RVLocs; local 376 getTargetMachine(), RVLocs, *DAG.getContext()); 381 for (unsigned i = 0; i != RVLocs.size(); ++i) { 383 RVLocs[i].getLocReg(), 384 RVLocs[i].getValVT(), InFlag).getValue(1);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2612 SmallVector<CCValAssign, 16> RVLocs; local 2614 getTargetMachine(), RVLocs, *DAG.getContext()); 2622 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2623 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2624 RVLocs[i].getLocVT(), InFlag); 2628 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2629 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); 2796 SmallVector<CCValAssign, 16> RVLocs; local 2798 RVLocs, Contex 2810 SmallVector<CCValAssign, 16> RVLocs; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 3057 SmallVector<CCValAssign, 16> RVLocs; local 3058 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs, 3062 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3063 EVT CopyVT = RVLocs[i].getValVT(); 3069 if ((RVLocs[i].getLocReg() == X86::ST0 || 3070 RVLocs[i].getLocReg() == X86::ST1)) { 3071 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { 3080 CopyReg).addReg(RVLocs[i].getLocReg()); 3081 UsedRegs.push_back(RVLocs[i].getLocReg()); 3084 if (CopyVT != RVLocs[ [all...] |
H A D | X86ISelLowering.cpp | 1853 SmallVector<CCValAssign, 16> RVLocs; local 1855 RVLocs, Context); 1873 SmallVector<CCValAssign, 16> RVLocs; local 1875 RVLocs, *DAG.getContext()); 1886 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1887 CCValAssign &VA = RVLocs[i]; 2043 SmallVector<CCValAssign, 16> RVLocs; local 2046 DAG.getTarget(), RVLocs, *DAG.getContext()); 2050 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2051 CCValAssign &VA = RVLocs[ 3230 SmallVector<CCValAssign, 16> RVLocs; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 1320 SmallVector<CCValAssign, 16> RVLocs; local 1321 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 1323 CCValAssign &VA = RVLocs[0]; 1324 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); 1410 SmallVector<CCValAssign, 16> RVLocs; local 1411 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 1413 if (RVLocs.size() > 1)
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H A D | PPCISelLowering.cpp | 3524 SmallVector<CCValAssign, 16> RVLocs; local 3526 getTargetMachine(), RVLocs, *DAG.getContext()); 3530 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 3531 CCValAssign &VA = RVLocs[i]; 4753 SmallVector<CCValAssign, 16> RVLocs; local 4755 RVLocs, Context); 4766 SmallVector<CCValAssign, 16> RVLocs; local 4768 getTargetMachine(), RVLocs, *DAG.getContext()); 4775 for (unsigned i = 0; i != RVLocs.size(); ++i) { 4776 CCValAssign &VA = RVLocs[ [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 1285 SmallVector<CCValAssign, 16> RVLocs; local 1286 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context); 1290 if (RVLocs.size() != 1) 1294 MVT CopyVT = RVLocs[0].getValVT(); 1298 ResultReg).addReg(RVLocs[0].getLocReg()); 1299 UsedRegs.push_back(RVLocs[0].getLocReg());
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H A D | AArch64ISelLowering.cpp | 1918 SmallVector<CCValAssign, 16> RVLocs; local 1920 getTargetMachine(), RVLocs, *DAG.getContext()); 1924 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1925 CCValAssign VA = RVLocs[i]; 2471 SmallVector<CCValAssign, 16> RVLocs; local 2472 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); 2485 SmallVector<CCValAssign, 16> RVLocs; local 2487 getTargetMachine(), RVLocs, *DAG.getContext()); 2493 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size(); 2495 CCValAssign &VA = RVLocs[ [all...] |