Searched refs:Rn (Results 1 - 25 of 30) sorted by relevance

12

/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1234 // Writeback not allowed if Rn is in the target list.
1327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1473 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1533 if (writeback && (Rn == 15 || Rn == Rt))
1578 unsigned Rn local
1623 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1813 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1844 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
1866 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2097 unsigned Rn = fieldFromInstruction(Insn, 0, 4); local
2126 unsigned Rn = fieldFromInstruction(Val, 13, 4); local
2144 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
2242 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2567 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2837 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2884 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2932 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
2967 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3110 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3192 unsigned Rn = fieldFromInstruction(Val, 0, 3); local
3207 unsigned Rn = fieldFromInstruction(Val, 0, 3); local
3239 unsigned Rn = fieldFromInstruction(Val, 6, 4); local
3268 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3338 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3402 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3467 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3565 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
3580 unsigned Rn = fieldFromInstruction(Val, 8, 4); local
3608 unsigned Rn = fieldFromInstruction(Val, 9, 4); local
3655 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3715 unsigned Rn = fieldFromInstruction(Val, 13, 4); local
3840 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
3987 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4009 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4032 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4057 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4085 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4110 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4135 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4202 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4268 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4335 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4399 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4469 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4533 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4614 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4760 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4797 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4855 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local
4942 unsigned Rn = fieldFromInstruction(Val, 16, 4); local
[all...]
/external/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp943 // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
956 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
969 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1906 uint32_t Rn; // This function assumes Rn is the SP, but we should verify that. local
1915 Rn = Bits32 (opcode, 19, 16);
1917 if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP.
1924 if (wback && ((Rn == 15) || (Rn
2391 uint32_t Rn; // the base register which contains the address of the table of branch lengths local
2530 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
2582 uint32_t Rd, Rn; local
2642 uint32_t Rd, Rn, Rm; local
2725 uint32_t Rn; // the first operand local
2776 uint32_t Rn; // the first operand local
2845 uint32_t Rn; // the first operand local
2900 uint32_t Rn; // the first operand local
3279 uint32_t Rn; // the first operand register local
3536 addr_t Rn = ReadCoreReg (n, &success); local
3674 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
3785 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
3878 uint32_t Rn; // the base register local
4214 addr_t Rn = ReadCoreReg (n, &success); local
4365 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
4490 addr_t Rn = ReadCoreReg (n, &success); local
5255 uint32_t Rd, Rn; local
5325 uint32_t Rd, Rn, Rm; local
5476 uint32_t Rd, Rn; local
5550 uint32_t Rd, Rn, Rm; local
5641 uint32_t Rd, Rn; local
5713 uint32_t Rd, Rn, Rm; local
6215 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
6592 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
6876 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
7033 uint64_t Rn = ReadCoreReg (n, &success); local
7283 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
7432 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
8191 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); local
8275 uint32_t Rd, Rn; local
8350 uint32_t Rd, Rn, Rm; local
8442 uint32_t Rd, Rn; local
8516 uint32_t Rd, Rn, Rm; local
8605 uint32_t Rn; // the first operand local
8678 uint32_t Rn; // the first operand local
8757 uint32_t Rn; // the first operand local
8817 uint32_t Rn; // the first operand local
8886 uint32_t Rn; // the first operand local
8954 uint32_t Rn; // the first operand local
9035 uint32_t Rn; // the first operand local
9129 uint32_t Rn; // the first operand local
9191 uint32_t Rn; local
9249 uint32_t Rn, Rm; local
9316 uint32_t Rn; local
9373 uint32_t Rn, Rm; local
9816 uint32_t Rn = ReadCoreReg (n, &success); local
9910 uint32_t Rn = ReadCoreReg (n, &success); local
10005 uint32_t Rn = ReadCoreReg (n, &success); local
10152 uint32_t Rn = ReadCoreReg (n, &success); local
10274 uint32_t Rn = ReadCoreReg (n, &success); local
10425 uint32_t Rn = ReadCoreReg (n, &success); local
10557 uint32_t Rn = ReadCoreReg (n, &success); local
10723 uint32_t Rn = ReadCoreReg (n, &success); local
10916 uint32_t Rn = ReadCoreReg (n, &success); local
11070 uint32_t Rn = ReadCoreReg (n, &success); local
11208 uint32_t Rn = ReadCoreReg (n, &success); local
11379 uint32_t Rn = ReadCoreReg (n, &success); local
11551 uint32_t Rn = ReadCoreReg (n, &success); local
11718 uint32_t Rn = ReadCoreReg (n, &success); local
11890 uint32_t Rn = ReadCoreReg (n, &success); local
12016 uint32_t Rn = ReadCoreReg (n, &success); local
12167 uint32_t Rn = ReadCoreReg (n, &success); local
[all...]
/external/chromium_org/v8/src/arm64/
H A Dassembler-arm64.cc652 instr->following()->Rn() == xzr.code()));
695 Emit(BLR | Rn(xzr));
728 Emit(BR | Rn(xn));
738 Emit(BLR | Rn(xn));
745 Emit(RET | Rn(xn));
1017 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
1026 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
1035 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
1044 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
1058 Rn(r
[all...]
H A Ddisasm-arm64.h55 return (instr->Rn() == kZeroRegCode);
H A Dsimulator-arm64.cc872 reg<T>(instr->Rn()),
947 T op1 = reg<T>(instr->Rn());
1215 Instruction* target = reg<Instruction*>(instr->Rn());
1219 if (instr->Rn() == 31) {
1274 reg<T>(instr->Rn(), instr->RnMode()),
1281 reg<T>(instr->Rn(), instr->RnMode()),
1366 T op1 = reg<T>(instr->Rn());
1412 T op1 = reg<T>(instr->Rn());
1465 unsigned addr_reg = instr->Rn();
1564 unsigned addr_reg = instr->Rn();
[all...]
H A Dinstrument-arm64.cc247 (instr->Rd() == 31) && (instr->Rn() == 31)) {
460 (instr->Rd() == 31) && (instr->Rn() == 31)) {
H A Ddisasm-arm64.cc101 const char *form = "'Rd, 'Rn, 'Rm'HDP";
102 const char *form_cmp = "'Rn, 'Rm'HDP";
185 const char *form = "'Rd, 'Rn, 'Rm";
221 const char *form = "'Rds, 'Rn, 'ITri";
250 form = "'Rn, 'ITri";
293 const char *form = "'Rd, 'Rn, 'Rm'HLo";
311 form = "'Rn, 'Rm'HLo";
342 const char *form = "'Rn, 'Rm, 'INzcv, 'Cond";
357 const char *form = "'Rn, 'IP, 'INzcv, 'Cond";
372 bool rn_is_rm = (instr->Rn()
[all...]
H A Dassembler-arm64-inl.h567 Emit(BLR | Rn(xzr));
837 i2->IsBranchAndLinkToRegister() && (i2->Rn() == ip0.code());
H A Dconstants-arm64.h124 V_(Rn, 9, 5, Bits) /* First source register. */ \
/external/vixl/src/a64/
H A Dassembler-a64.cc433 Emit(BR | Rn(xn));
439 Emit(BLR | Rn(xn));
445 Emit(RET | Rn(xn));
705 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
714 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
723 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
732 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
744 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
755 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
766 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(r
[all...]
H A Ddisasm-a64.h74 return (instr->Rn() == kZeroRegCode);
H A Dsimulator-a64.cc543 Instruction* target = Instruction::Cast(xreg(instr->Rn()));
599 reg(reg_size, instr->Rn(), instr->RnMode()),
607 reg(reg_size, instr->Rn(), instr->RnMode()),
656 reg(reg_size, instr->Rn()),
684 int64_t op1 = reg(reg_size, instr->Rn());
723 int64_t op1 = reg(reg_size, instr->Rn());
777 uint8_t* address = AddressModeHelper(instr->Rn(), offset, addrmode);
844 uint8_t* address = AddressModeHelper(instr->Rn(), offset, addrmode);
1059 uint64_t new_val = xreg(instr->Rn());
1082 unsigned src = instr->Rn();
[all...]
H A Ddisasm-a64.cc108 const char *form = "'Rd, 'Rn, 'Rm'HDP";
109 const char *form_cmp = "'Rn, 'Rm'HDP";
192 const char *form = "'Rd, 'Rn, 'Rm";
228 const char *form = "'Rds, 'Rn, 'ITri";
257 form = "'Rn, 'ITri";
300 const char *form = "'Rd, 'Rn, 'Rm'HLo";
318 form = "'Rn, 'Rm'HLo";
349 const char *form = "'Rn, 'Rm, 'INzcv, 'Cond";
364 const char *form = "'Rn, 'IP, 'INzcv, 'Cond";
379 bool rn_is_rm = (instr->Rn()
[all...]
H A Dconstants-a64.h50 V_(Rn, 9, 5, Bits) /* First source register. */ \
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp670 unsigned Rn = fieldFromInstruction(Insn, 5, 5); local
675 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
678 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
761 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
789 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
810 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
856 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
907 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
917 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
975 DecodeGPR64spRegisterClass(Inst, Rn, Add
1102 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1177 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1306 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1363 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
1469 unsigned Rn = fieldFromInstruction(insn, 5, 5); local
[all...]
/external/chromium_org/v8/src/arm/
H A Ddisasm-arm.cc91 void FormatNeonMemory(int Rn, int align, int Rm);
303 if (format[1] == 'n') { // 'rn: Rn register
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { argument
418 "[r%d", Rn);
712 // Rn field to encode it.
717 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
718 // Rn field to encode the Rd register and the Rd field to encode
719 // the Rn register.
723 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
724 // Rn fiel
1570 int Rn = instr->VnValue(); local
1583 int Rn = instr->VnValue(); local
1600 int Rn = instr->Bits(19, 16); local
[all...]
H A Dsimulator-arm.cc2017 // Rn field to encode it.
2030 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
2031 // Rn field to encode the Rd register and the Rd field to encode
2032 // the Rn register.
2046 // when referring to the target registers. They are mapped to the Rn
2049 // RdHi == Rn (This is confusingly stored in variable rd here
2051 // Rn field to encode the Rd register. Good luck figuring
3498 int Rn = instr->VnValue(); local
3501 int32_t address = get_register(Rn);
3531 set_register(Rn, addres
3539 int Rn = instr->VnValue(); local
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp848 // [Rn, Rm]
850 // {2-0} = Rn
853 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); local
855 return (Rm << 3) | Rn;
871 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
955 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1060 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local
1071 // {16-13} = Rn
1079 Binary |= Rn << 13;
1091 // {17-14} Rn
1096 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local
1172 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. local
1182 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local
1219 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local
[all...]
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3291 unsigned Rn = Inst.getOperand(3).getReg(); local
3292 if (RI->isSubRegisterEq(Rn, Rt))
3295 if (RI->isSubRegisterEq(Rn, Rt2))
3337 unsigned Rn = Inst.getOperand(3).getReg(); local
3338 if (RI->isSubRegisterEq(Rn, Rt))
3341 if (RI->isSubRegisterEq(Rn, Rt2))
3369 unsigned Rn = Inst.getOperand(2).getReg(); local
3370 if (RI->isSubRegisterEq(Rn, Rt))
3388 unsigned Rn = Inst.getOperand(2).getReg(); local
3389 if (RI->isSubRegisterEq(Rn, R
[all...]
/external/qemu/disas/
H A Darm.c3454 unsigned int Rn = (given & 0x000f0000) >> 16; local
3462 func (stream, "[%s", arm_regnames[Rn]);
3465 else if (Rn == 15) /* 12-bit negative immediate offset */
3521 if (Rn == 15)
3535 unsigned int Rn = (given & 0x000f0000) >> 16; local
3538 func (stream, "[%s", arm_regnames[Rn]);
/external/llvm/test/MC/AArch64/
H A Darm64-diags.s156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
H A Darm64-aliases.s25 ; ORR Rd, Rn, Rn is a MOV
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2742 unsigned Rn = MI->getOperand(2).getReg(); local
2746 return (Rt == Rn) ? 3 : 2;
2766 unsigned Rn = MI->getOperand(3).getReg(); local
2770 return (Rt == Rn) ? 4 : 3;
2775 unsigned Rn = MI->getOperand(3).getReg(); local
2776 return (Rt == Rn) ? 4 : 3;
2811 unsigned Rn = MI->getOperand(2).getReg(); local
2812 return (Rt == Rn) ? 3 : 2;
/external/valgrind/main/none/tests/arm/
H A Dvfp.stdout.exp871 vldr d9, [r6, #+4] :: Dd 0x0000011a 0x00000dd3 *(int*) (Rn + shift) 0x0dd3
872 vldr d16, [r9, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1
873 vldr d30, [r12] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2
874 vldr d22, [r9, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a
875 vldr d29, [r2, #-8] :: Dd 0x00000bb1 0x00000aa0 *(int*) (Rn + shift) 0x0aa0
876 vldr d8, [r8, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a
877 vldr d11, [r12, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1
878 vldr d18, [r3] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2
879 vldr d5, [r10, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a
880 vldr d17, [r10] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn
[all...]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4388 // If we have a three-operand form, make sure to set Rn to be the operand
5690 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); local
5693 if (Rn == Rt || Rn == Rt2)
5749 unsigned Rn = Inst.getOperand(0).getReg(); local
5754 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6176 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6194 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6259 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6281 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7684 unsigned Rn = Inst.getOperand(0).getReg(); local
7708 unsigned Rn = Inst.getOperand(0).getReg(); local
[all...]

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