Searched refs:Src0RC (Results 1 - 2 of 2) sorted by relevance
/external/llvm/lib/Target/R600/ |
H A D | SIFixSGPRCopies.cpp | 262 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; local 264 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); 267 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
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H A D | SIInstrInfo.cpp | 991 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); local 992 if (DstRC != Src0RC) { 1380 const TargetRegisterClass *Src0RC = Src0.isReg() ? local 1384 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); 1386 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 1396 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 1433 const TargetRegisterClass *Src0RC = Src0.isReg() ? local 1437 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); 1444 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, 1457 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, [all...] |
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