/external/libunwind/src/ia64/ |
H A D | Grbs.c | 128 unw_word_t nregs, bsp = c->bsp, curr = c->rbs_curr, n; local 149 nregs = rse_num_regs (bsp, c->rbs_area[curr].end); 151 if (regs_to_skip < nregs) 170 regs_to_skip -= nregs; 199 rbs_cover_and_flush (struct cursor *c, unw_word_t nregs, argument 209 c->bsp = rse_skip_regs (bsp, nregs); 215 if (likely (n >= nregs)) 232 nregs -= n; /* account for registers already on the rbs */ 234 assert (rse_skip_regs (c->bsp, -nregs) == rse_skip_regs (rbs->end, 0)); 239 nregs [all...] |
/external/elfutils/0.153/libdwfl/ |
H A D | dwfl_module_register_names.c | 74 int nregs = ebl_register_info (mod->ebl, -1, NULL, 0, local 77 for (int regno = 0; regno < nregs && likely (result == 0); ++regno)
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/ |
H A D | r600.h | 116 unsigned nregs; member in struct:r600_pipe_state 234 state->regs[state->nregs].value = value; 235 state->nregs++;
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H A D | r600_state_common.c | 465 for (int i = 0; i < rstate->nregs; i++) { 1189 rctx->vgt.nregs = 0; 1201 rctx->vgt.nregs = 0; 1388 state->regs[state->nregs].block = block; 1389 state->regs[state->nregs].id = (offset - block->start_offset) >> 2; 1391 state->regs[state->nregs].value = value; 1392 state->regs[state->nregs].bo = bo; 1393 state->regs[state->nregs].bo_usage = usage; 1395 state->nregs++; 1396 assert(state->nregs < R600_BLOCK_MAX_RE [all...] |
H A D | r600_state.c | 649 state.nregs = 0; 2130 rstate.nregs = 0; 2472 rstate->nregs = 0; 2589 rstate->nregs = 0; 2638 rstate->nregs = 0; 2725 rstate.nregs = 0;
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H A D | r600_hw_context.c | 759 for (i = 0; i < state->nregs; i++) { 769 for (i = 0; i < state->nregs; i++) { 781 for (int i = 0; i < state->nregs; i++) {
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/external/mesa3d/src/gallium/drivers/r600/ |
H A D | r600.h | 116 unsigned nregs; member in struct:r600_pipe_state 234 state->regs[state->nregs].value = value; 235 state->nregs++;
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H A D | r600_state_common.c | 465 for (int i = 0; i < rstate->nregs; i++) { 1189 rctx->vgt.nregs = 0; 1201 rctx->vgt.nregs = 0; 1388 state->regs[state->nregs].block = block; 1389 state->regs[state->nregs].id = (offset - block->start_offset) >> 2; 1391 state->regs[state->nregs].value = value; 1392 state->regs[state->nregs].bo = bo; 1393 state->regs[state->nregs].bo_usage = usage; 1395 state->nregs++; 1396 assert(state->nregs < R600_BLOCK_MAX_RE [all...] |
H A D | r600_state.c | 649 state.nregs = 0; 2130 rstate.nregs = 0; 2472 rstate->nregs = 0; 2589 rstate->nregs = 0; 2638 rstate->nregs = 0; 2725 rstate.nregs = 0;
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H A D | r600_hw_context.c | 759 for (i = 0; i < state->nregs; i++) { 769 for (i = 0; i < state->nregs; i++) { 781 for (int i = 0; i < state->nregs; i++) {
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/external/elfutils/0.153/libdw/ |
H A D | dwarf_frame_register.c | 78 if (unlikely ((size_t) regno >= fs->nregs))
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H A D | cfi.c | 69 size_t size = offsetof (Dwarf_Frame, regs[original->nregs]); 102 if (fs->nregs <= reg) 113 bigger->nregs = reg + 1; 308 if (cie->initial_state->nregs > operand)
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H A D | cfi.h | 206 size_t nregs; member in struct:Dwarf_Frame_s
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/external/qemu/target-arm/ |
H A D | op_helper.c | 483 int nregs; member in struct:__anon29231 505 const int nregs = neon_ls_element_type[op].nregs; local 513 for (reg = 0; reg < nregs; reg++) { 514 if (interleave > 2 || (interleave == 2 && nregs == 2)) { 516 } else if (interleave == 2 && nregs == 4 && reg == 2) {
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H A D | helper.c | 365 int nregs; local 368 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 369 if (reg < nregs) { 375 nregs += 16; 376 if (reg < nregs) { 382 switch (reg - nregs) { 392 int nregs; local 394 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 395 if (reg < nregs) { 400 nregs [all...] |
H A D | translate.c | 3884 int nregs; member in struct:__anon29232 3907 int nregs; local 3947 nregs = neon_ls_element_type[op].nregs; 3956 stride = nregs * 8; 3966 nregs = ((insn >> 8) & 3) + 1; 3969 if (nregs != 4 || a == 0) { 3975 if (nregs == 1 && a == 1 && size == 0) { 3978 if (nregs == 3 && a == 1) { 3983 if (nregs [all...] |
/external/elfutils/0.153/backends/ |
H A D | ia64_retval.c | 100 inline int hfa (const Dwarf_Op *loc, int nregs) argument 106 return fpregs_used + nregs;
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/external/jemalloc/src/ |
H A D | stats.c | 87 uint32_t nregs; local 106 CTL_J_GET("arenas.bin.0.nregs", &nregs, uint32_t); 132 j, reg_size, nregs, run_size / page, 140 j, reg_size, nregs, run_size / page,
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H A D | tcache.c | 494 if ((arena_bin_info[i].nregs << 1) <= TCACHE_NSLOTS_SMALL_MAX) { 496 (arena_bin_info[i].nregs << 1);
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H A D | arena.c | 329 assert(run->nfree < bin_info->nregs); 1477 run->nfree = bin_info->nregs; 1535 if (run->nfree == bin_info->nregs) 1880 if (bin_info->nregs != 1) { 1986 if (run->nfree == bin_info->nregs) { 2460 * *) bin_info->nregs <= RUN_MAXREGS 2462 * bin_info->nregs, bin_info->bitmap_offset, and bin_info->reg0_offset are also 2572 bin_info->nregs = good_nregs; 2576 assert(bin_info->reg0_offset - bin_info->redzone_size + (bin_info->nregs 2592 bitmap_info_init(&bin_info->bitmap_info, bin_info->nregs); [all...] |
/external/jemalloc/test/unit/ |
H A D | mallctl.c | 109 assert_d_eq(mallctlnametomib("arenas.bin.0.nregs", mib, &miblen), 0, 329 TEST_ARENAS_BIN_CONSTANT(uint32_t, nregs, arena_bin_info[0].nregs);
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/external/valgrind/main/VEX/priv/ |
H A D | host_amd64_defs.h | 557 /* Do 'ffree' on %st(7) .. %st(7-nregs) */ 559 Int nregs; /* 1 <= nregs <= 7 */ member in struct:__anon30799::__anon30800::__anon30825 723 extern AMD64Instr* AMD64Instr_A87Free ( Int nregs );
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H A D | host_amd64_defs.c | 135 void getAllocableRegs_AMD64 ( Int* nregs, HReg** arr ) argument 138 *nregs = 6; 139 *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); 149 *nregs = 20; 150 *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); 813 AMD64Instr* AMD64Instr_A87Free ( Int nregs ) 817 i->Ain.A87Free.nregs = nregs; 818 vassert(nregs >= 1 && nregs < [all...] |
/external/jemalloc/include/jemalloc/internal/ |
H A D | arena.h | 199 /* Index of next region that has never been allocated, or nregs. */ 232 * | region nregs-1 | 256 uint32_t nregs; member in struct:arena_bin_info_s 1018 assert(regind < bin_info->nregs);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/ |
H A D | si_state_draw.c | 305 rstate.nregs = 0;
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