1/*
2 * Copyright (C) 2010 The Android Open Source Project
3 * Copyright (c) 2008 ARM Ltd
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. The name of the company may not be used to endorse or promote
15 *    products derived from this software without specific prior written
16 *    permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Android adaptation and tweak by Jim Huang <jserv@0xlab.org>.
30 */
31
32#include <machine/cpu-features.h>
33#include <private/bionic_asm.h>
34
35ENTRY(strcpy)
36	pld	[r1, #0]
37	eor	r2, r0, r1
38	mov	ip, r0
39	tst	r2, #3
40	bne	4f
41	tst	r1, #3
42	bne	3f
435:
44	str	r5, [sp, #-4]!
45	mov	r5, #0x01
46	orr	r5, r5, r5, lsl #8
47	orr	r5, r5, r5, lsl #16
48
49	str	r4, [sp, #-4]!
50	tst	r1, #4
51	ldr	r3, [r1], #4
52	beq	2f
53	sub	r2, r3, r5
54	bics	r2, r2, r3
55	tst	r2, r5, lsl #7
56	itt	eq
57	streq	r3, [ip], #4
58	ldreq	r3, [r1], #4
59	bne	1f
60       /* Inner loop.  We now know that r1 is 64-bit aligned, so we
61	  can safely fetch up to two words.  This allows us to avoid
62	  load stalls.  */
63	.p2align 2
642:
65	pld	[r1, #8]
66	ldr	r4, [r1], #4
67	sub	r2, r3, r5
68	bics	r2, r2, r3
69	tst	r2, r5, lsl #7
70	sub	r2, r4, r5
71	bne	1f
72	str	r3, [ip], #4
73	bics	r2, r2, r4
74	tst	r2, r5, lsl #7
75	itt	eq
76	ldreq	r3, [r1], #4
77	streq	r4, [ip], #4
78	beq	2b
79	mov	r3, r4
801:
81#ifdef __ARMEB__
82	rors	r3, r3, #24
83#endif
84	strb	r3, [ip], #1
85	tst	r3, #0xff
86#ifdef __ARMEL__
87	ror	r3, r3, #8
88#endif
89	bne	1b
90	ldr	r4, [sp], #4
91	ldr	r5, [sp], #4
92	bx	lr
93
94       /* Strings have the same offset from word alignment, but it's
95	  not zero.  */
963:
97	tst	r1, #1
98	beq	1f
99	ldrb	r2, [r1], #1
100	strb	r2, [ip], #1
101	cmp	r2, #0
102	it	eq
103	bxeq	lr
1041:
105	tst	r1, #2
106	beq	5b
107	ldrh	r2, [r1], #2
108#ifdef __ARMEB__
109	tst	r2, #0xff00
110	iteet	ne
111	strneh	r2, [ip], #2
112	lsreq	r2, r2, #8
113	streqb	r2, [ip]
114	tstne	r2, #0xff
115#else
116	tst	r2, #0xff
117	itet	ne
118	strneh	r2, [ip], #2
119	streqb	r2, [ip]
120	tstne	r2, #0xff00
121#endif
122	bne	5b
123	bx	lr
124
125       /* src and dst do not have a common word-alignement.  Fall back to
126	  byte copying.  */
1274:
128	ldrb	r2, [r1], #1
129	strb	r2, [ip], #1
130	cmp	r2, #0
131	bne	4b
132	bx	lr
133END(strcpy)
134