1/*	$OpenBSD: regnum.h,v 1.3 2004/08/10 20:28:13 deraadt Exp $ */
2
3/*
4 * Copyright (c) 2001-2002 Opsycon AB  (www.opsycon.se / www.opsycon.com)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29#ifndef _MIPS64_REGNUM_H_
30#define _MIPS64_REGNUM_H_
31
32/*
33 * Location of the saved registers relative to ZERO.
34 * Usage is p->p_regs[XX].
35 */
36#define ZERO	0
37#define AST	1
38#define V0	2
39#define V1	3
40#define A0	4
41#define A1	5
42#define A2	6
43#define A3	7
44#define T0	8
45#define T1	9
46#define T2	10
47#define T3	11
48#define T4	12
49#define T5	13
50#define T6	14
51#define T7	15
52#define S0	16
53#define S1	17
54#define S2	18
55#define S3	19
56#define S4	20
57#define S5	21
58#define S6	22
59#define S7	23
60#define T8	24
61#define T9	25
62#define K0	26
63#define K1	27
64#define GP	28
65#define SP	29
66#define S8	30
67#define RA	31
68#define	SR	32
69#define	PS	SR	/* alias for SR */
70#define MULLO	33
71#define MULHI	34
72#define BADVADDR 35
73#define CAUSE	36
74#define	PC	37
75#define	IC	38
76#define	CPL	39
77
78#define	NUMSAVEREGS 40		/* Number of registers saved in trap */
79
80#define FPBASE	NUMSAVEREGS
81#define F0	(FPBASE+0)
82#define F1	(FPBASE+1)
83#define F2	(FPBASE+2)
84#define F3	(FPBASE+3)
85#define F4	(FPBASE+4)
86#define F5	(FPBASE+5)
87#define F6	(FPBASE+6)
88#define F7	(FPBASE+7)
89#define F8	(FPBASE+8)
90#define F9	(FPBASE+9)
91#define F10	(FPBASE+10)
92#define F11	(FPBASE+11)
93#define F12	(FPBASE+12)
94#define F13	(FPBASE+13)
95#define F14	(FPBASE+14)
96#define F15	(FPBASE+15)
97#define F16	(FPBASE+16)
98#define F17	(FPBASE+17)
99#define F18	(FPBASE+18)
100#define F19	(FPBASE+19)
101#define F20	(FPBASE+20)
102#define F21	(FPBASE+21)
103#define F22	(FPBASE+22)
104#define F23	(FPBASE+23)
105#define F24	(FPBASE+24)
106#define F25	(FPBASE+25)
107#define F26	(FPBASE+26)
108#define F27	(FPBASE+27)
109#define F28	(FPBASE+28)
110#define F29	(FPBASE+29)
111#define F30	(FPBASE+30)
112#define F31	(FPBASE+31)
113#define	FSR	(FPBASE+32)
114
115#define	NUMFPREGS 33
116
117#define	NREGS	(NUMSAVEREGS + NUMFPREGS)
118
119#endif /* !_MIPS64_REGNUM_H_ */
120