1// Copyright (c) 2006-2008 The Chromium Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5// This module gets enough CPU information to optimize the 6// atomicops module on x86. 7 8#include <stdint.h> 9#include <string.h> 10 11#include "base/atomicops.h" 12 13// This file only makes sense with atomicops_internals_x86_gcc.h -- it 14// depends on structs that are defined in that file. If atomicops.h 15// doesn't sub-include that file, then we aren't needed, and shouldn't 16// try to do anything. 17#ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 18 19// Inline cpuid instruction. In PIC compilations, %ebx contains the address 20// of the global offset table. To avoid breaking such executables, this code 21// must preserve that register's value across cpuid instructions. 22#if defined(__i386__) 23#define cpuid(a, b, c, d, inp) \ 24 asm("mov %%ebx, %%edi\n" \ 25 "cpuid\n" \ 26 "xchg %%edi, %%ebx\n" \ 27 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) 28#elif defined(__x86_64__) 29#define cpuid(a, b, c, d, inp) \ 30 asm("mov %%rbx, %%rdi\n" \ 31 "cpuid\n" \ 32 "xchg %%rdi, %%rbx\n" \ 33 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) 34#endif 35 36#if defined(cpuid) // initialize the struct only on x86 37 38// Set the flags so that code will run correctly and conservatively, so even 39// if we haven't been initialized yet, we're probably single threaded, and our 40// default values should hopefully be pretty safe. 41struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { 42 false, // bug can't exist before process spawns multiple threads 43}; 44 45namespace { 46 47// Initialize the AtomicOps_Internalx86CPUFeatures struct. 48void AtomicOps_Internalx86CPUFeaturesInit() { 49 uint32_t eax; 50 uint32_t ebx; 51 uint32_t ecx; 52 uint32_t edx; 53 54 // Get vendor string (issue CPUID with eax = 0) 55 cpuid(eax, ebx, ecx, edx, 0); 56 char vendor[13]; 57 memcpy(vendor, &ebx, 4); 58 memcpy(vendor + 4, &edx, 4); 59 memcpy(vendor + 8, &ecx, 4); 60 vendor[12] = 0; 61 62 // get feature flags in ecx/edx, and family/model in eax 63 cpuid(eax, ebx, ecx, edx, 1); 64 65 int family = (eax >> 8) & 0xf; // family and model fields 66 int model = (eax >> 4) & 0xf; 67 if (family == 0xf) { // use extended family and model fields 68 family += (eax >> 20) & 0xff; 69 model += ((eax >> 16) & 0xf) << 4; 70 } 71 72 // Opteron Rev E has a bug in which on very rare occasions a locked 73 // instruction doesn't act as a read-acquire barrier if followed by a 74 // non-locked read-modify-write instruction. Rev F has this bug in 75 // pre-release versions, but not in versions released to customers, 76 // so we test only for Rev E, which is family 15, model 32..63 inclusive. 77 if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD 78 family == 15 && 79 32 <= model && model <= 63) { 80 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; 81 } else { 82 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; 83 } 84} 85 86class AtomicOpsx86Initializer { 87 public: 88 AtomicOpsx86Initializer() { 89 AtomicOps_Internalx86CPUFeaturesInit(); 90 } 91}; 92 93// A global to get use initialized on startup via static initialization :/ 94AtomicOpsx86Initializer g_initer; 95 96} // namespace 97 98#endif // if x86 99 100#endif // ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 101