1// Copyright 2013 the V8 project authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5// CPU specific code for arm independent of OS goes here. 6 7#include "src/v8.h" 8 9#if V8_TARGET_ARCH_ARM64 10 11#include "src/cpu.h" 12#include "src/arm64/utils-arm64.h" 13 14namespace v8 { 15namespace internal { 16 17class CacheLineSizes { 18 public: 19 CacheLineSizes() { 20#ifdef USE_SIMULATOR 21 cache_type_register_ = 0; 22#else 23 // Copy the content of the cache type register to a core register. 24 __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT 25 : [ctr] "=r" (cache_type_register_)); 26#endif 27 } 28 29 uint32_t icache_line_size() const { return ExtractCacheLineSize(0); } 30 uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); } 31 32 private: 33 uint32_t ExtractCacheLineSize(int cache_line_size_shift) const { 34 // The cache type register holds the size of cache lines in words as a 35 // power of two. 36 return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf); 37 } 38 39 uint32_t cache_type_register_; 40}; 41 42 43void CPU::FlushICache(void* address, size_t length) { 44 if (length == 0) return; 45 46#ifdef USE_SIMULATOR 47 // TODO(all): consider doing some cache simulation to ensure every address 48 // run has been synced. 49 USE(address); 50 USE(length); 51#else 52 // The code below assumes user space cache operations are allowed. The goal 53 // of this routine is to make sure the code generated is visible to the I 54 // side of the CPU. 55 56 uintptr_t start = reinterpret_cast<uintptr_t>(address); 57 // Sizes will be used to generate a mask big enough to cover a pointer. 58 CacheLineSizes sizes; 59 uintptr_t dsize = sizes.dcache_line_size(); 60 uintptr_t isize = sizes.icache_line_size(); 61 // Cache line sizes are always a power of 2. 62 ASSERT(CountSetBits(dsize, 64) == 1); 63 ASSERT(CountSetBits(isize, 64) == 1); 64 uintptr_t dstart = start & ~(dsize - 1); 65 uintptr_t istart = start & ~(isize - 1); 66 uintptr_t end = start + length; 67 68 __asm__ __volatile__ ( // NOLINT 69 // Clean every line of the D cache containing the target data. 70 "0: \n\t" 71 // dc : Data Cache maintenance 72 // c : Clean 73 // va : by (Virtual) Address 74 // u : to the point of Unification 75 // The point of unification for a processor is the point by which the 76 // instruction and data caches are guaranteed to see the same copy of a 77 // memory location. See ARM DDI 0406B page B2-12 for more information. 78 "dc cvau, %[dline] \n\t" 79 "add %[dline], %[dline], %[dsize] \n\t" 80 "cmp %[dline], %[end] \n\t" 81 "b.lt 0b \n\t" 82 // Barrier to make sure the effect of the code above is visible to the rest 83 // of the world. 84 // dsb : Data Synchronisation Barrier 85 // ish : Inner SHareable domain 86 // The point of unification for an Inner Shareable shareability domain is 87 // the point by which the instruction and data caches of all the processors 88 // in that Inner Shareable shareability domain are guaranteed to see the 89 // same copy of a memory location. See ARM DDI 0406B page B2-12 for more 90 // information. 91 "dsb ish \n\t" 92 // Invalidate every line of the I cache containing the target data. 93 "1: \n\t" 94 // ic : instruction cache maintenance 95 // i : invalidate 96 // va : by address 97 // u : to the point of unification 98 "ic ivau, %[iline] \n\t" 99 "add %[iline], %[iline], %[isize] \n\t" 100 "cmp %[iline], %[end] \n\t" 101 "b.lt 1b \n\t" 102 // Barrier to make sure the effect of the code above is visible to the rest 103 // of the world. 104 "dsb ish \n\t" 105 // Barrier to ensure any prefetching which happened before this code is 106 // discarded. 107 // isb : Instruction Synchronisation Barrier 108 "isb \n\t" 109 : [dline] "+r" (dstart), 110 [iline] "+r" (istart) 111 : [dsize] "r" (dsize), 112 [isize] "r" (isize), 113 [end] "r" (end) 114 // This code does not write to memory but without the dependency gcc might 115 // move this code before the code is generated. 116 : "cc", "memory" 117 ); // NOLINT 118#endif 119} 120 121} } // namespace v8::internal 122 123#endif // V8_TARGET_ARCH_ARM64 124