1#ifndef _ASM_ARM_PERF_REGS_H
2#define _ASM_ARM_PERF_REGS_H
3
4enum perf_event_arm_regs {
5	PERF_REG_ARM_R0,
6	PERF_REG_ARM_R1,
7	PERF_REG_ARM_R2,
8	PERF_REG_ARM_R3,
9	PERF_REG_ARM_R4,
10	PERF_REG_ARM_R5,
11	PERF_REG_ARM_R6,
12	PERF_REG_ARM_R7,
13	PERF_REG_ARM_R8,
14	PERF_REG_ARM_R9,
15	PERF_REG_ARM_R10,
16	PERF_REG_ARM_FP,
17	PERF_REG_ARM_IP,
18	PERF_REG_ARM_SP,
19	PERF_REG_ARM_LR,
20	PERF_REG_ARM_PC,
21	PERF_REG_ARM_MAX,
22};
23#endif /* _ASM_ARM_PERF_REGS_H */
24