MCRegisterInfo.h revision 0371cd8b1c0d2101295ca9381a0b437e1f2d8fa2
1//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCREGISTERINFO_H 17#define LLVM_MC_MCREGISTERINFO_H 18 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/Support/ErrorHandling.h" 21#include <cassert> 22 23namespace llvm { 24 25/// MCRegisterClass - Base class of TargetRegisterClass. 26class MCRegisterClass { 27public: 28 typedef const uint16_t* iterator; 29 typedef const uint16_t* const_iterator; 30 31 const char *Name; 32 const iterator RegsBegin; 33 const uint8_t *const RegSet; 34 const uint16_t RegsSize; 35 const uint16_t RegSetSize; 36 const uint16_t ID; 37 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes 38 const int8_t CopyCost; 39 const bool Allocatable; 40 41 /// getID() - Return the register class ID number. 42 /// 43 unsigned getID() const { return ID; } 44 45 /// getName() - Return the register class name for debugging. 46 /// 47 const char *getName() const { return Name; } 48 49 /// begin/end - Return all of the registers in this class. 50 /// 51 iterator begin() const { return RegsBegin; } 52 iterator end() const { return RegsBegin + RegsSize; } 53 54 /// getNumRegs - Return the number of registers in this class. 55 /// 56 unsigned getNumRegs() const { return RegsSize; } 57 58 /// getRegister - Return the specified register in the class. 59 /// 60 unsigned getRegister(unsigned i) const { 61 assert(i < getNumRegs() && "Register number out of range!"); 62 return RegsBegin[i]; 63 } 64 65 /// contains - Return true if the specified register is included in this 66 /// register class. This does not include virtual registers. 67 bool contains(unsigned Reg) const { 68 unsigned InByte = Reg % 8; 69 unsigned Byte = Reg / 8; 70 if (Byte >= RegSetSize) 71 return false; 72 return (RegSet[Byte] & (1 << InByte)) != 0; 73 } 74 75 /// contains - Return true if both registers are in this class. 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2); 78 } 79 80 /// getSize - Return the size of the register in bytes, which is also the size 81 /// of a stack slot allocated to hold a spilled copy of this register. 82 unsigned getSize() const { return RegSize; } 83 84 /// getAlignment - Return the minimum required alignment for a register of 85 /// this class. 86 unsigned getAlignment() const { return Alignment; } 87 88 /// getCopyCost - Return the cost of copying a value between two registers in 89 /// this class. A negative number means the register class is very expensive 90 /// to copy e.g. status flag register classes. 91 int getCopyCost() const { return CopyCost; } 92 93 /// isAllocatable - Return true if this register class may be used to create 94 /// virtual registers. 95 bool isAllocatable() const { return Allocatable; } 96}; 97 98/// MCRegisterDesc - This record contains all of the information known about 99/// a particular register. The Overlaps field contains a pointer to a zero 100/// terminated array of registers that this register aliases, starting with 101/// itself. This is needed for architectures like X86 which have AL alias AX 102/// alias EAX. The SubRegs field is a zero terminated array of registers that 103/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 104/// AX. The SuperRegs field is a zero terminated array of registers that are 105/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 106/// of AX. 107/// 108struct MCRegisterDesc { 109 uint32_t Name; // Printable name for the reg (for debugging) 110 uint32_t Overlaps; // Overlapping registers, described above 111 uint32_t SubRegs; // Sub-register set, described above 112 uint32_t SuperRegs; // Super-register set, described above 113 114 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each 115 // sub-register in SubRegs. 116 uint32_t SubRegIndices; 117 118 // RegUnits - Points to the list of register units. The low 4 bits holds the 119 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 120 uint32_t RegUnits; 121}; 122 123/// MCRegisterInfo base class - We assume that the target defines a static 124/// array of MCRegisterDesc objects that represent all of the machine 125/// registers that the target has. As such, we simply have to track a pointer 126/// to this array so that we can turn register number into a register 127/// descriptor. 128/// 129/// Note this class is designed to be a base class of TargetRegisterInfo, which 130/// is the interface used by codegen. However, specific targets *should never* 131/// specialize this class. MCRegisterInfo should only contain getters to access 132/// TableGen generated physical register data. It must not be extended with 133/// virtual methods. 134/// 135class MCRegisterInfo { 136public: 137 typedef const MCRegisterClass *regclass_iterator; 138 139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 140 /// performed with a binary search. 141 struct DwarfLLVMRegPair { 142 unsigned FromReg; 143 unsigned ToReg; 144 145 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 146 }; 147private: 148 const MCRegisterDesc *Desc; // Pointer to the descriptor array 149 unsigned NumRegs; // Number of entries in the array 150 unsigned RAReg; // Return address register 151 const MCRegisterClass *Classes; // Pointer to the regclass array 152 unsigned NumClasses; // Number of entries in the array 153 unsigned NumRegUnits; // Number of regunits. 154 const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table. 155 const uint16_t *DiffLists; // Pointer to the difflists array 156 const char *RegStrings; // Pointer to the string table. 157 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 158 // array. 159 unsigned NumSubRegIndices; // Number of subreg indices. 160 const uint16_t *RegEncodingTable; // Pointer to array of register 161 // encodings. 162 163 unsigned L2DwarfRegsSize; 164 unsigned EHL2DwarfRegsSize; 165 unsigned Dwarf2LRegsSize; 166 unsigned EHDwarf2LRegsSize; 167 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 168 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 169 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 170 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 171 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 172 173public: 174 /// DiffListIterator - Base iterator class that can traverse the 175 /// differentially encoded register and regunit lists in DiffLists. 176 /// Don't use this class directly, use one of the specialized sub-classes 177 /// defined below. 178 class DiffListIterator { 179 uint16_t Val; 180 const uint16_t *List; 181 182 protected: 183 /// Create an invalid iterator. Call init() to point to something useful. 184 DiffListIterator() : Val(0), List(0) {} 185 186 /// init - Point the iterator to InitVal, decoding subsequent values from 187 /// DiffList. The iterator will initially point to InitVal, sub-classes are 188 /// responsible for skipping the seed value if it is not part of the list. 189 void init(uint16_t InitVal, const uint16_t *DiffList) { 190 Val = InitVal; 191 List = DiffList; 192 } 193 194 /// advance - Move to the next list position, return the applied 195 /// differential. This function does not detect the end of the list, that 196 /// is the caller's responsibility (by checking for a 0 return value). 197 unsigned advance() { 198 assert(isValid() && "Cannot move off the end of the list."); 199 uint16_t D = *List++; 200 Val += D; 201 return D; 202 } 203 204 public: 205 206 /// isValid - returns true if this iterator is not yet at the end. 207 bool isValid() const { return List; } 208 209 /// Dereference the iterator to get the value at the current position. 210 unsigned operator*() const { return Val; } 211 212 /// Pre-increment to move to the next position. 213 void operator++() { 214 // The end of the list is encoded as a 0 differential. 215 if (!advance()) 216 List = 0; 217 } 218 }; 219 220 // These iterators are allowed to sub-class DiffListIterator and access 221 // internal list pointers. 222 friend class MCSubRegIterator; 223 friend class MCSuperRegIterator; 224 friend class MCRegAliasIterator; 225 friend class MCRegUnitIterator; 226 friend class MCRegUnitRootIterator; 227 228 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 229 /// auto-generated routines. *DO NOT USE*. 230 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 231 const MCRegisterClass *C, unsigned NC, 232 const uint16_t (*RURoots)[2], 233 unsigned NRU, 234 const uint16_t *DL, 235 const char *Strings, 236 const uint16_t *SubIndices, 237 unsigned NumIndices, 238 const uint16_t *RET) { 239 Desc = D; 240 NumRegs = NR; 241 RAReg = RA; 242 Classes = C; 243 DiffLists = DL; 244 RegStrings = Strings; 245 NumClasses = NC; 246 RegUnitRoots = RURoots; 247 NumRegUnits = NRU; 248 SubRegIndices = SubIndices; 249 NumSubRegIndices = NumIndices; 250 RegEncodingTable = RET; 251 } 252 253 /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf 254 /// register number mapping. Called by TableGen auto-generated routines. 255 /// *DO NOT USE*. 256 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 257 bool isEH) { 258 if (isEH) { 259 EHL2DwarfRegs = Map; 260 EHL2DwarfRegsSize = Size; 261 } else { 262 L2DwarfRegs = Map; 263 L2DwarfRegsSize = Size; 264 } 265 } 266 267 /// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM 268 /// register number mapping. Called by TableGen auto-generated routines. 269 /// *DO NOT USE*. 270 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 271 bool isEH) { 272 if (isEH) { 273 EHDwarf2LRegs = Map; 274 EHDwarf2LRegsSize = Size; 275 } else { 276 Dwarf2LRegs = Map; 277 Dwarf2LRegsSize = Size; 278 } 279 } 280 281 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 282 /// number mapping. By default the SEH register number is just the same 283 /// as the LLVM register number. 284 /// FIXME: TableGen these numbers. Currently this requires target specific 285 /// initialization code. 286 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 287 L2SEHRegs[LLVMReg] = SEHReg; 288 } 289 290 /// getRARegister - This method should return the register where the return 291 /// address can be found. 292 unsigned getRARegister() const { 293 return RAReg; 294 } 295 296 const MCRegisterDesc &operator[](unsigned RegNo) const { 297 assert(RegNo < NumRegs && 298 "Attempting to access record for invalid register number!"); 299 return Desc[RegNo]; 300 } 301 302 /// Provide a get method, equivalent to [], but more useful if we have a 303 /// pointer to this object. 304 /// 305 const MCRegisterDesc &get(unsigned RegNo) const { 306 return operator[](RegNo); 307 } 308 309 /// getSubReg - Returns the physical register number of sub-register "Index" 310 /// for physical register RegNo. Return zero if the sub-register does not 311 /// exist. 312 unsigned getSubReg(unsigned Reg, unsigned Idx) const; 313 314 /// getMatchingSuperReg - Return a super-register of the specified register 315 /// Reg so its sub-register of index SubIdx is Reg. 316 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 317 const MCRegisterClass *RC) const; 318 319 /// getSubRegIndex - For a given register pair, return the sub-register index 320 /// if the second register is a sub-register of the first. Return zero 321 /// otherwise. 322 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; 323 324 /// getName - Return the human-readable symbolic target-specific name for the 325 /// specified physical register. 326 const char *getName(unsigned RegNo) const { 327 return RegStrings + get(RegNo).Name; 328 } 329 330 /// getNumRegs - Return the number of registers this target has (useful for 331 /// sizing arrays holding per register information) 332 unsigned getNumRegs() const { 333 return NumRegs; 334 } 335 336 /// getNumRegUnits - Return the number of (native) register units in the 337 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 338 /// can be accessed through MCRegUnitIterator defined below. 339 unsigned getNumRegUnits() const { 340 return NumRegUnits; 341 } 342 343 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 344 /// number. Returns -1 if there is no equivalent value. The second 345 /// parameter allows targets to use different numberings for EH info and 346 /// debugging info. 347 int getDwarfRegNum(unsigned RegNum, bool isEH) const { 348 const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs; 349 unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize; 350 351 DwarfLLVMRegPair Key = { RegNum, 0 }; 352 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 353 if (I == M+Size || I->FromReg != RegNum) 354 return -1; 355 return I->ToReg; 356 } 357 358 /// getLLVMRegNum - Map a dwarf register back to a target register. 359 /// 360 int getLLVMRegNum(unsigned RegNum, bool isEH) const { 361 const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; 362 unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize; 363 364 DwarfLLVMRegPair Key = { RegNum, 0 }; 365 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 366 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); 367 return I->ToReg; 368 } 369 370 /// getSEHRegNum - Map a target register to an equivalent SEH register 371 /// number. Returns LLVM register number if there is no equivalent value. 372 int getSEHRegNum(unsigned RegNum) const { 373 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 374 if (I == L2SEHRegs.end()) return (int)RegNum; 375 return I->second; 376 } 377 378 regclass_iterator regclass_begin() const { return Classes; } 379 regclass_iterator regclass_end() const { return Classes+NumClasses; } 380 381 unsigned getNumRegClasses() const { 382 return (unsigned)(regclass_end()-regclass_begin()); 383 } 384 385 /// getRegClass - Returns the register class associated with the enumeration 386 /// value. See class MCOperandInfo. 387 const MCRegisterClass getRegClass(unsigned i) const { 388 assert(i < getNumRegClasses() && "Register Class ID out of range"); 389 return Classes[i]; 390 } 391 392 /// getEncodingValue - Returns the encoding for RegNo 393 uint16_t getEncodingValue(unsigned RegNo) const { 394 assert(RegNo < NumRegs && 395 "Attempting to get encoding for invalid register number!"); 396 return RegEncodingTable[RegNo]; 397 } 398 399}; 400 401//===----------------------------------------------------------------------===// 402// Register List Iterators 403//===----------------------------------------------------------------------===// 404 405// MCRegisterInfo provides lists of super-registers, sub-registers, and 406// aliasing registers. Use these iterator classes to traverse the lists. 407 408/// MCSubRegIterator enumerates all sub-registers of Reg. 409class MCSubRegIterator : public MCRegisterInfo::DiffListIterator { 410public: 411 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 412 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); 413 ++*this; 414 } 415}; 416 417/// MCSuperRegIterator enumerates all super-registers of Reg. 418class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { 419public: 420 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 421 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 422 ++*this; 423 } 424}; 425 426/// MCRegAliasIterator enumerates all registers aliasing Reg. 427/// If IncludeSelf is set, Reg itself is included in the list. 428class MCRegAliasIterator : public MCRegisterInfo::DiffListIterator { 429public: 430 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, 431 bool IncludeSelf) { 432 init(Reg, MCRI->DiffLists + MCRI->get(Reg).Overlaps); 433 // Initially, the iterator points to Reg itself. 434 if (!IncludeSelf) 435 ++*this; 436 } 437}; 438 439inline 440unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 441 const MCRegisterClass *RC) const { 442 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers) 443 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) 444 return *Supers; 445 return 0; 446} 447 448inline 449unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { 450 // Get a pointer to the corresponding SubRegIndices list. This list has the 451 // name of each sub-register in the same order as MCSubRegIterator. 452 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; 453 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) 454 if (*SRI == Idx) 455 return *Subs; 456 return 0; 457} 458 459inline 460unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { 461 // Get a pointer to the corresponding SubRegIndices list. This list has the 462 // name of each sub-register in the same order as MCSubRegIterator. 463 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; 464 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) 465 if (*Subs == SubReg) 466 return *SRI; 467 return 0; 468} 469 470//===----------------------------------------------------------------------===// 471// Register Units 472//===----------------------------------------------------------------------===// 473 474// Register units are used to compute register aliasing. Every register has at 475// least one register unit, but it can have more. Two registers overlap if and 476// only if they have a common register unit. 477// 478// A target with a complicated sub-register structure will typically have many 479// fewer register units than actual registers. MCRI::getNumRegUnits() returns 480// the number of register units in the target. 481 482// MCRegUnitIterator enumerates a list of register units for Reg. The list is 483// in ascending numerical order. 484class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 485public: 486 /// MCRegUnitIterator - Create an iterator that traverses the register units 487 /// in Reg. 488 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 489 // Decode the RegUnits MCRegisterDesc field. 490 unsigned RU = MCRI->get(Reg).RegUnits; 491 unsigned Scale = RU & 15; 492 unsigned Offset = RU >> 4; 493 494 // Initialize the iterator to Reg * Scale, and the List pointer to 495 // DiffLists + Offset. 496 init(Reg * Scale, MCRI->DiffLists + Offset); 497 498 // That may not be a valid unit, we need to advance by one to get the real 499 // unit number. The first differential can be 0 which would normally 500 // terminate the list, but since we know every register has at least one 501 // unit, we can allow a 0 differential here. 502 advance(); 503 } 504}; 505 506// Each register unit has one or two root registers. The complete set of 507// registers containing a register unit is the union of the roots and their 508// super-registers. All registers aliasing Unit can be visited like this: 509// 510// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 511// unsigned Root = *RI; 512// visit(Root); 513// for (MCSuperRegIterator SI(Root, MCRI); SI.isValid(); ++SI) 514// visit(*SI); 515// } 516 517/// MCRegUnitRootIterator enumerates the root registers of a register unit. 518class MCRegUnitRootIterator { 519 uint16_t Reg0; 520 uint16_t Reg1; 521public: 522 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { 523 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); 524 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 525 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 526 } 527 528 /// Dereference to get the current root register. 529 unsigned operator*() const { 530 return Reg0; 531 } 532 533 /// isValid - Check if the iterator is at the end of the list. 534 bool isValid() const { 535 return Reg0; 536 } 537 538 /// Preincrement to move to the next root register. 539 void operator++() { 540 assert(isValid() && "Cannot move off the end of the list."); 541 Reg0 = Reg1; 542 Reg1 = 0; 543 } 544}; 545 546} // End llvm namespace 547 548#endif 549