MCRegisterInfo.h revision b6632ba380cf624e60fe16b03d6e21b05dd07724
1//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCREGISTERINFO_H 17#define LLVM_MC_MCREGISTERINFO_H 18 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/Support/ErrorHandling.h" 21#include <cassert> 22 23namespace llvm { 24 25/// MCRegisterClass - Base class of TargetRegisterClass. 26class MCRegisterClass { 27public: 28 typedef const uint16_t* iterator; 29 typedef const uint16_t* const_iterator; 30 31 const unsigned ID; 32 const char *Name; 33 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 34 const int CopyCost; 35 const bool Allocatable; 36 const iterator RegsBegin; 37 const uint8_t *const RegSet; 38 const unsigned RegsSize; 39 const unsigned RegSetSize; 40 41 /// getID() - Return the register class ID number. 42 /// 43 unsigned getID() const { return ID; } 44 45 /// getName() - Return the register class name for debugging. 46 /// 47 const char *getName() const { return Name; } 48 49 /// begin/end - Return all of the registers in this class. 50 /// 51 iterator begin() const { return RegsBegin; } 52 iterator end() const { return RegsBegin + RegsSize; } 53 54 /// getNumRegs - Return the number of registers in this class. 55 /// 56 unsigned getNumRegs() const { return RegsSize; } 57 58 /// getRegister - Return the specified register in the class. 59 /// 60 unsigned getRegister(unsigned i) const { 61 assert(i < getNumRegs() && "Register number out of range!"); 62 return RegsBegin[i]; 63 } 64 65 /// contains - Return true if the specified register is included in this 66 /// register class. This does not include virtual registers. 67 bool contains(unsigned Reg) const { 68 unsigned InByte = Reg % 8; 69 unsigned Byte = Reg / 8; 70 if (Byte >= RegSetSize) 71 return false; 72 return (RegSet[Byte] & (1 << InByte)) != 0; 73 } 74 75 /// contains - Return true if both registers are in this class. 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2); 78 } 79 80 /// getSize - Return the size of the register in bytes, which is also the size 81 /// of a stack slot allocated to hold a spilled copy of this register. 82 unsigned getSize() const { return RegSize; } 83 84 /// getAlignment - Return the minimum required alignment for a register of 85 /// this class. 86 unsigned getAlignment() const { return Alignment; } 87 88 /// getCopyCost - Return the cost of copying a value between two registers in 89 /// this class. A negative number means the register class is very expensive 90 /// to copy e.g. status flag register classes. 91 int getCopyCost() const { return CopyCost; } 92 93 /// isAllocatable - Return true if this register class may be used to create 94 /// virtual registers. 95 bool isAllocatable() const { return Allocatable; } 96}; 97 98/// MCRegisterDesc - This record contains all of the information known about 99/// a particular register. The Overlaps field contains a pointer to a zero 100/// terminated array of registers that this register aliases, starting with 101/// itself. This is needed for architectures like X86 which have AL alias AX 102/// alias EAX. The SubRegs field is a zero terminated array of registers that 103/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 104/// AX. The SuperRegs field is a zero terminated array of registers that are 105/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 106/// of AX. 107/// 108struct MCRegisterDesc { 109 const char *Name; // Printable name for the reg (for debugging) 110 unsigned Overlaps; // Overlapping registers, described above 111 unsigned SubRegs; // Sub-register set, described above 112 unsigned SuperRegs; // Super-register set, described above 113}; 114 115/// MCRegisterInfo base class - We assume that the target defines a static 116/// array of MCRegisterDesc objects that represent all of the machine 117/// registers that the target has. As such, we simply have to track a pointer 118/// to this array so that we can turn register number into a register 119/// descriptor. 120/// 121/// Note this class is designed to be a base class of TargetRegisterInfo, which 122/// is the interface used by codegen. However, specific targets *should never* 123/// specialize this class. MCRegisterInfo should only contain getters to access 124/// TableGen generated physical register data. It must not be extended with 125/// virtual methods. 126/// 127class MCRegisterInfo { 128public: 129 typedef const MCRegisterClass *regclass_iterator; 130private: 131 const MCRegisterDesc *Desc; // Pointer to the descriptor array 132 unsigned NumRegs; // Number of entries in the array 133 unsigned RAReg; // Return address register 134 const MCRegisterClass *Classes; // Pointer to the regclass array 135 unsigned NumClasses; // Number of entries in the array 136 const unsigned *Overlaps; // Pointer to the overlaps array 137 const unsigned *SubRegs; // Pointer to the subregs array 138 const unsigned *SuperRegs; // Pointer to the superregs array 139 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 140 // array. 141 unsigned NumSubRegIndices; // Number of subreg indices. 142 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping 143 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 144 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping 145 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 146 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 147 148public: 149 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 150 /// auto-generated routines. *DO NOT USE*. 151 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 152 const MCRegisterClass *C, unsigned NC, 153 const unsigned *O, const unsigned *Sub, 154 const unsigned *Super, 155 const uint16_t *SubIndices, 156 unsigned NumIndices) { 157 Desc = D; 158 NumRegs = NR; 159 RAReg = RA; 160 Classes = C; 161 Overlaps = O; 162 SubRegs = Sub; 163 SuperRegs = Super; 164 NumClasses = NC; 165 SubRegIndices = SubIndices; 166 NumSubRegIndices = NumIndices; 167 } 168 169 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf 170 /// register number mapping. Called by TableGen auto-generated routines. 171 /// *DO NOT USE*. 172 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) { 173 if (isEH) 174 EHL2DwarfRegs[LLVMReg] = DwarfReg; 175 else 176 L2DwarfRegs[LLVMReg] = DwarfReg; 177 } 178 179 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM 180 /// register number mapping. Called by TableGen auto-generated routines. 181 /// *DO NOT USE*. 182 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) { 183 if (isEH) 184 EHDwarf2LRegs[DwarfReg] = LLVMReg; 185 else 186 Dwarf2LRegs[DwarfReg] = LLVMReg; 187 } 188 189 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 190 /// number mapping. By default the SEH register number is just the same 191 /// as the LLVM register number. 192 /// FIXME: TableGen these numbers. Currently this requires target specific 193 /// initialization code. 194 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 195 L2SEHRegs[LLVMReg] = SEHReg; 196 } 197 198 /// getRARegister - This method should return the register where the return 199 /// address can be found. 200 unsigned getRARegister() const { 201 return RAReg; 202 } 203 204 const MCRegisterDesc &operator[](unsigned RegNo) const { 205 assert(RegNo < NumRegs && 206 "Attempting to access record for invalid register number!"); 207 return Desc[RegNo]; 208 } 209 210 /// Provide a get method, equivalent to [], but more useful if we have a 211 /// pointer to this object. 212 /// 213 const MCRegisterDesc &get(unsigned RegNo) const { 214 return operator[](RegNo); 215 } 216 217 /// getAliasSet - Return the set of registers aliased by the specified 218 /// register, or a null list of there are none. The list returned is zero 219 /// terminated. 220 /// 221 const unsigned *getAliasSet(unsigned RegNo) const { 222 // The Overlaps set always begins with Reg itself. 223 return Overlaps + get(RegNo).Overlaps + 1; 224 } 225 226 /// getOverlaps - Return a list of registers that overlap Reg, including 227 /// itself. This is the same as the alias set except Reg is included in the 228 /// list. 229 /// These are exactly the registers in { x | regsOverlap(x, Reg) }. 230 /// 231 const unsigned *getOverlaps(unsigned RegNo) const { 232 return Overlaps + get(RegNo).Overlaps; 233 } 234 235 /// getSubRegisters - Return the list of registers that are sub-registers of 236 /// the specified register, or a null list of there are none. The list 237 /// returned is zero terminated and sorted according to super-sub register 238 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 239 /// 240 const unsigned *getSubRegisters(unsigned RegNo) const { 241 return SubRegs + get(RegNo).SubRegs; 242 } 243 244 /// getSubReg - Returns the physical register number of sub-register "Index" 245 /// for physical register RegNo. Return zero if the sub-register does not 246 /// exist. 247 unsigned getSubReg(unsigned Reg, unsigned Idx) const { 248 return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1); 249 } 250 251 /// getSubRegIndex - For a given register pair, return the sub-register index 252 /// if the second register is a sub-register of the first. Return zero 253 /// otherwise. 254 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const { 255 for (unsigned I = 1; I <= NumSubRegIndices; ++I) 256 if (getSubReg(RegNo, I) == SubRegNo) 257 return I; 258 return 0; 259 } 260 261 /// getSuperRegisters - Return the list of registers that are super-registers 262 /// of the specified register, or a null list of there are none. The list 263 /// returned is zero terminated and sorted according to super-sub register 264 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. 265 /// 266 const unsigned *getSuperRegisters(unsigned RegNo) const { 267 return SuperRegs + get(RegNo).SuperRegs; 268 } 269 270 /// getName - Return the human-readable symbolic target-specific name for the 271 /// specified physical register. 272 const char *getName(unsigned RegNo) const { 273 return get(RegNo).Name; 274 } 275 276 /// getNumRegs - Return the number of registers this target has (useful for 277 /// sizing arrays holding per register information) 278 unsigned getNumRegs() const { 279 return NumRegs; 280 } 281 282 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 283 /// number. Returns -1 if there is no equivalent value. The second 284 /// parameter allows targets to use different numberings for EH info and 285 /// debugging info. 286 int getDwarfRegNum(unsigned RegNum, bool isEH) const { 287 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs; 288 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum); 289 if (I == M.end()) return -1; 290 return I->second; 291 } 292 293 /// getLLVMRegNum - Map a dwarf register back to a target register. 294 /// 295 int getLLVMRegNum(unsigned RegNum, bool isEH) const { 296 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; 297 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum); 298 if (I == M.end()) { 299 llvm_unreachable("Invalid RegNum"); 300 } 301 return I->second; 302 } 303 304 /// getSEHRegNum - Map a target register to an equivalent SEH register 305 /// number. Returns LLVM register number if there is no equivalent value. 306 int getSEHRegNum(unsigned RegNum) const { 307 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 308 if (I == L2SEHRegs.end()) return (int)RegNum; 309 return I->second; 310 } 311 312 regclass_iterator regclass_begin() const { return Classes; } 313 regclass_iterator regclass_end() const { return Classes+NumClasses; } 314 315 unsigned getNumRegClasses() const { 316 return (unsigned)(regclass_end()-regclass_begin()); 317 } 318 319 /// getRegClass - Returns the register class associated with the enumeration 320 /// value. See class MCOperandInfo. 321 const MCRegisterClass getRegClass(unsigned i) const { 322 assert(i < getNumRegClasses() && "Register Class ID out of range"); 323 return Classes[i]; 324 } 325}; 326 327} // End llvm namespace 328 329#endif 330