MCRegisterInfo.h revision cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3
1//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCREGISTERINFO_H 17#define LLVM_MC_MCREGISTERINFO_H 18 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/Support/ErrorHandling.h" 21#include <cassert> 22 23namespace llvm { 24 25/// MCRegisterClass - Base class of TargetRegisterClass. 26class MCRegisterClass { 27public: 28 typedef const uint16_t* iterator; 29 typedef const uint16_t* const_iterator; 30 31 const char *Name; 32 const iterator RegsBegin; 33 const uint8_t *const RegSet; 34 const uint16_t RegsSize; 35 const uint16_t RegSetSize; 36 const uint16_t ID; 37 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes 38 const int8_t CopyCost; 39 const bool Allocatable; 40 41 /// getID() - Return the register class ID number. 42 /// 43 unsigned getID() const { return ID; } 44 45 /// getName() - Return the register class name for debugging. 46 /// 47 const char *getName() const { return Name; } 48 49 /// begin/end - Return all of the registers in this class. 50 /// 51 iterator begin() const { return RegsBegin; } 52 iterator end() const { return RegsBegin + RegsSize; } 53 54 /// getNumRegs - Return the number of registers in this class. 55 /// 56 unsigned getNumRegs() const { return RegsSize; } 57 58 /// getRegister - Return the specified register in the class. 59 /// 60 unsigned getRegister(unsigned i) const { 61 assert(i < getNumRegs() && "Register number out of range!"); 62 return RegsBegin[i]; 63 } 64 65 /// contains - Return true if the specified register is included in this 66 /// register class. This does not include virtual registers. 67 bool contains(unsigned Reg) const { 68 unsigned InByte = Reg % 8; 69 unsigned Byte = Reg / 8; 70 if (Byte >= RegSetSize) 71 return false; 72 return (RegSet[Byte] & (1 << InByte)) != 0; 73 } 74 75 /// contains - Return true if both registers are in this class. 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2); 78 } 79 80 /// getSize - Return the size of the register in bytes, which is also the size 81 /// of a stack slot allocated to hold a spilled copy of this register. 82 unsigned getSize() const { return RegSize; } 83 84 /// getAlignment - Return the minimum required alignment for a register of 85 /// this class. 86 unsigned getAlignment() const { return Alignment; } 87 88 /// getCopyCost - Return the cost of copying a value between two registers in 89 /// this class. A negative number means the register class is very expensive 90 /// to copy e.g. status flag register classes. 91 int getCopyCost() const { return CopyCost; } 92 93 /// isAllocatable - Return true if this register class may be used to create 94 /// virtual registers. 95 bool isAllocatable() const { return Allocatable; } 96}; 97 98/// MCRegisterDesc - This record contains all of the information known about 99/// a particular register. The Overlaps field contains a pointer to a zero 100/// terminated array of registers that this register aliases, starting with 101/// itself. This is needed for architectures like X86 which have AL alias AX 102/// alias EAX. The SubRegs field is a zero terminated array of registers that 103/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 104/// AX. The SuperRegs field is a zero terminated array of registers that are 105/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 106/// of AX. 107/// 108struct MCRegisterDesc { 109 uint32_t Name; // Printable name for the reg (for debugging) 110 uint32_t Overlaps; // Overlapping registers, described above 111 uint32_t SubRegs; // Sub-register set, described above 112 uint32_t SuperRegs; // Super-register set, described above 113 114 // RegUnits - Points to the list of register units. The low 4 bits holds the 115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 116 uint32_t RegUnits; 117}; 118 119/// MCRegisterInfo base class - We assume that the target defines a static 120/// array of MCRegisterDesc objects that represent all of the machine 121/// registers that the target has. As such, we simply have to track a pointer 122/// to this array so that we can turn register number into a register 123/// descriptor. 124/// 125/// Note this class is designed to be a base class of TargetRegisterInfo, which 126/// is the interface used by codegen. However, specific targets *should never* 127/// specialize this class. MCRegisterInfo should only contain getters to access 128/// TableGen generated physical register data. It must not be extended with 129/// virtual methods. 130/// 131class MCRegisterInfo { 132public: 133 typedef const MCRegisterClass *regclass_iterator; 134 135 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 136 /// performed with a binary search. 137 struct DwarfLLVMRegPair { 138 unsigned FromReg; 139 unsigned ToReg; 140 141 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 142 }; 143private: 144 const MCRegisterDesc *Desc; // Pointer to the descriptor array 145 unsigned NumRegs; // Number of entries in the array 146 unsigned RAReg; // Return address register 147 const MCRegisterClass *Classes; // Pointer to the regclass array 148 unsigned NumClasses; // Number of entries in the array 149 unsigned NumRegUnits; // Number of regunits. 150 const uint16_t *RegLists; // Pointer to the reglists array 151 const uint16_t *DiffLists; // Pointer to the difflists array 152 const char *RegStrings; // Pointer to the string table. 153 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 154 // array. 155 unsigned NumSubRegIndices; // Number of subreg indices. 156 const uint16_t *RegEncodingTable; // Pointer to array of register 157 // encodings. 158 159 unsigned L2DwarfRegsSize; 160 unsigned EHL2DwarfRegsSize; 161 unsigned Dwarf2LRegsSize; 162 unsigned EHDwarf2LRegsSize; 163 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 164 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 165 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 166 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 167 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 168 169public: 170 /// RegListIterator. This iterator class is used to traverse lists of 171 /// super-registers, sub-registers, and overlapping registers. Don't use it 172 /// directly, use one of the sub-classes defined below. 173 class RegListIterator { 174 const uint16_t *Pos; 175 public: 176 explicit RegListIterator(const uint16_t *Table) 177 : Pos(Table) {} 178 179 /// isValid - Return false when the end of the list is reached. 180 bool isValid() const { return *Pos; } 181 182 /// Dereference the iterator to get the current register. 183 unsigned operator*() const { return *Pos; } 184 185 /// Pre-increment. Move to the next register. 186 void operator++() { ++Pos; } 187 }; 188 189 /// DiffListIterator - Base iterator class that can traverse the 190 /// differentially encoded register and regunit lists in DiffLists. 191 /// Don't use this class directly, use one of the specialized sub-classes 192 /// defined below. 193 class DiffListIterator { 194 uint16_t Val; 195 const uint16_t *List; 196 197 protected: 198 /// Create an invalid iterator. Call init() to point to something useful. 199 DiffListIterator() : Val(0), List(0) {} 200 201 /// init - Point the iterator to InitVal, decoding subsequent values from 202 /// DiffList. The iterator will initially point to InitVal, sub-classes are 203 /// responsible for skipping the seed value if it is not part of the list. 204 void init(uint16_t InitVal, const uint16_t *DiffList) { 205 Val = InitVal; 206 List = DiffList; 207 } 208 209 /// advance - Move to the next list position, return the applied 210 /// differential. This function does not detect the end of the list, that 211 /// is the caller's responsibility (by checking for a 0 return value). 212 unsigned advance() { 213 assert(isValid() && "Cannot move off the end of the list."); 214 uint16_t D = *List++; 215 Val += D; 216 return D; 217 } 218 219 public: 220 221 /// isValid - returns true if this iterator is not yet at the end. 222 bool isValid() const { return List; } 223 224 /// Dereference the iterator to get the value at the current position. 225 unsigned operator*() const { return Val; } 226 227 /// Pre-increment to move to the next position. 228 void operator++() { 229 // The end of the list is encoded as a 0 differential. 230 if (!advance()) 231 List = 0; 232 } 233 }; 234 235 // These iterators are allowed to sub-class RegListIterator and 236 // DiffListIterator and access internal list pointers. 237 friend class MCSubRegIterator; 238 friend class MCSuperRegIterator; 239 friend class MCRegAliasIterator; 240 friend class MCRegUnitIterator; 241 242 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 243 /// auto-generated routines. *DO NOT USE*. 244 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 245 const MCRegisterClass *C, unsigned NC, unsigned NRU, 246 const uint16_t *RL, 247 const uint16_t *DL, 248 const char *Strings, 249 const uint16_t *SubIndices, 250 unsigned NumIndices, 251 const uint16_t *RET) { 252 Desc = D; 253 NumRegs = NR; 254 RAReg = RA; 255 Classes = C; 256 RegLists = RL; 257 DiffLists = DL; 258 RegStrings = Strings; 259 NumClasses = NC; 260 NumRegUnits = NRU; 261 SubRegIndices = SubIndices; 262 NumSubRegIndices = NumIndices; 263 RegEncodingTable = RET; 264 } 265 266 /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf 267 /// register number mapping. Called by TableGen auto-generated routines. 268 /// *DO NOT USE*. 269 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 270 bool isEH) { 271 if (isEH) { 272 EHL2DwarfRegs = Map; 273 EHL2DwarfRegsSize = Size; 274 } else { 275 L2DwarfRegs = Map; 276 L2DwarfRegsSize = Size; 277 } 278 } 279 280 /// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM 281 /// register number mapping. Called by TableGen auto-generated routines. 282 /// *DO NOT USE*. 283 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 284 bool isEH) { 285 if (isEH) { 286 EHDwarf2LRegs = Map; 287 EHDwarf2LRegsSize = Size; 288 } else { 289 Dwarf2LRegs = Map; 290 Dwarf2LRegsSize = Size; 291 } 292 } 293 294 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 295 /// number mapping. By default the SEH register number is just the same 296 /// as the LLVM register number. 297 /// FIXME: TableGen these numbers. Currently this requires target specific 298 /// initialization code. 299 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 300 L2SEHRegs[LLVMReg] = SEHReg; 301 } 302 303 /// getRARegister - This method should return the register where the return 304 /// address can be found. 305 unsigned getRARegister() const { 306 return RAReg; 307 } 308 309 const MCRegisterDesc &operator[](unsigned RegNo) const { 310 assert(RegNo < NumRegs && 311 "Attempting to access record for invalid register number!"); 312 return Desc[RegNo]; 313 } 314 315 /// Provide a get method, equivalent to [], but more useful if we have a 316 /// pointer to this object. 317 /// 318 const MCRegisterDesc &get(unsigned RegNo) const { 319 return operator[](RegNo); 320 } 321 322 /// getAliasSet - Return the set of registers aliased by the specified 323 /// register, or a null list of there are none. The list returned is zero 324 /// terminated. 325 /// 326 const uint16_t *getAliasSet(unsigned RegNo) const { 327 // The Overlaps set always begins with Reg itself. 328 return RegLists + get(RegNo).Overlaps + 1; 329 } 330 331 /// getOverlaps - Return a list of registers that overlap Reg, including 332 /// itself. This is the same as the alias set except Reg is included in the 333 /// list. 334 /// These are exactly the registers in { x | regsOverlap(x, Reg) }. 335 /// 336 const uint16_t *getOverlaps(unsigned RegNo) const { 337 return RegLists + get(RegNo).Overlaps; 338 } 339 340 /// getSubRegisters - Return the list of registers that are sub-registers of 341 /// the specified register, or a null list of there are none. The list 342 /// returned is zero terminated and sorted according to super-sub register 343 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 344 /// 345 const uint16_t *getSubRegisters(unsigned RegNo) const { 346 return RegLists + get(RegNo).SubRegs; 347 } 348 349 /// getSubReg - Returns the physical register number of sub-register "Index" 350 /// for physical register RegNo. Return zero if the sub-register does not 351 /// exist. 352 unsigned getSubReg(unsigned Reg, unsigned Idx) const { 353 return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1); 354 } 355 356 /// getMatchingSuperReg - Return a super-register of the specified register 357 /// Reg so its sub-register of index SubIdx is Reg. 358 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 359 const MCRegisterClass *RC) const { 360 for (const uint16_t *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 361 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 362 return SR; 363 return 0; 364 } 365 366 /// getSubRegIndex - For a given register pair, return the sub-register index 367 /// if the second register is a sub-register of the first. Return zero 368 /// otherwise. 369 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const { 370 for (unsigned I = 1; I <= NumSubRegIndices; ++I) 371 if (getSubReg(RegNo, I) == SubRegNo) 372 return I; 373 return 0; 374 } 375 376 /// getSuperRegisters - Return the list of registers that are super-registers 377 /// of the specified register, or a null list of there are none. The list 378 /// returned is zero terminated and sorted according to super-sub register 379 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. 380 /// 381 const uint16_t *getSuperRegisters(unsigned RegNo) const { 382 return RegLists + get(RegNo).SuperRegs; 383 } 384 385 /// getName - Return the human-readable symbolic target-specific name for the 386 /// specified physical register. 387 const char *getName(unsigned RegNo) const { 388 return RegStrings + get(RegNo).Name; 389 } 390 391 /// getNumRegs - Return the number of registers this target has (useful for 392 /// sizing arrays holding per register information) 393 unsigned getNumRegs() const { 394 return NumRegs; 395 } 396 397 /// getNumRegUnits - Return the number of (native) register units in the 398 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 399 /// can be accessed through MCRegUnitIterator defined below. 400 unsigned getNumRegUnits() const { 401 return NumRegUnits; 402 } 403 404 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 405 /// number. Returns -1 if there is no equivalent value. The second 406 /// parameter allows targets to use different numberings for EH info and 407 /// debugging info. 408 int getDwarfRegNum(unsigned RegNum, bool isEH) const { 409 const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs; 410 unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize; 411 412 DwarfLLVMRegPair Key = { RegNum, 0 }; 413 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 414 if (I == M+Size || I->FromReg != RegNum) 415 return -1; 416 return I->ToReg; 417 } 418 419 /// getLLVMRegNum - Map a dwarf register back to a target register. 420 /// 421 int getLLVMRegNum(unsigned RegNum, bool isEH) const { 422 const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; 423 unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize; 424 425 DwarfLLVMRegPair Key = { RegNum, 0 }; 426 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 427 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); 428 return I->ToReg; 429 } 430 431 /// getSEHRegNum - Map a target register to an equivalent SEH register 432 /// number. Returns LLVM register number if there is no equivalent value. 433 int getSEHRegNum(unsigned RegNum) const { 434 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 435 if (I == L2SEHRegs.end()) return (int)RegNum; 436 return I->second; 437 } 438 439 regclass_iterator regclass_begin() const { return Classes; } 440 regclass_iterator regclass_end() const { return Classes+NumClasses; } 441 442 unsigned getNumRegClasses() const { 443 return (unsigned)(regclass_end()-regclass_begin()); 444 } 445 446 /// getRegClass - Returns the register class associated with the enumeration 447 /// value. See class MCOperandInfo. 448 const MCRegisterClass getRegClass(unsigned i) const { 449 assert(i < getNumRegClasses() && "Register Class ID out of range"); 450 return Classes[i]; 451 } 452 453 /// getEncodingValue - Returns the encoding for RegNo 454 uint16_t getEncodingValue(unsigned RegNo) const { 455 assert(RegNo < NumRegs && 456 "Attempting to get encoding for invalid register number!"); 457 return RegEncodingTable[RegNo]; 458 } 459 460}; 461 462//===----------------------------------------------------------------------===// 463// Register List Iterators 464//===----------------------------------------------------------------------===// 465 466// MCRegisterInfo provides lists of super-registers, sub-registers, and 467// aliasing registers. Use these iterator classes to traverse the lists. 468 469/// MCSubRegIterator enumerates all sub-registers of Reg. 470class MCSubRegIterator : public MCRegisterInfo::RegListIterator { 471public: 472 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) 473 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).SubRegs) {} 474}; 475 476/// MCSuperRegIterator enumerates all super-registers of Reg. 477class MCSuperRegIterator : public MCRegisterInfo::RegListIterator { 478public: 479 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) 480 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).SuperRegs) {} 481}; 482 483/// MCRegAliasIterator enumerates all registers aliasing Reg. 484/// If IncludeSelf is set, Reg itself is included in the list. 485class MCRegAliasIterator : public MCRegisterInfo::RegListIterator { 486public: 487 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf) 488 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).Overlaps + !IncludeSelf) 489 {} 490}; 491 492//===----------------------------------------------------------------------===// 493// Register Units 494//===----------------------------------------------------------------------===// 495 496// Register units are used to compute register aliasing. Every register has at 497// least one register unit, but it can have more. Two registers overlap if and 498// only if they have a common register unit. 499// 500// A target with a complicated sub-register structure will typically have many 501// fewer register units than actual registers. MCRI::getNumRegUnits() returns 502// the number of register units in the target. 503 504// MCRegUnitIterator enumerates a list of register units for Reg. The list is 505// in ascending numerical order. 506class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 507public: 508 /// MCRegUnitIterator - Create an iterator that traverses the register units 509 /// in Reg. 510 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 511 // Decode the RegUnits MCRegisterDesc field. 512 unsigned RU = MCRI->get(Reg).RegUnits; 513 unsigned Scale = RU & 15; 514 unsigned Offset = RU >> 4; 515 516 // Initialize the iterator to Reg * Scale, and the List pointer to 517 // DiffLists + Offset. 518 init(Reg * Scale, MCRI->DiffLists + Offset); 519 520 // That may not be a valid unit, we need to advance by one to get the real 521 // unit number. The first differential can be 0 which would normally 522 // terminate the list, but since we know every register has at least one 523 // unit, we can allow a 0 differential here. 524 advance(); 525 } 526}; 527 528} // End llvm namespace 529 530#endif 531