MCRegisterInfo.h revision f3e3783012dc7875ed37be8aaaefd96f98454781
1//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCREGISTERINFO_H 17#define LLVM_MC_MCREGISTERINFO_H 18 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/Support/ErrorHandling.h" 21#include <cassert> 22 23namespace llvm { 24 25/// MCRegisterClass - Base class of TargetRegisterClass. 26class MCRegisterClass { 27public: 28 typedef const unsigned* iterator; 29 typedef const unsigned* const_iterator; 30 31 unsigned ID; 32 const char *Name; 33 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 34 const int CopyCost; 35 const bool Allocatable; 36 const iterator RegsBegin; 37 unsigned RegsSize; 38 const unsigned char *const RegSet; 39 const unsigned RegSetSize; 40 41 /// getID() - Return the register class ID number. 42 /// 43 unsigned getID() const { return ID; } 44 45 /// getName() - Return the register class name for debugging. 46 /// 47 const char *getName() const { return Name; } 48 49 /// begin/end - Return all of the registers in this class. 50 /// 51 iterator begin() const { return RegsBegin; } 52 iterator end() const { return RegsBegin + RegsSize; } 53 54 /// getNumRegs - Return the number of registers in this class. 55 /// 56 unsigned getNumRegs() const { return RegsSize; } 57 58 /// getRegister - Return the specified register in the class. 59 /// 60 unsigned getRegister(unsigned i) const { 61 assert(i < getNumRegs() && "Register number out of range!"); 62 return RegsBegin[i]; 63 } 64 65 /// contains - Return true if the specified register is included in this 66 /// register class. This does not include virtual registers. 67 bool contains(unsigned Reg) const { 68 unsigned InByte = Reg % 8; 69 unsigned Byte = Reg / 8; 70 if (Byte >= RegSetSize) 71 return false; 72 return (RegSet[Byte] & (1 << InByte)) != 0; 73 } 74 75 /// contains - Return true if both registers are in this class. 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2); 78 } 79 80 /// getSize - Return the size of the register in bytes, which is also the size 81 /// of a stack slot allocated to hold a spilled copy of this register. 82 unsigned getSize() const { return RegSize; } 83 84 /// getAlignment - Return the minimum required alignment for a register of 85 /// this class. 86 unsigned getAlignment() const { return Alignment; } 87 88 /// getCopyCost - Return the cost of copying a value between two registers in 89 /// this class. A negative number means the register class is very expensive 90 /// to copy e.g. status flag register classes. 91 int getCopyCost() const { return CopyCost; } 92 93 /// isAllocatable - Return true if this register class may be used to create 94 /// virtual registers. 95 bool isAllocatable() const { return Allocatable; } 96}; 97 98/// MCRegisterDesc - This record contains all of the information known about 99/// a particular register. The Overlaps field contains a pointer to a zero 100/// terminated array of registers that this register aliases, starting with 101/// itself. This is needed for architectures like X86 which have AL alias AX 102/// alias EAX. The SubRegs field is a zero terminated array of registers that 103/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 104/// AX. The SuperRegs field is a zero terminated array of registers that are 105/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 106/// of AX. 107/// 108struct MCRegisterDesc { 109 const char *Name; // Printable name for the reg (for debugging) 110 int Overlaps; // Overlapping registers, described above 111 int SubRegs; // Sub-register set, described above 112 int SuperRegs; // Super-register set, described above 113}; 114 115/// MCRegisterInfo base class - We assume that the target defines a static 116/// array of MCRegisterDesc objects that represent all of the machine 117/// registers that the target has. As such, we simply have to track a pointer 118/// to this array so that we can turn register number into a register 119/// descriptor. 120/// 121/// Note this class is designed to be a base class of TargetRegisterInfo, which 122/// is the interface used by codegen. However, specific targets *should never* 123/// specialize this class. MCRegisterInfo should only contain getters to access 124/// TableGen generated physical register data. It must not be extended with 125/// virtual methods. 126/// 127class MCRegisterInfo { 128public: 129 typedef const MCRegisterClass *regclass_iterator; 130private: 131 const MCRegisterDesc *Desc; // Pointer to the descriptor array 132 unsigned NumRegs; // Number of entries in the array 133 unsigned RAReg; // Return address register 134 const MCRegisterClass *Classes; // Pointer to the regclass array 135 unsigned NumClasses; // Number of entries in the array 136 const unsigned *Overlaps; // Pointer to the overlaps array 137 const unsigned *SubRegs; // Pointer to the subregs array 138 const unsigned *SuperRegs; // Pointer to the superregs array 139 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping 140 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 141 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping 142 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 143 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 144 145public: 146 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 147 /// auto-generated routines. *DO NOT USE*. 148 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 149 const MCRegisterClass *C, unsigned NC, 150 const unsigned *O, const unsigned *Sub, 151 const unsigned *Super) { 152 Desc = D; 153 NumRegs = NR; 154 RAReg = RA; 155 Classes = C; 156 Overlaps = O; 157 SubRegs = Sub; 158 SuperRegs = Super; 159 NumClasses = NC; 160 } 161 162 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf 163 /// register number mapping. Called by TableGen auto-generated routines. 164 /// *DO NOT USE*. 165 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) { 166 if (isEH) 167 EHL2DwarfRegs[LLVMReg] = DwarfReg; 168 else 169 L2DwarfRegs[LLVMReg] = DwarfReg; 170 } 171 172 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM 173 /// register number mapping. Called by TableGen auto-generated routines. 174 /// *DO NOT USE*. 175 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) { 176 if (isEH) 177 EHDwarf2LRegs[DwarfReg] = LLVMReg; 178 else 179 Dwarf2LRegs[DwarfReg] = LLVMReg; 180 } 181 182 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 183 /// number mapping. By default the SEH register number is just the same 184 /// as the LLVM register number. 185 /// FIXME: TableGen these numbers. Currently this requires target specific 186 /// initialization code. 187 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 188 L2SEHRegs[LLVMReg] = SEHReg; 189 } 190 191 /// getRARegister - This method should return the register where the return 192 /// address can be found. 193 unsigned getRARegister() const { 194 return RAReg; 195 } 196 197 const MCRegisterDesc &operator[](unsigned RegNo) const { 198 assert(RegNo < NumRegs && 199 "Attempting to access record for invalid register number!"); 200 return Desc[RegNo]; 201 } 202 203 /// Provide a get method, equivalent to [], but more useful if we have a 204 /// pointer to this object. 205 /// 206 const MCRegisterDesc &get(unsigned RegNo) const { 207 return operator[](RegNo); 208 } 209 210 /// getAliasSet - Return the set of registers aliased by the specified 211 /// register, or a null list of there are none. The list returned is zero 212 /// terminated. 213 /// 214 const unsigned *getAliasSet(unsigned RegNo) const { 215 // The Overlaps set always begins with Reg itself. 216 if (get(RegNo).Overlaps < 0) return 0; 217 return Overlaps + get(RegNo).Overlaps + 1; 218 } 219 220 /// getOverlaps - Return a list of registers that overlap Reg, including 221 /// itself. This is the same as the alias set except Reg is included in the 222 /// list. 223 /// These are exactly the registers in { x | regsOverlap(x, Reg) }. 224 /// 225 const unsigned *getOverlaps(unsigned RegNo) const { 226 if (get(RegNo).Overlaps < 0) return 0; 227 return Overlaps + get(RegNo).Overlaps; 228 } 229 230 /// getSubRegisters - Return the list of registers that are sub-registers of 231 /// the specified register, or a null list of there are none. The list 232 /// returned is zero terminated and sorted according to super-sub register 233 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 234 /// 235 const unsigned *getSubRegisters(unsigned RegNo) const { 236 if (get(RegNo).SubRegs < 0) return 0; 237 return SubRegs + get(RegNo).SubRegs; 238 } 239 240 /// getSuperRegisters - Return the list of registers that are super-registers 241 /// of the specified register, or a null list of there are none. The list 242 /// returned is zero terminated and sorted according to super-sub register 243 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. 244 /// 245 const unsigned *getSuperRegisters(unsigned RegNo) const { 246 if (get(RegNo).SuperRegs < 0) return 0; 247 return SuperRegs + get(RegNo).SuperRegs; 248 } 249 250 /// getName - Return the human-readable symbolic target-specific name for the 251 /// specified physical register. 252 const char *getName(unsigned RegNo) const { 253 return get(RegNo).Name; 254 } 255 256 /// getNumRegs - Return the number of registers this target has (useful for 257 /// sizing arrays holding per register information) 258 unsigned getNumRegs() const { 259 return NumRegs; 260 } 261 262 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 263 /// number. Returns -1 if there is no equivalent value. The second 264 /// parameter allows targets to use different numberings for EH info and 265 /// debugging info. 266 int getDwarfRegNum(unsigned RegNum, bool isEH) const { 267 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs; 268 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum); 269 if (I == M.end()) return -1; 270 return I->second; 271 } 272 273 /// getLLVMRegNum - Map a dwarf register back to a target register. 274 /// 275 int getLLVMRegNum(unsigned RegNum, bool isEH) const { 276 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; 277 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum); 278 if (I == M.end()) { 279 llvm_unreachable("Invalid RegNum"); 280 } 281 return I->second; 282 } 283 284 /// getSEHRegNum - Map a target register to an equivalent SEH register 285 /// number. Returns LLVM register number if there is no equivalent value. 286 int getSEHRegNum(unsigned RegNum) const { 287 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 288 if (I == L2SEHRegs.end()) return (int)RegNum; 289 return I->second; 290 } 291 292 regclass_iterator regclass_begin() const { return Classes; } 293 regclass_iterator regclass_end() const { return Classes+NumClasses; } 294 295 unsigned getNumRegClasses() const { 296 return (unsigned)(regclass_end()-regclass_begin()); 297 } 298 299 /// getRegClass - Returns the register class associated with the enumeration 300 /// value. See class MCOperandInfo. 301 const MCRegisterClass getRegClass(unsigned i) const { 302 assert(i < getNumRegClasses() && "Register Class ID out of range"); 303 return Classes[i]; 304 } 305}; 306 307} // End llvm namespace 308 309#endif 310