1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAG::Legalize method.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/SelectionDAG.h"
15#include "llvm/ADT/SmallPtrSet.h"
16#include "llvm/ADT/SmallSet.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/CodeGen/Analysis.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineJumpTableInfo.h"
22#include "llvm/IR/CallingConv.h"
23#include "llvm/IR/Constants.h"
24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DebugInfo.h"
26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/LLVMContext.h"
29#include "llvm/Support/Debug.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/MathExtras.h"
32#include "llvm/Support/raw_ostream.h"
33#include "llvm/Target/TargetFrameLowering.h"
34#include "llvm/Target/TargetLowering.h"
35#include "llvm/Target/TargetMachine.h"
36using namespace llvm;
37
38//===----------------------------------------------------------------------===//
39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40/// hacks on it until the target machine can handle it.  This involves
41/// eliminating value sizes the machine cannot handle (promoting small sizes to
42/// large sizes or splitting up large values into small values) as well as
43/// eliminating operations the machine cannot handle.
44///
45/// This code also does a small amount of optimization and recognition of idioms
46/// as part of its processing.  For example, if a target does not support a
47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48/// will attempt merge setcc and brc instructions into brcc's.
49///
50namespace {
51class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
52  const TargetMachine &TM;
53  const TargetLowering &TLI;
54  SelectionDAG &DAG;
55
56  /// LegalizePosition - The iterator for walking through the node list.
57  SelectionDAG::allnodes_iterator LegalizePosition;
58
59  /// LegalizedNodes - The set of nodes which have already been legalized.
60  SmallPtrSet<SDNode *, 16> LegalizedNodes;
61
62  EVT getSetCCResultType(EVT VT) const {
63    return TLI.getSetCCResultType(*DAG.getContext(), VT);
64  }
65
66  // Libcall insertion helpers.
67
68public:
69  explicit SelectionDAGLegalize(SelectionDAG &DAG);
70
71  void LegalizeDAG();
72
73private:
74  /// LegalizeOp - Legalizes the given operation.
75  void LegalizeOp(SDNode *Node);
76
77  SDValue OptimizeFloatStore(StoreSDNode *ST);
78
79  void LegalizeLoadOps(SDNode *Node);
80  void LegalizeStoreOps(SDNode *Node);
81
82  /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
83  /// insertion index for the INSERT_VECTOR_ELT instruction.  In this case, it
84  /// is necessary to spill the vector being inserted into to memory, perform
85  /// the insert there, and then read the result back.
86  SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
87                                         SDValue Idx, SDLoc dl);
88  SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
89                                  SDValue Idx, SDLoc dl);
90
91  /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
92  /// performs the same shuffe in terms of order or result bytes, but on a type
93  /// whose vector element type is narrower than the original shuffle type.
94  /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
95  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
96                                     SDValue N1, SDValue N2,
97                                     ArrayRef<int> Mask) const;
98
99  bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
100                             bool &NeedInvert, SDLoc dl);
101
102  SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
103  SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
104                        unsigned NumOps, bool isSigned, SDLoc dl);
105
106  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
107                                                 SDNode *Node, bool isSigned);
108  SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
109                          RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
110                          RTLIB::Libcall Call_F128,
111                          RTLIB::Libcall Call_PPCF128);
112  SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
113                           RTLIB::Libcall Call_I8,
114                           RTLIB::Libcall Call_I16,
115                           RTLIB::Libcall Call_I32,
116                           RTLIB::Libcall Call_I64,
117                           RTLIB::Libcall Call_I128);
118  void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
119  void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
120
121  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
122  SDValue ExpandBUILD_VECTOR(SDNode *Node);
123  SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
124  void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
125                                SmallVectorImpl<SDValue> &Results);
126  SDValue ExpandFCOPYSIGN(SDNode *Node);
127  SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128                               SDLoc dl);
129  SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130                                SDLoc dl);
131  SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
132                                SDLoc dl);
133
134  SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
135  SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
136
137  SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
138  SDValue ExpandInsertToVectorThroughStack(SDValue Op);
139  SDValue ExpandVectorBuildThroughStack(SDNode* Node);
140
141  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
142
143  std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
144
145  void ExpandNode(SDNode *Node);
146  void PromoteNode(SDNode *Node);
147
148  void ForgetNode(SDNode *N) {
149    LegalizedNodes.erase(N);
150    if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
151      ++LegalizePosition;
152  }
153
154public:
155  // DAGUpdateListener implementation.
156  void NodeDeleted(SDNode *N, SDNode *E) override {
157    ForgetNode(N);
158  }
159  void NodeUpdated(SDNode *N) override {}
160
161  // Node replacement helpers
162  void ReplacedNode(SDNode *N) {
163    if (N->use_empty()) {
164      DAG.RemoveDeadNode(N);
165    } else {
166      ForgetNode(N);
167    }
168  }
169  void ReplaceNode(SDNode *Old, SDNode *New) {
170    DAG.ReplaceAllUsesWith(Old, New);
171    ReplacedNode(Old);
172  }
173  void ReplaceNode(SDValue Old, SDValue New) {
174    DAG.ReplaceAllUsesWith(Old, New);
175    ReplacedNode(Old.getNode());
176  }
177  void ReplaceNode(SDNode *Old, const SDValue *New) {
178    DAG.ReplaceAllUsesWith(Old, New);
179    ReplacedNode(Old);
180  }
181};
182}
183
184/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
185/// performs the same shuffe in terms of order or result bytes, but on a type
186/// whose vector element type is narrower than the original shuffle type.
187/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188SDValue
189SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT,  SDLoc dl,
190                                                 SDValue N1, SDValue N2,
191                                                 ArrayRef<int> Mask) const {
192  unsigned NumMaskElts = VT.getVectorNumElements();
193  unsigned NumDestElts = NVT.getVectorNumElements();
194  unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195
196  assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197
198  if (NumEltsGrowth == 1)
199    return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200
201  SmallVector<int, 8> NewMask;
202  for (unsigned i = 0; i != NumMaskElts; ++i) {
203    int Idx = Mask[i];
204    for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205      if (Idx < 0)
206        NewMask.push_back(-1);
207      else
208        NewMask.push_back(Idx * NumEltsGrowth + j);
209    }
210  }
211  assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
212  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
213  return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
214}
215
216SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
217  : SelectionDAG::DAGUpdateListener(dag),
218    TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
219    DAG(dag) {
220}
221
222void SelectionDAGLegalize::LegalizeDAG() {
223  DAG.AssignTopologicalOrder();
224
225  // Visit all the nodes. We start in topological order, so that we see
226  // nodes with their original operands intact. Legalization can produce
227  // new nodes which may themselves need to be legalized. Iterate until all
228  // nodes have been legalized.
229  for (;;) {
230    bool AnyLegalized = false;
231    for (LegalizePosition = DAG.allnodes_end();
232         LegalizePosition != DAG.allnodes_begin(); ) {
233      --LegalizePosition;
234
235      SDNode *N = LegalizePosition;
236      if (LegalizedNodes.insert(N)) {
237        AnyLegalized = true;
238        LegalizeOp(N);
239      }
240    }
241    if (!AnyLegalized)
242      break;
243
244  }
245
246  // Remove dead nodes now.
247  DAG.RemoveDeadNodes();
248}
249
250/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
251/// a load from the constant pool.
252SDValue
253SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
254  bool Extend = false;
255  SDLoc dl(CFP);
256
257  // If a FP immediate is precise when represented as a float and if the
258  // target can do an extending load from float to double, we put it into
259  // the constant pool as a float, even if it's is statically typed as a
260  // double.  This shrinks FP constants and canonicalizes them for targets where
261  // an FP extending load is the same cost as a normal load (such as on the x87
262  // fp stack or PPC FP unit).
263  EVT VT = CFP->getValueType(0);
264  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
265  if (!UseCP) {
266    assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
267    return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
268                           (VT == MVT::f64) ? MVT::i64 : MVT::i32);
269  }
270
271  EVT OrigVT = VT;
272  EVT SVT = VT;
273  while (SVT != MVT::f32) {
274    SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
275    if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
276        // Only do this if the target has a native EXTLOAD instruction from
277        // smaller type.
278        TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
279        TLI.ShouldShrinkFPConstant(OrigVT)) {
280      Type *SType = SVT.getTypeForEVT(*DAG.getContext());
281      LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
282      VT = SVT;
283      Extend = true;
284    }
285  }
286
287  SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
288  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
289  if (Extend) {
290    SDValue Result =
291      DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
292                     DAG.getEntryNode(),
293                     CPIdx, MachinePointerInfo::getConstantPool(),
294                     VT, false, false, Alignment);
295    return Result;
296  }
297  SDValue Result =
298    DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
299                MachinePointerInfo::getConstantPool(), false, false, false,
300                Alignment);
301  return Result;
302}
303
304/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
305static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
306                                 const TargetLowering &TLI,
307                                 SelectionDAGLegalize *DAGLegalize) {
308  assert(ST->getAddressingMode() == ISD::UNINDEXED &&
309         "unaligned indexed stores not implemented!");
310  SDValue Chain = ST->getChain();
311  SDValue Ptr = ST->getBasePtr();
312  SDValue Val = ST->getValue();
313  EVT VT = Val.getValueType();
314  int Alignment = ST->getAlignment();
315  unsigned AS = ST->getAddressSpace();
316
317  SDLoc dl(ST);
318  if (ST->getMemoryVT().isFloatingPoint() ||
319      ST->getMemoryVT().isVector()) {
320    EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
321    if (TLI.isTypeLegal(intVT)) {
322      // Expand to a bitconvert of the value to the integer type of the
323      // same size, then a (misaligned) int store.
324      // FIXME: Does not handle truncating floating point stores!
325      SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
326      Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
327                           ST->isVolatile(), ST->isNonTemporal(), Alignment);
328      DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
329      return;
330    }
331    // Do a (aligned) store to a stack slot, then copy from the stack slot
332    // to the final destination using (unaligned) integer loads and stores.
333    EVT StoredVT = ST->getMemoryVT();
334    MVT RegVT =
335      TLI.getRegisterType(*DAG.getContext(),
336                          EVT::getIntegerVT(*DAG.getContext(),
337                                            StoredVT.getSizeInBits()));
338    unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
339    unsigned RegBytes = RegVT.getSizeInBits() / 8;
340    unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
341
342    // Make sure the stack slot is also aligned for the register type.
343    SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
344
345    // Perform the original store, only redirected to the stack slot.
346    SDValue Store = DAG.getTruncStore(Chain, dl,
347                                      Val, StackPtr, MachinePointerInfo(),
348                                      StoredVT, false, false, 0);
349    SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
350    SmallVector<SDValue, 8> Stores;
351    unsigned Offset = 0;
352
353    // Do all but one copies using the full register width.
354    for (unsigned i = 1; i < NumRegs; i++) {
355      // Load one integer register's worth from the stack slot.
356      SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
357                                 MachinePointerInfo(),
358                                 false, false, false, 0);
359      // Store it to the final location.  Remember the store.
360      Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
361                                  ST->getPointerInfo().getWithOffset(Offset),
362                                    ST->isVolatile(), ST->isNonTemporal(),
363                                    MinAlign(ST->getAlignment(), Offset)));
364      // Increment the pointers.
365      Offset += RegBytes;
366      StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
367                             Increment);
368      Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
369    }
370
371    // The last store may be partial.  Do a truncating store.  On big-endian
372    // machines this requires an extending load from the stack slot to ensure
373    // that the bits are in the right place.
374    EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
375                                  8 * (StoredBytes - Offset));
376
377    // Load from the stack slot.
378    SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
379                                  MachinePointerInfo(),
380                                  MemVT, false, false, 0);
381
382    Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
383                                       ST->getPointerInfo()
384                                         .getWithOffset(Offset),
385                                       MemVT, ST->isVolatile(),
386                                       ST->isNonTemporal(),
387                                       MinAlign(ST->getAlignment(), Offset),
388                                       ST->getTBAAInfo()));
389    // The order of the stores doesn't matter - say it with a TokenFactor.
390    SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
391    DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
392    return;
393  }
394  assert(ST->getMemoryVT().isInteger() &&
395         !ST->getMemoryVT().isVector() &&
396         "Unaligned store of unknown type.");
397  // Get the half-size VT
398  EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
399  int NumBits = NewStoredVT.getSizeInBits();
400  int IncrementSize = NumBits / 8;
401
402  // Divide the stored value in two parts.
403  SDValue ShiftAmount = DAG.getConstant(NumBits,
404                                      TLI.getShiftAmountTy(Val.getValueType()));
405  SDValue Lo = Val;
406  SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
407
408  // Store the two parts
409  SDValue Store1, Store2;
410  Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
411                             ST->getPointerInfo(), NewStoredVT,
412                             ST->isVolatile(), ST->isNonTemporal(), Alignment);
413
414  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
415                    DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
416  Alignment = MinAlign(Alignment, IncrementSize);
417  Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
418                             ST->getPointerInfo().getWithOffset(IncrementSize),
419                             NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
420                             Alignment, ST->getTBAAInfo());
421
422  SDValue Result =
423    DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
424  DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
425}
426
427/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
428static void
429ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
430                    const TargetLowering &TLI,
431                    SDValue &ValResult, SDValue &ChainResult) {
432  assert(LD->getAddressingMode() == ISD::UNINDEXED &&
433         "unaligned indexed loads not implemented!");
434  SDValue Chain = LD->getChain();
435  SDValue Ptr = LD->getBasePtr();
436  EVT VT = LD->getValueType(0);
437  EVT LoadedVT = LD->getMemoryVT();
438  SDLoc dl(LD);
439  if (VT.isFloatingPoint() || VT.isVector()) {
440    EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
441    if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
442      // Expand to a (misaligned) integer load of the same size,
443      // then bitconvert to floating point or vector.
444      SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
445                                    LD->getMemOperand());
446      SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
447      if (LoadedVT != VT)
448        Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
449                             ISD::ANY_EXTEND, dl, VT, Result);
450
451      ValResult = Result;
452      ChainResult = Chain;
453      return;
454    }
455
456    // Copy the value to a (aligned) stack slot using (unaligned) integer
457    // loads and stores, then do a (aligned) load from the stack slot.
458    MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
459    unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
460    unsigned RegBytes = RegVT.getSizeInBits() / 8;
461    unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
462
463    // Make sure the stack slot is also aligned for the register type.
464    SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
465
466    SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
467    SmallVector<SDValue, 8> Stores;
468    SDValue StackPtr = StackBase;
469    unsigned Offset = 0;
470
471    // Do all but one copies using the full register width.
472    for (unsigned i = 1; i < NumRegs; i++) {
473      // Load one integer register's worth from the original location.
474      SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
475                                 LD->getPointerInfo().getWithOffset(Offset),
476                                 LD->isVolatile(), LD->isNonTemporal(),
477                                 LD->isInvariant(),
478                                 MinAlign(LD->getAlignment(), Offset),
479                                 LD->getTBAAInfo());
480      // Follow the load with a store to the stack slot.  Remember the store.
481      Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
482                                    MachinePointerInfo(), false, false, 0));
483      // Increment the pointers.
484      Offset += RegBytes;
485      Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
486      StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
487                             Increment);
488    }
489
490    // The last copy may be partial.  Do an extending load.
491    EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
492                                  8 * (LoadedBytes - Offset));
493    SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
494                                  LD->getPointerInfo().getWithOffset(Offset),
495                                  MemVT, LD->isVolatile(),
496                                  LD->isNonTemporal(),
497                                  MinAlign(LD->getAlignment(), Offset),
498                                  LD->getTBAAInfo());
499    // Follow the load with a store to the stack slot.  Remember the store.
500    // On big-endian machines this requires a truncating store to ensure
501    // that the bits end up in the right place.
502    Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
503                                       MachinePointerInfo(), MemVT,
504                                       false, false, 0));
505
506    // The order of the stores doesn't matter - say it with a TokenFactor.
507    SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
508
509    // Finally, perform the original load only redirected to the stack slot.
510    Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
511                          MachinePointerInfo(), LoadedVT, false, false, 0);
512
513    // Callers expect a MERGE_VALUES node.
514    ValResult = Load;
515    ChainResult = TF;
516    return;
517  }
518  assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
519         "Unaligned load of unsupported type.");
520
521  // Compute the new VT that is half the size of the old one.  This is an
522  // integer MVT.
523  unsigned NumBits = LoadedVT.getSizeInBits();
524  EVT NewLoadedVT;
525  NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
526  NumBits >>= 1;
527
528  unsigned Alignment = LD->getAlignment();
529  unsigned IncrementSize = NumBits / 8;
530  ISD::LoadExtType HiExtType = LD->getExtensionType();
531
532  // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
533  if (HiExtType == ISD::NON_EXTLOAD)
534    HiExtType = ISD::ZEXTLOAD;
535
536  // Load the value in two parts
537  SDValue Lo, Hi;
538  if (TLI.isLittleEndian()) {
539    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
540                        NewLoadedVT, LD->isVolatile(),
541                        LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
542    Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
543                      DAG.getConstant(IncrementSize, Ptr.getValueType()));
544    Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
545                        LD->getPointerInfo().getWithOffset(IncrementSize),
546                        NewLoadedVT, LD->isVolatile(),
547                        LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
548                        LD->getTBAAInfo());
549  } else {
550    Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
551                        NewLoadedVT, LD->isVolatile(),
552                        LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
553    Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
554                      DAG.getConstant(IncrementSize, Ptr.getValueType()));
555    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
556                        LD->getPointerInfo().getWithOffset(IncrementSize),
557                        NewLoadedVT, LD->isVolatile(),
558                        LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
559                        LD->getTBAAInfo());
560  }
561
562  // aggregate the two parts
563  SDValue ShiftAmount = DAG.getConstant(NumBits,
564                                       TLI.getShiftAmountTy(Hi.getValueType()));
565  SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
566  Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
567
568  SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
569                             Hi.getValue(1));
570
571  ValResult = Result;
572  ChainResult = TF;
573}
574
575/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
576/// insertion index for the INSERT_VECTOR_ELT instruction.  In this case, it
577/// is necessary to spill the vector being inserted into to memory, perform
578/// the insert there, and then read the result back.
579SDValue SelectionDAGLegalize::
580PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
581                               SDLoc dl) {
582  SDValue Tmp1 = Vec;
583  SDValue Tmp2 = Val;
584  SDValue Tmp3 = Idx;
585
586  // If the target doesn't support this, we have to spill the input vector
587  // to a temporary stack slot, update the element, then reload it.  This is
588  // badness.  We could also load the value into a vector register (either
589  // with a "move to register" or "extload into register" instruction, then
590  // permute it into place, if the idx is a constant and if the idx is
591  // supported by the target.
592  EVT VT    = Tmp1.getValueType();
593  EVT EltVT = VT.getVectorElementType();
594  EVT IdxVT = Tmp3.getValueType();
595  EVT PtrVT = TLI.getPointerTy();
596  SDValue StackPtr = DAG.CreateStackTemporary(VT);
597
598  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
599
600  // Store the vector.
601  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
602                            MachinePointerInfo::getFixedStack(SPFI),
603                            false, false, 0);
604
605  // Truncate or zero extend offset to target pointer type.
606  unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
607  Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
608  // Add the offset to the index.
609  unsigned EltSize = EltVT.getSizeInBits()/8;
610  Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
611  SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
612  // Store the scalar value.
613  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
614                         false, false, 0);
615  // Load the updated vector.
616  return DAG.getLoad(VT, dl, Ch, StackPtr,
617                     MachinePointerInfo::getFixedStack(SPFI), false, false,
618                     false, 0);
619}
620
621
622SDValue SelectionDAGLegalize::
623ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
624  if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
625    // SCALAR_TO_VECTOR requires that the type of the value being inserted
626    // match the element type of the vector being created, except for
627    // integers in which case the inserted value can be over width.
628    EVT EltVT = Vec.getValueType().getVectorElementType();
629    if (Val.getValueType() == EltVT ||
630        (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
631      SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
632                                  Vec.getValueType(), Val);
633
634      unsigned NumElts = Vec.getValueType().getVectorNumElements();
635      // We generate a shuffle of InVec and ScVec, so the shuffle mask
636      // should be 0,1,2,3,4,5... with the appropriate element replaced with
637      // elt 0 of the RHS.
638      SmallVector<int, 8> ShufOps;
639      for (unsigned i = 0; i != NumElts; ++i)
640        ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
641
642      return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
643                                  &ShufOps[0]);
644    }
645  }
646  return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
647}
648
649SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
650  // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
651  // FIXME: We shouldn't do this for TargetConstantFP's.
652  // FIXME: move this to the DAG Combiner!  Note that we can't regress due
653  // to phase ordering between legalized code and the dag combiner.  This
654  // probably means that we need to integrate dag combiner and legalizer
655  // together.
656  // We generally can't do this one for long doubles.
657  SDValue Chain = ST->getChain();
658  SDValue Ptr = ST->getBasePtr();
659  unsigned Alignment = ST->getAlignment();
660  bool isVolatile = ST->isVolatile();
661  bool isNonTemporal = ST->isNonTemporal();
662  const MDNode *TBAAInfo = ST->getTBAAInfo();
663  SDLoc dl(ST);
664  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
665    if (CFP->getValueType(0) == MVT::f32 &&
666        TLI.isTypeLegal(MVT::i32)) {
667      SDValue Con = DAG.getConstant(CFP->getValueAPF().
668                                      bitcastToAPInt().zextOrTrunc(32),
669                              MVT::i32);
670      return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
671                          isVolatile, isNonTemporal, Alignment, TBAAInfo);
672    }
673
674    if (CFP->getValueType(0) == MVT::f64) {
675      // If this target supports 64-bit registers, do a single 64-bit store.
676      if (TLI.isTypeLegal(MVT::i64)) {
677        SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
678                                  zextOrTrunc(64), MVT::i64);
679        return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
680                            isVolatile, isNonTemporal, Alignment, TBAAInfo);
681      }
682
683      if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
684        // Otherwise, if the target supports 32-bit registers, use 2 32-bit
685        // stores.  If the target supports neither 32- nor 64-bits, this
686        // xform is certainly not worth it.
687        const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
688        SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
689        SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
690        if (TLI.isBigEndian()) std::swap(Lo, Hi);
691
692        Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
693                          isNonTemporal, Alignment, TBAAInfo);
694        Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
695                          DAG.getConstant(4, Ptr.getValueType()));
696        Hi = DAG.getStore(Chain, dl, Hi, Ptr,
697                          ST->getPointerInfo().getWithOffset(4),
698                          isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
699                          TBAAInfo);
700
701        return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
702      }
703    }
704  }
705  return SDValue(nullptr, 0);
706}
707
708void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
709    StoreSDNode *ST = cast<StoreSDNode>(Node);
710    SDValue Chain = ST->getChain();
711    SDValue Ptr = ST->getBasePtr();
712    SDLoc dl(Node);
713
714    unsigned Alignment = ST->getAlignment();
715    bool isVolatile = ST->isVolatile();
716    bool isNonTemporal = ST->isNonTemporal();
717    const MDNode *TBAAInfo = ST->getTBAAInfo();
718
719    if (!ST->isTruncatingStore()) {
720      if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
721        ReplaceNode(ST, OptStore);
722        return;
723      }
724
725      {
726        SDValue Value = ST->getValue();
727        MVT VT = Value.getSimpleValueType();
728        switch (TLI.getOperationAction(ISD::STORE, VT)) {
729        default: llvm_unreachable("This action is not supported yet!");
730        case TargetLowering::Legal: {
731          // If this is an unaligned store and the target doesn't support it,
732          // expand it.
733          unsigned AS = ST->getAddressSpace();
734          if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
735            Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
736            unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
737            if (ST->getAlignment() < ABIAlignment)
738              ExpandUnalignedStore(cast<StoreSDNode>(Node),
739                                   DAG, TLI, this);
740          }
741          break;
742        }
743        case TargetLowering::Custom: {
744          SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
745          if (Res.getNode())
746            ReplaceNode(SDValue(Node, 0), Res);
747          return;
748        }
749        case TargetLowering::Promote: {
750          MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
751          assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
752                 "Can only promote stores to same size type");
753          Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
754          SDValue Result =
755            DAG.getStore(Chain, dl, Value, Ptr,
756                         ST->getPointerInfo(), isVolatile,
757                         isNonTemporal, Alignment, TBAAInfo);
758          ReplaceNode(SDValue(Node, 0), Result);
759          break;
760        }
761        }
762        return;
763      }
764    } else {
765      SDValue Value = ST->getValue();
766
767      EVT StVT = ST->getMemoryVT();
768      unsigned StWidth = StVT.getSizeInBits();
769
770      if (StWidth != StVT.getStoreSizeInBits()) {
771        // Promote to a byte-sized store with upper bits zero if not
772        // storing an integral number of bytes.  For example, promote
773        // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
774        EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
775                                    StVT.getStoreSizeInBits());
776        Value = DAG.getZeroExtendInReg(Value, dl, StVT);
777        SDValue Result =
778          DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
779                            NVT, isVolatile, isNonTemporal, Alignment,
780                            TBAAInfo);
781        ReplaceNode(SDValue(Node, 0), Result);
782      } else if (StWidth & (StWidth - 1)) {
783        // If not storing a power-of-2 number of bits, expand as two stores.
784        assert(!StVT.isVector() && "Unsupported truncstore!");
785        unsigned RoundWidth = 1 << Log2_32(StWidth);
786        assert(RoundWidth < StWidth);
787        unsigned ExtraWidth = StWidth - RoundWidth;
788        assert(ExtraWidth < RoundWidth);
789        assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
790               "Store size not an integral number of bytes!");
791        EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
792        EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
793        SDValue Lo, Hi;
794        unsigned IncrementSize;
795
796        if (TLI.isLittleEndian()) {
797          // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
798          // Store the bottom RoundWidth bits.
799          Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
800                                 RoundVT,
801                                 isVolatile, isNonTemporal, Alignment,
802                                 TBAAInfo);
803
804          // Store the remaining ExtraWidth bits.
805          IncrementSize = RoundWidth / 8;
806          Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
807                            DAG.getConstant(IncrementSize, Ptr.getValueType()));
808          Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
809                           DAG.getConstant(RoundWidth,
810                                   TLI.getShiftAmountTy(Value.getValueType())));
811          Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
812                             ST->getPointerInfo().getWithOffset(IncrementSize),
813                                 ExtraVT, isVolatile, isNonTemporal,
814                                 MinAlign(Alignment, IncrementSize), TBAAInfo);
815        } else {
816          // Big endian - avoid unaligned stores.
817          // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
818          // Store the top RoundWidth bits.
819          Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
820                           DAG.getConstant(ExtraWidth,
821                                   TLI.getShiftAmountTy(Value.getValueType())));
822          Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
823                                 RoundVT, isVolatile, isNonTemporal, Alignment,
824                                 TBAAInfo);
825
826          // Store the remaining ExtraWidth bits.
827          IncrementSize = RoundWidth / 8;
828          Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
829                            DAG.getConstant(IncrementSize, Ptr.getValueType()));
830          Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
831                              ST->getPointerInfo().getWithOffset(IncrementSize),
832                                 ExtraVT, isVolatile, isNonTemporal,
833                                 MinAlign(Alignment, IncrementSize), TBAAInfo);
834        }
835
836        // The order of the stores doesn't matter.
837        SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
838        ReplaceNode(SDValue(Node, 0), Result);
839      } else {
840        switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
841                                        StVT.getSimpleVT())) {
842        default: llvm_unreachable("This action is not supported yet!");
843        case TargetLowering::Legal: {
844          unsigned AS = ST->getAddressSpace();
845          // If this is an unaligned store and the target doesn't support it,
846          // expand it.
847          if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
848            Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
849            unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
850            if (ST->getAlignment() < ABIAlignment)
851              ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
852          }
853          break;
854        }
855        case TargetLowering::Custom: {
856          SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
857          if (Res.getNode())
858            ReplaceNode(SDValue(Node, 0), Res);
859          return;
860        }
861        case TargetLowering::Expand:
862          assert(!StVT.isVector() &&
863                 "Vector Stores are handled in LegalizeVectorOps");
864
865          // TRUNCSTORE:i16 i32 -> STORE i16
866          assert(TLI.isTypeLegal(StVT) &&
867                 "Do not know how to expand this store!");
868          Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
869          SDValue Result =
870            DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
871                         isVolatile, isNonTemporal, Alignment, TBAAInfo);
872          ReplaceNode(SDValue(Node, 0), Result);
873          break;
874        }
875      }
876    }
877}
878
879void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
880  LoadSDNode *LD = cast<LoadSDNode>(Node);
881  SDValue Chain = LD->getChain();  // The chain.
882  SDValue Ptr = LD->getBasePtr();  // The base pointer.
883  SDValue Value;                   // The value returned by the load op.
884  SDLoc dl(Node);
885
886  ISD::LoadExtType ExtType = LD->getExtensionType();
887  if (ExtType == ISD::NON_EXTLOAD) {
888    MVT VT = Node->getSimpleValueType(0);
889    SDValue RVal = SDValue(Node, 0);
890    SDValue RChain = SDValue(Node, 1);
891
892    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
893    default: llvm_unreachable("This action is not supported yet!");
894    case TargetLowering::Legal: {
895      unsigned AS = LD->getAddressSpace();
896      // If this is an unaligned load and the target doesn't support it,
897      // expand it.
898      if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT(), AS)) {
899        Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
900        unsigned ABIAlignment =
901          TLI.getDataLayout()->getABITypeAlignment(Ty);
902        if (LD->getAlignment() < ABIAlignment){
903          ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
904        }
905      }
906      break;
907    }
908    case TargetLowering::Custom: {
909      SDValue Res = TLI.LowerOperation(RVal, DAG);
910      if (Res.getNode()) {
911        RVal = Res;
912        RChain = Res.getValue(1);
913      }
914      break;
915    }
916    case TargetLowering::Promote: {
917      MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
918      assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
919             "Can only promote loads to same size type");
920
921      SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
922      RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
923      RChain = Res.getValue(1);
924      break;
925    }
926    }
927    if (RChain.getNode() != Node) {
928      assert(RVal.getNode() != Node && "Load must be completely replaced");
929      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
930      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
931      ReplacedNode(Node);
932    }
933    return;
934  }
935
936  EVT SrcVT = LD->getMemoryVT();
937  unsigned SrcWidth = SrcVT.getSizeInBits();
938  unsigned Alignment = LD->getAlignment();
939  bool isVolatile = LD->isVolatile();
940  bool isNonTemporal = LD->isNonTemporal();
941  const MDNode *TBAAInfo = LD->getTBAAInfo();
942
943  if (SrcWidth != SrcVT.getStoreSizeInBits() &&
944      // Some targets pretend to have an i1 loading operation, and actually
945      // load an i8.  This trick is correct for ZEXTLOAD because the top 7
946      // bits are guaranteed to be zero; it helps the optimizers understand
947      // that these bits are zero.  It is also useful for EXTLOAD, since it
948      // tells the optimizers that those bits are undefined.  It would be
949      // nice to have an effective generic way of getting these benefits...
950      // Until such a way is found, don't insist on promoting i1 here.
951      (SrcVT != MVT::i1 ||
952       TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
953    // Promote to a byte-sized load if not loading an integral number of
954    // bytes.  For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
955    unsigned NewWidth = SrcVT.getStoreSizeInBits();
956    EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
957    SDValue Ch;
958
959    // The extra bits are guaranteed to be zero, since we stored them that
960    // way.  A zext load from NVT thus automatically gives zext from SrcVT.
961
962    ISD::LoadExtType NewExtType =
963      ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
964
965    SDValue Result =
966      DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
967                     Chain, Ptr, LD->getPointerInfo(),
968                     NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
969
970    Ch = Result.getValue(1); // The chain.
971
972    if (ExtType == ISD::SEXTLOAD)
973      // Having the top bits zero doesn't help when sign extending.
974      Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
975                           Result.getValueType(),
976                           Result, DAG.getValueType(SrcVT));
977    else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
978      // All the top bits are guaranteed to be zero - inform the optimizers.
979      Result = DAG.getNode(ISD::AssertZext, dl,
980                           Result.getValueType(), Result,
981                           DAG.getValueType(SrcVT));
982
983    Value = Result;
984    Chain = Ch;
985  } else if (SrcWidth & (SrcWidth - 1)) {
986    // If not loading a power-of-2 number of bits, expand as two loads.
987    assert(!SrcVT.isVector() && "Unsupported extload!");
988    unsigned RoundWidth = 1 << Log2_32(SrcWidth);
989    assert(RoundWidth < SrcWidth);
990    unsigned ExtraWidth = SrcWidth - RoundWidth;
991    assert(ExtraWidth < RoundWidth);
992    assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
993           "Load size not an integral number of bytes!");
994    EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
995    EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
996    SDValue Lo, Hi, Ch;
997    unsigned IncrementSize;
998
999    if (TLI.isLittleEndian()) {
1000      // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1001      // Load the bottom RoundWidth bits.
1002      Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1003                          Chain, Ptr,
1004                          LD->getPointerInfo(), RoundVT, isVolatile,
1005                          isNonTemporal, Alignment, TBAAInfo);
1006
1007      // Load the remaining ExtraWidth bits.
1008      IncrementSize = RoundWidth / 8;
1009      Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1010                         DAG.getConstant(IncrementSize, Ptr.getValueType()));
1011      Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1012                          LD->getPointerInfo().getWithOffset(IncrementSize),
1013                          ExtraVT, isVolatile, isNonTemporal,
1014                          MinAlign(Alignment, IncrementSize), TBAAInfo);
1015
1016      // Build a factor node to remember that this load is independent of
1017      // the other one.
1018      Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1019                       Hi.getValue(1));
1020
1021      // Move the top bits to the right place.
1022      Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1023                       DAG.getConstant(RoundWidth,
1024                                      TLI.getShiftAmountTy(Hi.getValueType())));
1025
1026      // Join the hi and lo parts.
1027      Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1028    } else {
1029      // Big endian - avoid unaligned loads.
1030      // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1031      // Load the top RoundWidth bits.
1032      Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1033                          LD->getPointerInfo(), RoundVT, isVolatile,
1034                          isNonTemporal, Alignment, TBAAInfo);
1035
1036      // Load the remaining ExtraWidth bits.
1037      IncrementSize = RoundWidth / 8;
1038      Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1039                         DAG.getConstant(IncrementSize, Ptr.getValueType()));
1040      Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1041                          dl, Node->getValueType(0), Chain, Ptr,
1042                          LD->getPointerInfo().getWithOffset(IncrementSize),
1043                          ExtraVT, isVolatile, isNonTemporal,
1044                          MinAlign(Alignment, IncrementSize), TBAAInfo);
1045
1046      // Build a factor node to remember that this load is independent of
1047      // the other one.
1048      Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1049                       Hi.getValue(1));
1050
1051      // Move the top bits to the right place.
1052      Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1053                       DAG.getConstant(ExtraWidth,
1054                                      TLI.getShiftAmountTy(Hi.getValueType())));
1055
1056      // Join the hi and lo parts.
1057      Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1058    }
1059
1060    Chain = Ch;
1061  } else {
1062    bool isCustom = false;
1063    switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1064    default: llvm_unreachable("This action is not supported yet!");
1065    case TargetLowering::Custom:
1066      isCustom = true;
1067      // FALLTHROUGH
1068    case TargetLowering::Legal: {
1069      Value = SDValue(Node, 0);
1070      Chain = SDValue(Node, 1);
1071
1072      if (isCustom) {
1073        SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1074        if (Res.getNode()) {
1075          Value = Res;
1076          Chain = Res.getValue(1);
1077        }
1078      } else {
1079        // If this is an unaligned load and the target doesn't support
1080        // it, expand it.
1081        EVT MemVT = LD->getMemoryVT();
1082        unsigned AS = LD->getAddressSpace();
1083        if (!TLI.allowsUnalignedMemoryAccesses(MemVT, AS)) {
1084          Type *Ty =
1085            LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1086          unsigned ABIAlignment =
1087            TLI.getDataLayout()->getABITypeAlignment(Ty);
1088          if (LD->getAlignment() < ABIAlignment){
1089            ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1090                                DAG, TLI, Value, Chain);
1091          }
1092        }
1093      }
1094      break;
1095    }
1096    case TargetLowering::Expand:
1097      if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1098          TLI.isTypeLegal(SrcVT)) {
1099        SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1100                                   LD->getMemOperand());
1101        unsigned ExtendOp;
1102        switch (ExtType) {
1103        case ISD::EXTLOAD:
1104          ExtendOp = (SrcVT.isFloatingPoint() ?
1105                      ISD::FP_EXTEND : ISD::ANY_EXTEND);
1106          break;
1107        case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1108        case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1109        default: llvm_unreachable("Unexpected extend load type!");
1110        }
1111        Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1112        Chain = Load.getValue(1);
1113        break;
1114      }
1115
1116      assert(!SrcVT.isVector() &&
1117             "Vector Loads are handled in LegalizeVectorOps");
1118
1119      // FIXME: This does not work for vectors on most targets.  Sign-
1120      // and zero-extend operations are currently folded into extending
1121      // loads, whether they are legal or not, and then we end up here
1122      // without any support for legalizing them.
1123      assert(ExtType != ISD::EXTLOAD &&
1124             "EXTLOAD should always be supported!");
1125      // Turn the unsupported load into an EXTLOAD followed by an
1126      // explicit zero/sign extend inreg.
1127      SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1128                                      Node->getValueType(0),
1129                                      Chain, Ptr, SrcVT,
1130                                      LD->getMemOperand());
1131      SDValue ValRes;
1132      if (ExtType == ISD::SEXTLOAD)
1133        ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1134                             Result.getValueType(),
1135                             Result, DAG.getValueType(SrcVT));
1136      else
1137        ValRes = DAG.getZeroExtendInReg(Result, dl,
1138                                        SrcVT.getScalarType());
1139      Value = ValRes;
1140      Chain = Result.getValue(1);
1141      break;
1142    }
1143  }
1144
1145  // Since loads produce two values, make sure to remember that we legalized
1146  // both of them.
1147  if (Chain.getNode() != Node) {
1148    assert(Value.getNode() != Node && "Load must be completely replaced");
1149    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1150    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1151    ReplacedNode(Node);
1152  }
1153}
1154
1155/// LegalizeOp - Return a legal replacement for the given operation, with
1156/// all legal operands.
1157void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1158  if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1159    return;
1160
1161  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1162    assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1163             TargetLowering::TypeLegal &&
1164           "Unexpected illegal type!");
1165
1166  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1167    assert((TLI.getTypeAction(*DAG.getContext(),
1168                              Node->getOperand(i).getValueType()) ==
1169              TargetLowering::TypeLegal ||
1170            Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1171           "Unexpected illegal type!");
1172
1173  // Figure out the correct action; the way to query this varies by opcode
1174  TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1175  bool SimpleFinishLegalizing = true;
1176  switch (Node->getOpcode()) {
1177  case ISD::INTRINSIC_W_CHAIN:
1178  case ISD::INTRINSIC_WO_CHAIN:
1179  case ISD::INTRINSIC_VOID:
1180  case ISD::STACKSAVE:
1181    Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1182    break;
1183  case ISD::VAARG:
1184    Action = TLI.getOperationAction(Node->getOpcode(),
1185                                    Node->getValueType(0));
1186    if (Action != TargetLowering::Promote)
1187      Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1188    break;
1189  case ISD::SINT_TO_FP:
1190  case ISD::UINT_TO_FP:
1191  case ISD::EXTRACT_VECTOR_ELT:
1192    Action = TLI.getOperationAction(Node->getOpcode(),
1193                                    Node->getOperand(0).getValueType());
1194    break;
1195  case ISD::FP_ROUND_INREG:
1196  case ISD::SIGN_EXTEND_INREG: {
1197    EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1198    Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1199    break;
1200  }
1201  case ISD::ATOMIC_STORE: {
1202    Action = TLI.getOperationAction(Node->getOpcode(),
1203                                    Node->getOperand(2).getValueType());
1204    break;
1205  }
1206  case ISD::SELECT_CC:
1207  case ISD::SETCC:
1208  case ISD::BR_CC: {
1209    unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1210                         Node->getOpcode() == ISD::SETCC ? 2 : 1;
1211    unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1212    MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1213    ISD::CondCode CCCode =
1214        cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1215    Action = TLI.getCondCodeAction(CCCode, OpVT);
1216    if (Action == TargetLowering::Legal) {
1217      if (Node->getOpcode() == ISD::SELECT_CC)
1218        Action = TLI.getOperationAction(Node->getOpcode(),
1219                                        Node->getValueType(0));
1220      else
1221        Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1222    }
1223    break;
1224  }
1225  case ISD::LOAD:
1226  case ISD::STORE:
1227    // FIXME: Model these properly.  LOAD and STORE are complicated, and
1228    // STORE expects the unlegalized operand in some cases.
1229    SimpleFinishLegalizing = false;
1230    break;
1231  case ISD::CALLSEQ_START:
1232  case ISD::CALLSEQ_END:
1233    // FIXME: This shouldn't be necessary.  These nodes have special properties
1234    // dealing with the recursive nature of legalization.  Removing this
1235    // special case should be done as part of making LegalizeDAG non-recursive.
1236    SimpleFinishLegalizing = false;
1237    break;
1238  case ISD::EXTRACT_ELEMENT:
1239  case ISD::FLT_ROUNDS_:
1240  case ISD::SADDO:
1241  case ISD::SSUBO:
1242  case ISD::UADDO:
1243  case ISD::USUBO:
1244  case ISD::SMULO:
1245  case ISD::UMULO:
1246  case ISD::FPOWI:
1247  case ISD::MERGE_VALUES:
1248  case ISD::EH_RETURN:
1249  case ISD::FRAME_TO_ARGS_OFFSET:
1250  case ISD::EH_SJLJ_SETJMP:
1251  case ISD::EH_SJLJ_LONGJMP:
1252    // These operations lie about being legal: when they claim to be legal,
1253    // they should actually be expanded.
1254    Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1255    if (Action == TargetLowering::Legal)
1256      Action = TargetLowering::Expand;
1257    break;
1258  case ISD::INIT_TRAMPOLINE:
1259  case ISD::ADJUST_TRAMPOLINE:
1260  case ISD::FRAMEADDR:
1261  case ISD::RETURNADDR:
1262    // These operations lie about being legal: when they claim to be legal,
1263    // they should actually be custom-lowered.
1264    Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1265    if (Action == TargetLowering::Legal)
1266      Action = TargetLowering::Custom;
1267    break;
1268  case ISD::READ_REGISTER:
1269  case ISD::WRITE_REGISTER:
1270    // Named register is legal in the DAG, but blocked by register name
1271    // selection if not implemented by target (to chose the correct register)
1272    // They'll be converted to Copy(To/From)Reg.
1273    Action = TargetLowering::Legal;
1274    break;
1275  case ISD::DEBUGTRAP:
1276    Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1277    if (Action == TargetLowering::Expand) {
1278      // replace ISD::DEBUGTRAP with ISD::TRAP
1279      SDValue NewVal;
1280      NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1281                           Node->getOperand(0));
1282      ReplaceNode(Node, NewVal.getNode());
1283      LegalizeOp(NewVal.getNode());
1284      return;
1285    }
1286    break;
1287
1288  default:
1289    if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1290      Action = TargetLowering::Legal;
1291    } else {
1292      Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1293    }
1294    break;
1295  }
1296
1297  if (SimpleFinishLegalizing) {
1298    SDNode *NewNode = Node;
1299    switch (Node->getOpcode()) {
1300    default: break;
1301    case ISD::SHL:
1302    case ISD::SRL:
1303    case ISD::SRA:
1304    case ISD::ROTL:
1305    case ISD::ROTR:
1306      // Legalizing shifts/rotates requires adjusting the shift amount
1307      // to the appropriate width.
1308      if (!Node->getOperand(1).getValueType().isVector()) {
1309        SDValue SAO =
1310          DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1311                                    Node->getOperand(1));
1312        HandleSDNode Handle(SAO);
1313        LegalizeOp(SAO.getNode());
1314        NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1315                                         Handle.getValue());
1316      }
1317      break;
1318    case ISD::SRL_PARTS:
1319    case ISD::SRA_PARTS:
1320    case ISD::SHL_PARTS:
1321      // Legalizing shifts/rotates requires adjusting the shift amount
1322      // to the appropriate width.
1323      if (!Node->getOperand(2).getValueType().isVector()) {
1324        SDValue SAO =
1325          DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1326                                    Node->getOperand(2));
1327        HandleSDNode Handle(SAO);
1328        LegalizeOp(SAO.getNode());
1329        NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1330                                         Node->getOperand(1),
1331                                         Handle.getValue());
1332      }
1333      break;
1334    }
1335
1336    if (NewNode != Node) {
1337      DAG.ReplaceAllUsesWith(Node, NewNode);
1338      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1339        DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1340      ReplacedNode(Node);
1341      Node = NewNode;
1342    }
1343    switch (Action) {
1344    case TargetLowering::Legal:
1345      return;
1346    case TargetLowering::Custom: {
1347      // FIXME: The handling for custom lowering with multiple results is
1348      // a complete mess.
1349      SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1350      if (Res.getNode()) {
1351        SmallVector<SDValue, 8> ResultVals;
1352        for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1353          if (e == 1)
1354            ResultVals.push_back(Res);
1355          else
1356            ResultVals.push_back(Res.getValue(i));
1357        }
1358        if (Res.getNode() != Node || Res.getResNo() != 0) {
1359          DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1360          for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1361            DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1362          ReplacedNode(Node);
1363        }
1364        return;
1365      }
1366    }
1367      // FALL THROUGH
1368    case TargetLowering::Expand:
1369      ExpandNode(Node);
1370      return;
1371    case TargetLowering::Promote:
1372      PromoteNode(Node);
1373      return;
1374    }
1375  }
1376
1377  switch (Node->getOpcode()) {
1378  default:
1379#ifndef NDEBUG
1380    dbgs() << "NODE: ";
1381    Node->dump( &DAG);
1382    dbgs() << "\n";
1383#endif
1384    llvm_unreachable("Do not know how to legalize this operator!");
1385
1386  case ISD::CALLSEQ_START:
1387  case ISD::CALLSEQ_END:
1388    break;
1389  case ISD::LOAD: {
1390    return LegalizeLoadOps(Node);
1391  }
1392  case ISD::STORE: {
1393    return LegalizeStoreOps(Node);
1394  }
1395  }
1396}
1397
1398SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1399  SDValue Vec = Op.getOperand(0);
1400  SDValue Idx = Op.getOperand(1);
1401  SDLoc dl(Op);
1402
1403  // Before we generate a new store to a temporary stack slot, see if there is
1404  // already one that we can use. There often is because when we scalarize
1405  // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1406  // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1407  // the vector. If all are expanded here, we don't want one store per vector
1408  // element.
1409  SDValue StackPtr, Ch;
1410  for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1411       UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1412    SDNode *User = *UI;
1413    if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1414      if (ST->isIndexed() || ST->isTruncatingStore() ||
1415          ST->getValue() != Vec)
1416        continue;
1417
1418      // Make sure that nothing else could have stored into the destination of
1419      // this store.
1420      if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1421        continue;
1422
1423      StackPtr = ST->getBasePtr();
1424      Ch = SDValue(ST, 0);
1425      break;
1426    }
1427  }
1428
1429  if (!Ch.getNode()) {
1430    // Store the value to a temporary stack slot, then LOAD the returned part.
1431    StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1432    Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1433                      MachinePointerInfo(), false, false, 0);
1434  }
1435
1436  // Add the offset to the index.
1437  unsigned EltSize =
1438      Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1439  Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1440                    DAG.getConstant(EltSize, Idx.getValueType()));
1441
1442  Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1443  StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1444
1445  if (Op.getValueType().isVector())
1446    return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1447                       false, false, false, 0);
1448  return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1449                        MachinePointerInfo(),
1450                        Vec.getValueType().getVectorElementType(),
1451                        false, false, 0);
1452}
1453
1454SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1455  assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1456
1457  SDValue Vec  = Op.getOperand(0);
1458  SDValue Part = Op.getOperand(1);
1459  SDValue Idx  = Op.getOperand(2);
1460  SDLoc dl(Op);
1461
1462  // Store the value to a temporary stack slot, then LOAD the returned part.
1463
1464  SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1465  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1466  MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1467
1468  // First store the whole vector.
1469  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1470                            false, false, 0);
1471
1472  // Then store the inserted part.
1473
1474  // Add the offset to the index.
1475  unsigned EltSize =
1476      Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1477
1478  Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1479                    DAG.getConstant(EltSize, Idx.getValueType()));
1480  Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1481
1482  SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1483                                    StackPtr);
1484
1485  // Store the subvector.
1486  Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1487                    MachinePointerInfo(), false, false, 0);
1488
1489  // Finally, load the updated vector.
1490  return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1491                     false, false, false, 0);
1492}
1493
1494SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1495  // We can't handle this case efficiently.  Allocate a sufficiently
1496  // aligned object on the stack, store each element into it, then load
1497  // the result as a vector.
1498  // Create the stack frame object.
1499  EVT VT = Node->getValueType(0);
1500  EVT EltVT = VT.getVectorElementType();
1501  SDLoc dl(Node);
1502  SDValue FIPtr = DAG.CreateStackTemporary(VT);
1503  int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1504  MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1505
1506  // Emit a store of each element to the stack slot.
1507  SmallVector<SDValue, 8> Stores;
1508  unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1509  // Store (in the right endianness) the elements to memory.
1510  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1511    // Ignore undef elements.
1512    if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1513
1514    unsigned Offset = TypeByteSize*i;
1515
1516    SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1517    Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1518
1519    // If the destination vector element type is narrower than the source
1520    // element type, only store the bits necessary.
1521    if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1522      Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1523                                         Node->getOperand(i), Idx,
1524                                         PtrInfo.getWithOffset(Offset),
1525                                         EltVT, false, false, 0));
1526    } else
1527      Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1528                                    Node->getOperand(i), Idx,
1529                                    PtrInfo.getWithOffset(Offset),
1530                                    false, false, 0));
1531  }
1532
1533  SDValue StoreChain;
1534  if (!Stores.empty())    // Not all undef elements?
1535    StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1536  else
1537    StoreChain = DAG.getEntryNode();
1538
1539  // Result is a load from the stack slot.
1540  return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1541                     false, false, false, 0);
1542}
1543
1544SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1545  SDLoc dl(Node);
1546  SDValue Tmp1 = Node->getOperand(0);
1547  SDValue Tmp2 = Node->getOperand(1);
1548
1549  // Get the sign bit of the RHS.  First obtain a value that has the same
1550  // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1551  SDValue SignBit;
1552  EVT FloatVT = Tmp2.getValueType();
1553  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1554  if (TLI.isTypeLegal(IVT)) {
1555    // Convert to an integer with the same sign bit.
1556    SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1557  } else {
1558    // Store the float to memory, then load the sign part out as an integer.
1559    MVT LoadTy = TLI.getPointerTy();
1560    // First create a temporary that is aligned for both the load and store.
1561    SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1562    // Then store the float to it.
1563    SDValue Ch =
1564      DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1565                   false, false, 0);
1566    if (TLI.isBigEndian()) {
1567      assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1568      // Load out a legal integer with the same sign bit as the float.
1569      SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1570                            false, false, false, 0);
1571    } else { // Little endian
1572      SDValue LoadPtr = StackPtr;
1573      // The float may be wider than the integer we are going to load.  Advance
1574      // the pointer so that the loaded integer will contain the sign bit.
1575      unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1576      unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1577      LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1578                           DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1579      // Load a legal integer containing the sign bit.
1580      SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1581                            false, false, false, 0);
1582      // Move the sign bit to the top bit of the loaded integer.
1583      unsigned BitShift = LoadTy.getSizeInBits() -
1584        (FloatVT.getSizeInBits() - 8 * ByteOffset);
1585      assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1586      if (BitShift)
1587        SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1588                              DAG.getConstant(BitShift,
1589                                 TLI.getShiftAmountTy(SignBit.getValueType())));
1590    }
1591  }
1592  // Now get the sign bit proper, by seeing whether the value is negative.
1593  SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1594                         SignBit, DAG.getConstant(0, SignBit.getValueType()),
1595                         ISD::SETLT);
1596  // Get the absolute value of the result.
1597  SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1598  // Select between the nabs and abs value based on the sign bit of
1599  // the input.
1600  return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1601                      DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1602                      AbsVal);
1603}
1604
1605void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1606                                           SmallVectorImpl<SDValue> &Results) {
1607  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1608  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1609          " not tell us which reg is the stack pointer!");
1610  SDLoc dl(Node);
1611  EVT VT = Node->getValueType(0);
1612  SDValue Tmp1 = SDValue(Node, 0);
1613  SDValue Tmp2 = SDValue(Node, 1);
1614  SDValue Tmp3 = Node->getOperand(2);
1615  SDValue Chain = Tmp1.getOperand(0);
1616
1617  // Chain the dynamic stack allocation so that it doesn't modify the stack
1618  // pointer when other instructions are using the stack.
1619  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1620                               SDLoc(Node));
1621
1622  SDValue Size  = Tmp2.getOperand(1);
1623  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1624  Chain = SP.getValue(1);
1625  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1626  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1627  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size);       // Value
1628  if (Align > StackAlign)
1629    Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1630                       DAG.getConstant(-(uint64_t)Align, VT));
1631  Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1);     // Output chain
1632
1633  Tmp2 = DAG.getCALLSEQ_END(Chain,  DAG.getIntPtrConstant(0, true),
1634                            DAG.getIntPtrConstant(0, true), SDValue(),
1635                            SDLoc(Node));
1636
1637  Results.push_back(Tmp1);
1638  Results.push_back(Tmp2);
1639}
1640
1641/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1642/// condition code CC on the current target.
1643///
1644/// If the SETCC has been legalized using AND / OR, then the legalized node
1645/// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1646/// will be set to false.
1647///
1648/// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1649/// then the values of LHS and RHS will be swapped, CC will be set to the
1650/// new condition, and NeedInvert will be set to false.
1651///
1652/// If the SETCC has been legalized using the inverse condcode, then LHS and
1653/// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1654/// will be set to true. The caller must invert the result of the SETCC with
1655/// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1656/// of a true/false result.
1657///
1658/// \returns true if the SetCC has been legalized, false if it hasn't.
1659bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1660                                                 SDValue &LHS, SDValue &RHS,
1661                                                 SDValue &CC,
1662                                                 bool &NeedInvert,
1663                                                 SDLoc dl) {
1664  MVT OpVT = LHS.getSimpleValueType();
1665  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1666  NeedInvert = false;
1667  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1668  default: llvm_unreachable("Unknown condition code action!");
1669  case TargetLowering::Legal:
1670    // Nothing to do.
1671    break;
1672  case TargetLowering::Expand: {
1673    ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1674    if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1675      std::swap(LHS, RHS);
1676      CC = DAG.getCondCode(InvCC);
1677      return true;
1678    }
1679    ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1680    unsigned Opc = 0;
1681    switch (CCCode) {
1682    default: llvm_unreachable("Don't know how to expand this condition!");
1683    case ISD::SETO:
1684        assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1685            == TargetLowering::Legal
1686            && "If SETO is expanded, SETOEQ must be legal!");
1687        CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1688    case ISD::SETUO:
1689        assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1690            == TargetLowering::Legal
1691            && "If SETUO is expanded, SETUNE must be legal!");
1692        CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR;  break;
1693    case ISD::SETOEQ:
1694    case ISD::SETOGT:
1695    case ISD::SETOGE:
1696    case ISD::SETOLT:
1697    case ISD::SETOLE:
1698    case ISD::SETONE:
1699    case ISD::SETUEQ:
1700    case ISD::SETUNE:
1701    case ISD::SETUGT:
1702    case ISD::SETUGE:
1703    case ISD::SETULT:
1704    case ISD::SETULE:
1705        // If we are floating point, assign and break, otherwise fall through.
1706        if (!OpVT.isInteger()) {
1707          // We can use the 4th bit to tell if we are the unordered
1708          // or ordered version of the opcode.
1709          CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1710          Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1711          CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1712          break;
1713        }
1714        // Fallthrough if we are unsigned integer.
1715    case ISD::SETLE:
1716    case ISD::SETGT:
1717    case ISD::SETGE:
1718    case ISD::SETLT:
1719      // We only support using the inverted operation, which is computed above
1720      // and not a different manner of supporting expanding these cases.
1721      llvm_unreachable("Don't know how to expand this condition!");
1722    case ISD::SETNE:
1723    case ISD::SETEQ:
1724      // Try inverting the result of the inverse condition.
1725      InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1726      if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1727        CC = DAG.getCondCode(InvCC);
1728        NeedInvert = true;
1729        return true;
1730      }
1731      // If inverting the condition didn't work then we have no means to expand
1732      // the condition.
1733      llvm_unreachable("Don't know how to expand this condition!");
1734    }
1735
1736    SDValue SetCC1, SetCC2;
1737    if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1738      // If we aren't the ordered or unorder operation,
1739      // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1740      SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1741      SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1742    } else {
1743      // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1744      SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1745      SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1746    }
1747    LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1748    RHS = SDValue();
1749    CC  = SDValue();
1750    return true;
1751  }
1752  }
1753  return false;
1754}
1755
1756/// EmitStackConvert - Emit a store/load combination to the stack.  This stores
1757/// SrcOp to a stack slot of type SlotVT, truncating it if needed.  It then does
1758/// a load from the stack slot to DestVT, extending it if needed.
1759/// The resultant code need not be legal.
1760SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1761                                               EVT SlotVT,
1762                                               EVT DestVT,
1763                                               SDLoc dl) {
1764  // Create the stack frame object.
1765  unsigned SrcAlign =
1766    TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1767                                              getTypeForEVT(*DAG.getContext()));
1768  SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1769
1770  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1771  int SPFI = StackPtrFI->getIndex();
1772  MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1773
1774  unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1775  unsigned SlotSize = SlotVT.getSizeInBits();
1776  unsigned DestSize = DestVT.getSizeInBits();
1777  Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1778  unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1779
1780  // Emit a store to the stack slot.  Use a truncstore if the input value is
1781  // later than DestVT.
1782  SDValue Store;
1783
1784  if (SrcSize > SlotSize)
1785    Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1786                              PtrInfo, SlotVT, false, false, SrcAlign);
1787  else {
1788    assert(SrcSize == SlotSize && "Invalid store");
1789    Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1790                         PtrInfo, false, false, SrcAlign);
1791  }
1792
1793  // Result is a load from the stack slot.
1794  if (SlotSize == DestSize)
1795    return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1796                       false, false, false, DestAlign);
1797
1798  assert(SlotSize < DestSize && "Unknown extension!");
1799  return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1800                        PtrInfo, SlotVT, false, false, DestAlign);
1801}
1802
1803SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1804  SDLoc dl(Node);
1805  // Create a vector sized/aligned stack slot, store the value to element #0,
1806  // then load the whole vector back out.
1807  SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1808
1809  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1810  int SPFI = StackPtrFI->getIndex();
1811
1812  SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1813                                 StackPtr,
1814                                 MachinePointerInfo::getFixedStack(SPFI),
1815                                 Node->getValueType(0).getVectorElementType(),
1816                                 false, false, 0);
1817  return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1818                     MachinePointerInfo::getFixedStack(SPFI),
1819                     false, false, false, 0);
1820}
1821
1822static bool
1823ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1824                     const TargetLowering &TLI, SDValue &Res) {
1825  unsigned NumElems = Node->getNumOperands();
1826  SDLoc dl(Node);
1827  EVT VT = Node->getValueType(0);
1828
1829  // Try to group the scalars into pairs, shuffle the pairs together, then
1830  // shuffle the pairs of pairs together, etc. until the vector has
1831  // been built. This will work only if all of the necessary shuffle masks
1832  // are legal.
1833
1834  // We do this in two phases; first to check the legality of the shuffles,
1835  // and next, assuming that all shuffles are legal, to create the new nodes.
1836  for (int Phase = 0; Phase < 2; ++Phase) {
1837    SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1838                                                               NewIntermedVals;
1839    for (unsigned i = 0; i < NumElems; ++i) {
1840      SDValue V = Node->getOperand(i);
1841      if (V.getOpcode() == ISD::UNDEF)
1842        continue;
1843
1844      SDValue Vec;
1845      if (Phase)
1846        Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1847      IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1848    }
1849
1850    while (IntermedVals.size() > 2) {
1851      NewIntermedVals.clear();
1852      for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1853        // This vector and the next vector are shuffled together (simply to
1854        // append the one to the other).
1855        SmallVector<int, 16> ShuffleVec(NumElems, -1);
1856
1857        SmallVector<int, 16> FinalIndices;
1858        FinalIndices.reserve(IntermedVals[i].second.size() +
1859                             IntermedVals[i+1].second.size());
1860
1861        int k = 0;
1862        for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1863             ++j, ++k) {
1864          ShuffleVec[k] = j;
1865          FinalIndices.push_back(IntermedVals[i].second[j]);
1866        }
1867        for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1868             ++j, ++k) {
1869          ShuffleVec[k] = NumElems + j;
1870          FinalIndices.push_back(IntermedVals[i+1].second[j]);
1871        }
1872
1873        SDValue Shuffle;
1874        if (Phase)
1875          Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1876                                         IntermedVals[i+1].first,
1877                                         ShuffleVec.data());
1878        else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1879          return false;
1880        NewIntermedVals.push_back(std::make_pair(Shuffle, FinalIndices));
1881      }
1882
1883      // If we had an odd number of defined values, then append the last
1884      // element to the array of new vectors.
1885      if ((IntermedVals.size() & 1) != 0)
1886        NewIntermedVals.push_back(IntermedVals.back());
1887
1888      IntermedVals.swap(NewIntermedVals);
1889    }
1890
1891    assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1892           "Invalid number of intermediate vectors");
1893    SDValue Vec1 = IntermedVals[0].first;
1894    SDValue Vec2;
1895    if (IntermedVals.size() > 1)
1896      Vec2 = IntermedVals[1].first;
1897    else if (Phase)
1898      Vec2 = DAG.getUNDEF(VT);
1899
1900    SmallVector<int, 16> ShuffleVec(NumElems, -1);
1901    for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1902      ShuffleVec[IntermedVals[0].second[i]] = i;
1903    for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1904      ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1905
1906    if (Phase)
1907      Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1908    else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1909      return false;
1910  }
1911
1912  return true;
1913}
1914
1915/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1916/// support the operation, but do support the resultant vector type.
1917SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1918  unsigned NumElems = Node->getNumOperands();
1919  SDValue Value1, Value2;
1920  SDLoc dl(Node);
1921  EVT VT = Node->getValueType(0);
1922  EVT OpVT = Node->getOperand(0).getValueType();
1923  EVT EltVT = VT.getVectorElementType();
1924
1925  // If the only non-undef value is the low element, turn this into a
1926  // SCALAR_TO_VECTOR node.  If this is { X, X, X, X }, determine X.
1927  bool isOnlyLowElement = true;
1928  bool MoreThanTwoValues = false;
1929  bool isConstant = true;
1930  for (unsigned i = 0; i < NumElems; ++i) {
1931    SDValue V = Node->getOperand(i);
1932    if (V.getOpcode() == ISD::UNDEF)
1933      continue;
1934    if (i > 0)
1935      isOnlyLowElement = false;
1936    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1937      isConstant = false;
1938
1939    if (!Value1.getNode()) {
1940      Value1 = V;
1941    } else if (!Value2.getNode()) {
1942      if (V != Value1)
1943        Value2 = V;
1944    } else if (V != Value1 && V != Value2) {
1945      MoreThanTwoValues = true;
1946    }
1947  }
1948
1949  if (!Value1.getNode())
1950    return DAG.getUNDEF(VT);
1951
1952  if (isOnlyLowElement)
1953    return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1954
1955  // If all elements are constants, create a load from the constant pool.
1956  if (isConstant) {
1957    SmallVector<Constant*, 16> CV;
1958    for (unsigned i = 0, e = NumElems; i != e; ++i) {
1959      if (ConstantFPSDNode *V =
1960          dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1961        CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1962      } else if (ConstantSDNode *V =
1963                 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1964        if (OpVT==EltVT)
1965          CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1966        else {
1967          // If OpVT and EltVT don't match, EltVT is not legal and the
1968          // element values have been promoted/truncated earlier.  Undo this;
1969          // we don't want a v16i8 to become a v16i32 for example.
1970          const ConstantInt *CI = V->getConstantIntValue();
1971          CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1972                                        CI->getZExtValue()));
1973        }
1974      } else {
1975        assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1976        Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1977        CV.push_back(UndefValue::get(OpNTy));
1978      }
1979    }
1980    Constant *CP = ConstantVector::get(CV);
1981    SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1982    unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1983    return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1984                       MachinePointerInfo::getConstantPool(),
1985                       false, false, false, Alignment);
1986  }
1987
1988  SmallSet<SDValue, 16> DefinedValues;
1989  for (unsigned i = 0; i < NumElems; ++i) {
1990    if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
1991      continue;
1992    DefinedValues.insert(Node->getOperand(i));
1993  }
1994
1995  if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1996    if (!MoreThanTwoValues) {
1997      SmallVector<int, 8> ShuffleVec(NumElems, -1);
1998      for (unsigned i = 0; i < NumElems; ++i) {
1999        SDValue V = Node->getOperand(i);
2000        if (V.getOpcode() == ISD::UNDEF)
2001          continue;
2002        ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2003      }
2004      if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2005        // Get the splatted value into the low element of a vector register.
2006        SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2007        SDValue Vec2;
2008        if (Value2.getNode())
2009          Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2010        else
2011          Vec2 = DAG.getUNDEF(VT);
2012
2013        // Return shuffle(LowValVec, undef, <0,0,0,0>)
2014        return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2015      }
2016    } else {
2017      SDValue Res;
2018      if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2019        return Res;
2020    }
2021  }
2022
2023  // Otherwise, we can't handle this case efficiently.
2024  return ExpandVectorBuildThroughStack(Node);
2025}
2026
2027// ExpandLibCall - Expand a node into a call to a libcall.  If the result value
2028// does not fit into a register, return the lo part and set the hi part to the
2029// by-reg argument.  If it does fit into a single register, return the result
2030// and leave the Hi part unset.
2031SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2032                                            bool isSigned) {
2033  TargetLowering::ArgListTy Args;
2034  TargetLowering::ArgListEntry Entry;
2035  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2036    EVT ArgVT = Node->getOperand(i).getValueType();
2037    Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2038    Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2039    Entry.isSExt = isSigned;
2040    Entry.isZExt = !isSigned;
2041    Args.push_back(Entry);
2042  }
2043  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2044                                         TLI.getPointerTy());
2045
2046  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2047
2048  // By default, the input chain to this libcall is the entry node of the
2049  // function. If the libcall is going to be emitted as a tail call then
2050  // TLI.isUsedByReturnOnly will change it to the right chain if the return
2051  // node which is being folded has a non-entry input chain.
2052  SDValue InChain = DAG.getEntryNode();
2053
2054  // isTailCall may be true since the callee does not reference caller stack
2055  // frame. Check if it's in the right position.
2056  SDValue TCChain = InChain;
2057  bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2058  if (isTailCall)
2059    InChain = TCChain;
2060
2061  TargetLowering::CallLoweringInfo CLI(DAG);
2062  CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2063    .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2064    .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2065
2066  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2067
2068  if (!CallInfo.second.getNode())
2069    // It's a tailcall, return the chain (which is the DAG root).
2070    return DAG.getRoot();
2071
2072  return CallInfo.first;
2073}
2074
2075/// ExpandLibCall - Generate a libcall taking the given operands as arguments
2076/// and returning a result of type RetVT.
2077SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2078                                            const SDValue *Ops, unsigned NumOps,
2079                                            bool isSigned, SDLoc dl) {
2080  TargetLowering::ArgListTy Args;
2081  Args.reserve(NumOps);
2082
2083  TargetLowering::ArgListEntry Entry;
2084  for (unsigned i = 0; i != NumOps; ++i) {
2085    Entry.Node = Ops[i];
2086    Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2087    Entry.isSExt = isSigned;
2088    Entry.isZExt = !isSigned;
2089    Args.push_back(Entry);
2090  }
2091  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2092                                         TLI.getPointerTy());
2093
2094  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2095
2096  TargetLowering::CallLoweringInfo CLI(DAG);
2097  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2098    .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2099    .setSExtResult(isSigned).setZExtResult(!isSigned);
2100
2101  std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2102
2103  return CallInfo.first;
2104}
2105
2106// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2107// ExpandLibCall except that the first operand is the in-chain.
2108std::pair<SDValue, SDValue>
2109SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2110                                         SDNode *Node,
2111                                         bool isSigned) {
2112  SDValue InChain = Node->getOperand(0);
2113
2114  TargetLowering::ArgListTy Args;
2115  TargetLowering::ArgListEntry Entry;
2116  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2117    EVT ArgVT = Node->getOperand(i).getValueType();
2118    Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2119    Entry.Node = Node->getOperand(i);
2120    Entry.Ty = ArgTy;
2121    Entry.isSExt = isSigned;
2122    Entry.isZExt = !isSigned;
2123    Args.push_back(Entry);
2124  }
2125  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2126                                         TLI.getPointerTy());
2127
2128  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2129
2130  TargetLowering::CallLoweringInfo CLI(DAG);
2131  CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2132    .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2133    .setSExtResult(isSigned).setZExtResult(!isSigned);
2134
2135  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2136
2137  return CallInfo;
2138}
2139
2140SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2141                                              RTLIB::Libcall Call_F32,
2142                                              RTLIB::Libcall Call_F64,
2143                                              RTLIB::Libcall Call_F80,
2144                                              RTLIB::Libcall Call_F128,
2145                                              RTLIB::Libcall Call_PPCF128) {
2146  RTLIB::Libcall LC;
2147  switch (Node->getSimpleValueType(0).SimpleTy) {
2148  default: llvm_unreachable("Unexpected request for libcall!");
2149  case MVT::f32: LC = Call_F32; break;
2150  case MVT::f64: LC = Call_F64; break;
2151  case MVT::f80: LC = Call_F80; break;
2152  case MVT::f128: LC = Call_F128; break;
2153  case MVT::ppcf128: LC = Call_PPCF128; break;
2154  }
2155  return ExpandLibCall(LC, Node, false);
2156}
2157
2158SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2159                                               RTLIB::Libcall Call_I8,
2160                                               RTLIB::Libcall Call_I16,
2161                                               RTLIB::Libcall Call_I32,
2162                                               RTLIB::Libcall Call_I64,
2163                                               RTLIB::Libcall Call_I128) {
2164  RTLIB::Libcall LC;
2165  switch (Node->getSimpleValueType(0).SimpleTy) {
2166  default: llvm_unreachable("Unexpected request for libcall!");
2167  case MVT::i8:   LC = Call_I8; break;
2168  case MVT::i16:  LC = Call_I16; break;
2169  case MVT::i32:  LC = Call_I32; break;
2170  case MVT::i64:  LC = Call_I64; break;
2171  case MVT::i128: LC = Call_I128; break;
2172  }
2173  return ExpandLibCall(LC, Node, isSigned);
2174}
2175
2176/// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2177static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2178                                     const TargetLowering &TLI) {
2179  RTLIB::Libcall LC;
2180  switch (Node->getSimpleValueType(0).SimpleTy) {
2181  default: llvm_unreachable("Unexpected request for libcall!");
2182  case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
2183  case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2184  case MVT::i32:  LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2185  case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2186  case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2187  }
2188
2189  return TLI.getLibcallName(LC) != nullptr;
2190}
2191
2192/// useDivRem - Only issue divrem libcall if both quotient and remainder are
2193/// needed.
2194static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2195  // The other use might have been replaced with a divrem already.
2196  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2197  unsigned OtherOpcode = 0;
2198  if (isSigned)
2199    OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2200  else
2201    OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2202
2203  SDValue Op0 = Node->getOperand(0);
2204  SDValue Op1 = Node->getOperand(1);
2205  for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2206         UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2207    SDNode *User = *UI;
2208    if (User == Node)
2209      continue;
2210    if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2211        User->getOperand(0) == Op0 &&
2212        User->getOperand(1) == Op1)
2213      return true;
2214  }
2215  return false;
2216}
2217
2218/// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2219/// pairs.
2220void
2221SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2222                                          SmallVectorImpl<SDValue> &Results) {
2223  unsigned Opcode = Node->getOpcode();
2224  bool isSigned = Opcode == ISD::SDIVREM;
2225
2226  RTLIB::Libcall LC;
2227  switch (Node->getSimpleValueType(0).SimpleTy) {
2228  default: llvm_unreachable("Unexpected request for libcall!");
2229  case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
2230  case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2231  case MVT::i32:  LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2232  case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2233  case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2234  }
2235
2236  // The input chain to this libcall is the entry node of the function.
2237  // Legalizing the call will automatically add the previous call to the
2238  // dependence.
2239  SDValue InChain = DAG.getEntryNode();
2240
2241  EVT RetVT = Node->getValueType(0);
2242  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2243
2244  TargetLowering::ArgListTy Args;
2245  TargetLowering::ArgListEntry Entry;
2246  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2247    EVT ArgVT = Node->getOperand(i).getValueType();
2248    Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2249    Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2250    Entry.isSExt = isSigned;
2251    Entry.isZExt = !isSigned;
2252    Args.push_back(Entry);
2253  }
2254
2255  // Also pass the return address of the remainder.
2256  SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2257  Entry.Node = FIPtr;
2258  Entry.Ty = RetTy->getPointerTo();
2259  Entry.isSExt = isSigned;
2260  Entry.isZExt = !isSigned;
2261  Args.push_back(Entry);
2262
2263  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2264                                         TLI.getPointerTy());
2265
2266  SDLoc dl(Node);
2267  TargetLowering::CallLoweringInfo CLI(DAG);
2268  CLI.setDebugLoc(dl).setChain(InChain)
2269    .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2270    .setSExtResult(isSigned).setZExtResult(!isSigned);
2271
2272  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2273
2274  // Remainder is loaded back from the stack frame.
2275  SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2276                            MachinePointerInfo(), false, false, false, 0);
2277  Results.push_back(CallInfo.first);
2278  Results.push_back(Rem);
2279}
2280
2281/// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2282static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2283  RTLIB::Libcall LC;
2284  switch (Node->getSimpleValueType(0).SimpleTy) {
2285  default: llvm_unreachable("Unexpected request for libcall!");
2286  case MVT::f32:     LC = RTLIB::SINCOS_F32; break;
2287  case MVT::f64:     LC = RTLIB::SINCOS_F64; break;
2288  case MVT::f80:     LC = RTLIB::SINCOS_F80; break;
2289  case MVT::f128:    LC = RTLIB::SINCOS_F128; break;
2290  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2291  }
2292  return TLI.getLibcallName(LC) != nullptr;
2293}
2294
2295/// canCombineSinCosLibcall - Return true if sincos libcall is available and
2296/// can be used to combine sin and cos.
2297static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2298                                    const TargetMachine &TM) {
2299  if (!isSinCosLibcallAvailable(Node, TLI))
2300    return false;
2301  // GNU sin/cos functions set errno while sincos does not. Therefore
2302  // combining sin and cos is only safe if unsafe-fpmath is enabled.
2303  bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2304  if (isGNU && !TM.Options.UnsafeFPMath)
2305    return false;
2306  return true;
2307}
2308
2309/// useSinCos - Only issue sincos libcall if both sin and cos are
2310/// needed.
2311static bool useSinCos(SDNode *Node) {
2312  unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2313    ? ISD::FCOS : ISD::FSIN;
2314
2315  SDValue Op0 = Node->getOperand(0);
2316  for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2317       UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2318    SDNode *User = *UI;
2319    if (User == Node)
2320      continue;
2321    // The other user might have been turned into sincos already.
2322    if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2323      return true;
2324  }
2325  return false;
2326}
2327
2328/// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2329/// pairs.
2330void
2331SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2332                                          SmallVectorImpl<SDValue> &Results) {
2333  RTLIB::Libcall LC;
2334  switch (Node->getSimpleValueType(0).SimpleTy) {
2335  default: llvm_unreachable("Unexpected request for libcall!");
2336  case MVT::f32:     LC = RTLIB::SINCOS_F32; break;
2337  case MVT::f64:     LC = RTLIB::SINCOS_F64; break;
2338  case MVT::f80:     LC = RTLIB::SINCOS_F80; break;
2339  case MVT::f128:    LC = RTLIB::SINCOS_F128; break;
2340  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2341  }
2342
2343  // The input chain to this libcall is the entry node of the function.
2344  // Legalizing the call will automatically add the previous call to the
2345  // dependence.
2346  SDValue InChain = DAG.getEntryNode();
2347
2348  EVT RetVT = Node->getValueType(0);
2349  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2350
2351  TargetLowering::ArgListTy Args;
2352  TargetLowering::ArgListEntry Entry;
2353
2354  // Pass the argument.
2355  Entry.Node = Node->getOperand(0);
2356  Entry.Ty = RetTy;
2357  Entry.isSExt = false;
2358  Entry.isZExt = false;
2359  Args.push_back(Entry);
2360
2361  // Pass the return address of sin.
2362  SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2363  Entry.Node = SinPtr;
2364  Entry.Ty = RetTy->getPointerTo();
2365  Entry.isSExt = false;
2366  Entry.isZExt = false;
2367  Args.push_back(Entry);
2368
2369  // Also pass the return address of the cos.
2370  SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2371  Entry.Node = CosPtr;
2372  Entry.Ty = RetTy->getPointerTo();
2373  Entry.isSExt = false;
2374  Entry.isZExt = false;
2375  Args.push_back(Entry);
2376
2377  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2378                                         TLI.getPointerTy());
2379
2380  SDLoc dl(Node);
2381  TargetLowering::CallLoweringInfo CLI(DAG);
2382  CLI.setDebugLoc(dl).setChain(InChain)
2383    .setCallee(TLI.getLibcallCallingConv(LC),
2384               Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2385
2386  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2387
2388  Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2389                                MachinePointerInfo(), false, false, false, 0));
2390  Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2391                                MachinePointerInfo(), false, false, false, 0));
2392}
2393
2394/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2395/// INT_TO_FP operation of the specified operand when the target requests that
2396/// we expand it.  At this point, we know that the result and operand types are
2397/// legal for the target.
2398SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2399                                                   SDValue Op0,
2400                                                   EVT DestVT,
2401                                                   SDLoc dl) {
2402  if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2403    // simple 32-bit [signed|unsigned] integer to float/double expansion
2404
2405    // Get the stack frame index of a 8 byte buffer.
2406    SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2407
2408    // word offset constant for Hi/Lo address computation
2409    SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2410    // set up Hi and Lo (into buffer) address based on endian
2411    SDValue Hi = StackSlot;
2412    SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2413                             StackSlot, WordOff);
2414    if (TLI.isLittleEndian())
2415      std::swap(Hi, Lo);
2416
2417    // if signed map to unsigned space
2418    SDValue Op0Mapped;
2419    if (isSigned) {
2420      // constant used to invert sign bit (signed to unsigned mapping)
2421      SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2422      Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2423    } else {
2424      Op0Mapped = Op0;
2425    }
2426    // store the lo of the constructed double - based on integer input
2427    SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2428                                  Op0Mapped, Lo, MachinePointerInfo(),
2429                                  false, false, 0);
2430    // initial hi portion of constructed double
2431    SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2432    // store the hi of the constructed double - biased exponent
2433    SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2434                                  MachinePointerInfo(),
2435                                  false, false, 0);
2436    // load the constructed double
2437    SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2438                               MachinePointerInfo(), false, false, false, 0);
2439    // FP constant to bias correct the final result
2440    SDValue Bias = DAG.getConstantFP(isSigned ?
2441                                     BitsToDouble(0x4330000080000000ULL) :
2442                                     BitsToDouble(0x4330000000000000ULL),
2443                                     MVT::f64);
2444    // subtract the bias
2445    SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2446    // final result
2447    SDValue Result;
2448    // handle final rounding
2449    if (DestVT == MVT::f64) {
2450      // do nothing
2451      Result = Sub;
2452    } else if (DestVT.bitsLT(MVT::f64)) {
2453      Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2454                           DAG.getIntPtrConstant(0));
2455    } else if (DestVT.bitsGT(MVT::f64)) {
2456      Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2457    }
2458    return Result;
2459  }
2460  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2461  // Code below here assumes !isSigned without checking again.
2462
2463  // Implementation of unsigned i64 to f64 following the algorithm in
2464  // __floatundidf in compiler_rt. This implementation has the advantage
2465  // of performing rounding correctly, both in the default rounding mode
2466  // and in all alternate rounding modes.
2467  // TODO: Generalize this for use with other types.
2468  if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2469    SDValue TwoP52 =
2470      DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2471    SDValue TwoP84PlusTwoP52 =
2472      DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2473    SDValue TwoP84 =
2474      DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2475
2476    SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2477    SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2478                             DAG.getConstant(32, MVT::i64));
2479    SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2480    SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2481    SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2482    SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2483    SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2484                                TwoP84PlusTwoP52);
2485    return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2486  }
2487
2488  // Implementation of unsigned i64 to f32.
2489  // TODO: Generalize this for use with other types.
2490  if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2491    // For unsigned conversions, convert them to signed conversions using the
2492    // algorithm from the x86_64 __floatundidf in compiler_rt.
2493    if (!isSigned) {
2494      SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2495
2496      SDValue ShiftConst =
2497          DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2498      SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2499      SDValue AndConst = DAG.getConstant(1, MVT::i64);
2500      SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2501      SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2502
2503      SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2504      SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2505
2506      // TODO: This really should be implemented using a branch rather than a
2507      // select.  We happen to get lucky and machinesink does the right
2508      // thing most of the time.  This would be a good candidate for a
2509      //pseudo-op, or, even better, for whole-function isel.
2510      SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2511        Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2512      return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2513    }
2514
2515    // Otherwise, implement the fully general conversion.
2516
2517    SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2518         DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2519    SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2520         DAG.getConstant(UINT64_C(0x800), MVT::i64));
2521    SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2522         DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2523    SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2524                   And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2525    SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2526    SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2527                   Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2528                   ISD::SETUGE);
2529    SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2530    EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2531
2532    SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2533                             DAG.getConstant(32, SHVT));
2534    SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2535    SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2536    SDValue TwoP32 =
2537      DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2538    SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2539    SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2540    SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2541    SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2542    return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2543                       DAG.getIntPtrConstant(0));
2544  }
2545
2546  SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2547
2548  SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2549                                 Op0, DAG.getConstant(0, Op0.getValueType()),
2550                                 ISD::SETLT);
2551  SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2552  SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2553                                    SignSet, Four, Zero);
2554
2555  // If the sign bit of the integer is set, the large number will be treated
2556  // as a negative number.  To counteract this, the dynamic code adds an
2557  // offset depending on the data type.
2558  uint64_t FF;
2559  switch (Op0.getSimpleValueType().SimpleTy) {
2560  default: llvm_unreachable("Unsupported integer type!");
2561  case MVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
2562  case MVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
2563  case MVT::i32: FF = 0x4F800000ULL; break;  // 2^32 (as a float)
2564  case MVT::i64: FF = 0x5F800000ULL; break;  // 2^64 (as a float)
2565  }
2566  if (TLI.isLittleEndian()) FF <<= 32;
2567  Constant *FudgeFactor = ConstantInt::get(
2568                                       Type::getInt64Ty(*DAG.getContext()), FF);
2569
2570  SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2571  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2572  CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2573  Alignment = std::min(Alignment, 4u);
2574  SDValue FudgeInReg;
2575  if (DestVT == MVT::f32)
2576    FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2577                             MachinePointerInfo::getConstantPool(),
2578                             false, false, false, Alignment);
2579  else {
2580    SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2581                                  DAG.getEntryNode(), CPIdx,
2582                                  MachinePointerInfo::getConstantPool(),
2583                                  MVT::f32, false, false, Alignment);
2584    HandleSDNode Handle(Load);
2585    LegalizeOp(Load.getNode());
2586    FudgeInReg = Handle.getValue();
2587  }
2588
2589  return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2590}
2591
2592/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2593/// *INT_TO_FP operation of the specified operand when the target requests that
2594/// we promote it.  At this point, we know that the result and operand types are
2595/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2596/// operation that takes a larger input.
2597SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2598                                                    EVT DestVT,
2599                                                    bool isSigned,
2600                                                    SDLoc dl) {
2601  // First step, figure out the appropriate *INT_TO_FP operation to use.
2602  EVT NewInTy = LegalOp.getValueType();
2603
2604  unsigned OpToUse = 0;
2605
2606  // Scan for the appropriate larger type to use.
2607  while (1) {
2608    NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2609    assert(NewInTy.isInteger() && "Ran out of possibilities!");
2610
2611    // If the target supports SINT_TO_FP of this type, use it.
2612    if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2613      OpToUse = ISD::SINT_TO_FP;
2614      break;
2615    }
2616    if (isSigned) continue;
2617
2618    // If the target supports UINT_TO_FP of this type, use it.
2619    if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2620      OpToUse = ISD::UINT_TO_FP;
2621      break;
2622    }
2623
2624    // Otherwise, try a larger type.
2625  }
2626
2627  // Okay, we found the operation and type to use.  Zero extend our input to the
2628  // desired type then run the operation on it.
2629  return DAG.getNode(OpToUse, dl, DestVT,
2630                     DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2631                                 dl, NewInTy, LegalOp));
2632}
2633
2634/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2635/// FP_TO_*INT operation of the specified operand when the target requests that
2636/// we promote it.  At this point, we know that the result and operand types are
2637/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2638/// operation that returns a larger result.
2639SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2640                                                    EVT DestVT,
2641                                                    bool isSigned,
2642                                                    SDLoc dl) {
2643  // First step, figure out the appropriate FP_TO*INT operation to use.
2644  EVT NewOutTy = DestVT;
2645
2646  unsigned OpToUse = 0;
2647
2648  // Scan for the appropriate larger type to use.
2649  while (1) {
2650    NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2651    assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2652
2653    // A larger signed type can hold all unsigned values of the requested type,
2654    // so using FP_TO_SINT is valid
2655    if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2656      OpToUse = ISD::FP_TO_SINT;
2657      break;
2658    }
2659
2660    // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2661    if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2662      OpToUse = ISD::FP_TO_UINT;
2663      break;
2664    }
2665
2666    // Otherwise, try a larger type.
2667  }
2668
2669
2670  // Okay, we found the operation and type to use.
2671  SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2672
2673  // Truncate the result of the extended FP_TO_*INT operation to the desired
2674  // size.
2675  return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2676}
2677
2678/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2679///
2680SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2681  EVT VT = Op.getValueType();
2682  EVT SHVT = TLI.getShiftAmountTy(VT);
2683  SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2684  switch (VT.getSimpleVT().SimpleTy) {
2685  default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2686  case MVT::i16:
2687    Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2688    Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2689    return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2690  case MVT::i32:
2691    Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2692    Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2693    Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2694    Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2695    Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2696    Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2697    Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2698    Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2699    return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2700  case MVT::i64:
2701    Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2702    Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2703    Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2704    Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2705    Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2706    Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2707    Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2708    Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2709    Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2710    Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2711    Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2712    Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2713    Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2714    Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2715    Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2716    Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2717    Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2718    Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2719    Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2720    Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2721    return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2722  }
2723}
2724
2725/// ExpandBitCount - Expand the specified bitcount instruction into operations.
2726///
2727SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2728                                             SDLoc dl) {
2729  switch (Opc) {
2730  default: llvm_unreachable("Cannot expand this yet!");
2731  case ISD::CTPOP: {
2732    EVT VT = Op.getValueType();
2733    EVT ShVT = TLI.getShiftAmountTy(VT);
2734    unsigned Len = VT.getSizeInBits();
2735
2736    assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2737           "CTPOP not implemented for this type.");
2738
2739    // This is the "best" algorithm from
2740    // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2741
2742    SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2743    SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2744    SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2745    SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2746
2747    // v = v - ((v >> 1) & 0x55555555...)
2748    Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2749                     DAG.getNode(ISD::AND, dl, VT,
2750                                 DAG.getNode(ISD::SRL, dl, VT, Op,
2751                                             DAG.getConstant(1, ShVT)),
2752                                 Mask55));
2753    // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2754    Op = DAG.getNode(ISD::ADD, dl, VT,
2755                     DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2756                     DAG.getNode(ISD::AND, dl, VT,
2757                                 DAG.getNode(ISD::SRL, dl, VT, Op,
2758                                             DAG.getConstant(2, ShVT)),
2759                                 Mask33));
2760    // v = (v + (v >> 4)) & 0x0F0F0F0F...
2761    Op = DAG.getNode(ISD::AND, dl, VT,
2762                     DAG.getNode(ISD::ADD, dl, VT, Op,
2763                                 DAG.getNode(ISD::SRL, dl, VT, Op,
2764                                             DAG.getConstant(4, ShVT))),
2765                     Mask0F);
2766    // v = (v * 0x01010101...) >> (Len - 8)
2767    Op = DAG.getNode(ISD::SRL, dl, VT,
2768                     DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2769                     DAG.getConstant(Len - 8, ShVT));
2770
2771    return Op;
2772  }
2773  case ISD::CTLZ_ZERO_UNDEF:
2774    // This trivially expands to CTLZ.
2775    return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2776  case ISD::CTLZ: {
2777    // for now, we do this:
2778    // x = x | (x >> 1);
2779    // x = x | (x >> 2);
2780    // ...
2781    // x = x | (x >>16);
2782    // x = x | (x >>32); // for 64-bit input
2783    // return popcount(~x);
2784    //
2785    // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2786    EVT VT = Op.getValueType();
2787    EVT ShVT = TLI.getShiftAmountTy(VT);
2788    unsigned len = VT.getSizeInBits();
2789    for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2790      SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2791      Op = DAG.getNode(ISD::OR, dl, VT, Op,
2792                       DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2793    }
2794    Op = DAG.getNOT(dl, Op, VT);
2795    return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2796  }
2797  case ISD::CTTZ_ZERO_UNDEF:
2798    // This trivially expands to CTTZ.
2799    return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2800  case ISD::CTTZ: {
2801    // for now, we use: { return popcount(~x & (x - 1)); }
2802    // unless the target has ctlz but not ctpop, in which case we use:
2803    // { return 32 - nlz(~x & (x-1)); }
2804    // see also http://www.hackersdelight.org/HDcode/ntz.cc
2805    EVT VT = Op.getValueType();
2806    SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2807                               DAG.getNOT(dl, Op, VT),
2808                               DAG.getNode(ISD::SUB, dl, VT, Op,
2809                                           DAG.getConstant(1, VT)));
2810    // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2811    if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2812        TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2813      return DAG.getNode(ISD::SUB, dl, VT,
2814                         DAG.getConstant(VT.getSizeInBits(), VT),
2815                         DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2816    return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2817  }
2818  }
2819}
2820
2821std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2822  unsigned Opc = Node->getOpcode();
2823  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2824  RTLIB::Libcall LC;
2825
2826  switch (Opc) {
2827  default:
2828    llvm_unreachable("Unhandled atomic intrinsic Expand!");
2829  case ISD::ATOMIC_SWAP:
2830    switch (VT.SimpleTy) {
2831    default: llvm_unreachable("Unexpected value type for atomic!");
2832    case MVT::i8:  LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2833    case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2834    case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2835    case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2836    case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2837    }
2838    break;
2839  case ISD::ATOMIC_CMP_SWAP:
2840    switch (VT.SimpleTy) {
2841    default: llvm_unreachable("Unexpected value type for atomic!");
2842    case MVT::i8:  LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2843    case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2844    case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2845    case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2846    case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2847    }
2848    break;
2849  case ISD::ATOMIC_LOAD_ADD:
2850    switch (VT.SimpleTy) {
2851    default: llvm_unreachable("Unexpected value type for atomic!");
2852    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2853    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2854    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2855    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2856    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2857    }
2858    break;
2859  case ISD::ATOMIC_LOAD_SUB:
2860    switch (VT.SimpleTy) {
2861    default: llvm_unreachable("Unexpected value type for atomic!");
2862    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2863    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2864    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2865    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2866    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2867    }
2868    break;
2869  case ISD::ATOMIC_LOAD_AND:
2870    switch (VT.SimpleTy) {
2871    default: llvm_unreachable("Unexpected value type for atomic!");
2872    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2873    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2874    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2875    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2876    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2877    }
2878    break;
2879  case ISD::ATOMIC_LOAD_OR:
2880    switch (VT.SimpleTy) {
2881    default: llvm_unreachable("Unexpected value type for atomic!");
2882    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2883    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2884    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2885    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2886    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2887    }
2888    break;
2889  case ISD::ATOMIC_LOAD_XOR:
2890    switch (VT.SimpleTy) {
2891    default: llvm_unreachable("Unexpected value type for atomic!");
2892    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2893    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2894    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2895    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2896    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2897    }
2898    break;
2899  case ISD::ATOMIC_LOAD_NAND:
2900    switch (VT.SimpleTy) {
2901    default: llvm_unreachable("Unexpected value type for atomic!");
2902    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2903    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2904    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2905    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2906    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2907    }
2908    break;
2909  case ISD::ATOMIC_LOAD_MAX:
2910    switch (VT.SimpleTy) {
2911    default: llvm_unreachable("Unexpected value type for atomic!");
2912    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2913    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2914    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2915    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2916    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2917    }
2918    break;
2919  case ISD::ATOMIC_LOAD_UMAX:
2920    switch (VT.SimpleTy) {
2921    default: llvm_unreachable("Unexpected value type for atomic!");
2922    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2923    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2924    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2925    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2926    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2927    }
2928    break;
2929  case ISD::ATOMIC_LOAD_MIN:
2930    switch (VT.SimpleTy) {
2931    default: llvm_unreachable("Unexpected value type for atomic!");
2932    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2933    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2934    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2935    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2936    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2937    }
2938    break;
2939  case ISD::ATOMIC_LOAD_UMIN:
2940    switch (VT.SimpleTy) {
2941    default: llvm_unreachable("Unexpected value type for atomic!");
2942    case MVT::i8:  LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2943    case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2944    case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2945    case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2946    case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2947    }
2948    break;
2949  }
2950
2951  return ExpandChainLibCall(LC, Node, false);
2952}
2953
2954void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2955  SmallVector<SDValue, 8> Results;
2956  SDLoc dl(Node);
2957  SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2958  bool NeedInvert;
2959  switch (Node->getOpcode()) {
2960  case ISD::CTPOP:
2961  case ISD::CTLZ:
2962  case ISD::CTLZ_ZERO_UNDEF:
2963  case ISD::CTTZ:
2964  case ISD::CTTZ_ZERO_UNDEF:
2965    Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2966    Results.push_back(Tmp1);
2967    break;
2968  case ISD::BSWAP:
2969    Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2970    break;
2971  case ISD::FRAMEADDR:
2972  case ISD::RETURNADDR:
2973  case ISD::FRAME_TO_ARGS_OFFSET:
2974    Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2975    break;
2976  case ISD::FLT_ROUNDS_:
2977    Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2978    break;
2979  case ISD::EH_RETURN:
2980  case ISD::EH_LABEL:
2981  case ISD::PREFETCH:
2982  case ISD::VAEND:
2983  case ISD::EH_SJLJ_LONGJMP:
2984    // If the target didn't expand these, there's nothing to do, so just
2985    // preserve the chain and be done.
2986    Results.push_back(Node->getOperand(0));
2987    break;
2988  case ISD::EH_SJLJ_SETJMP:
2989    // If the target didn't expand this, just return 'zero' and preserve the
2990    // chain.
2991    Results.push_back(DAG.getConstant(0, MVT::i32));
2992    Results.push_back(Node->getOperand(0));
2993    break;
2994  case ISD::ATOMIC_FENCE: {
2995    // If the target didn't lower this, lower it to '__sync_synchronize()' call
2996    // FIXME: handle "fence singlethread" more efficiently.
2997    TargetLowering::ArgListTy Args;
2998
2999    TargetLowering::CallLoweringInfo CLI(DAG);
3000    CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
3001      .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3002                 DAG.getExternalSymbol("__sync_synchronize",
3003                 TLI.getPointerTy()), std::move(Args), 0);
3004
3005    std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3006
3007    Results.push_back(CallResult.second);
3008    break;
3009  }
3010  case ISD::ATOMIC_LOAD: {
3011    // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3012    SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
3013    SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3014    SDValue Swap = DAG.getAtomicCmpSwap(
3015        ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3016        Node->getOperand(0), Node->getOperand(1), Zero, Zero,
3017        cast<AtomicSDNode>(Node)->getMemOperand(),
3018        cast<AtomicSDNode>(Node)->getOrdering(),
3019        cast<AtomicSDNode>(Node)->getOrdering(),
3020        cast<AtomicSDNode>(Node)->getSynchScope());
3021    Results.push_back(Swap.getValue(0));
3022    Results.push_back(Swap.getValue(1));
3023    break;
3024  }
3025  case ISD::ATOMIC_STORE: {
3026    // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3027    SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3028                                 cast<AtomicSDNode>(Node)->getMemoryVT(),
3029                                 Node->getOperand(0),
3030                                 Node->getOperand(1), Node->getOperand(2),
3031                                 cast<AtomicSDNode>(Node)->getMemOperand(),
3032                                 cast<AtomicSDNode>(Node)->getOrdering(),
3033                                 cast<AtomicSDNode>(Node)->getSynchScope());
3034    Results.push_back(Swap.getValue(1));
3035    break;
3036  }
3037  // By default, atomic intrinsics are marked Legal and lowered. Targets
3038  // which don't support them directly, however, may want libcalls, in which
3039  // case they mark them Expand, and we get here.
3040  case ISD::ATOMIC_SWAP:
3041  case ISD::ATOMIC_LOAD_ADD:
3042  case ISD::ATOMIC_LOAD_SUB:
3043  case ISD::ATOMIC_LOAD_AND:
3044  case ISD::ATOMIC_LOAD_OR:
3045  case ISD::ATOMIC_LOAD_XOR:
3046  case ISD::ATOMIC_LOAD_NAND:
3047  case ISD::ATOMIC_LOAD_MIN:
3048  case ISD::ATOMIC_LOAD_MAX:
3049  case ISD::ATOMIC_LOAD_UMIN:
3050  case ISD::ATOMIC_LOAD_UMAX:
3051  case ISD::ATOMIC_CMP_SWAP: {
3052    std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3053    Results.push_back(Tmp.first);
3054    Results.push_back(Tmp.second);
3055    break;
3056  }
3057  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3058    // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3059    // splits out the success value as a comparison. Expanding the resulting
3060    // ATOMIC_CMP_SWAP will produce a libcall.
3061    SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3062    SDValue Res = DAG.getAtomicCmpSwap(
3063        ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3064        Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
3065        Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
3066        cast<AtomicSDNode>(Node)->getSuccessOrdering(),
3067        cast<AtomicSDNode>(Node)->getFailureOrdering(),
3068        cast<AtomicSDNode>(Node)->getSynchScope());
3069
3070    SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
3071                                   Res, Node->getOperand(2), ISD::SETEQ);
3072
3073    Results.push_back(Res.getValue(0));
3074    Results.push_back(Success);
3075    Results.push_back(Res.getValue(1));
3076    break;
3077  }
3078  case ISD::DYNAMIC_STACKALLOC:
3079    ExpandDYNAMIC_STACKALLOC(Node, Results);
3080    break;
3081  case ISD::MERGE_VALUES:
3082    for (unsigned i = 0; i < Node->getNumValues(); i++)
3083      Results.push_back(Node->getOperand(i));
3084    break;
3085  case ISD::UNDEF: {
3086    EVT VT = Node->getValueType(0);
3087    if (VT.isInteger())
3088      Results.push_back(DAG.getConstant(0, VT));
3089    else {
3090      assert(VT.isFloatingPoint() && "Unknown value type!");
3091      Results.push_back(DAG.getConstantFP(0, VT));
3092    }
3093    break;
3094  }
3095  case ISD::TRAP: {
3096    // If this operation is not supported, lower it to 'abort()' call
3097    TargetLowering::ArgListTy Args;
3098    TargetLowering::CallLoweringInfo CLI(DAG);
3099    CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
3100      .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3101                 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3102                 std::move(Args), 0);
3103    std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3104
3105    Results.push_back(CallResult.second);
3106    break;
3107  }
3108  case ISD::FP_ROUND:
3109  case ISD::BITCAST:
3110    Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3111                            Node->getValueType(0), dl);
3112    Results.push_back(Tmp1);
3113    break;
3114  case ISD::FP_EXTEND:
3115    Tmp1 = EmitStackConvert(Node->getOperand(0),
3116                            Node->getOperand(0).getValueType(),
3117                            Node->getValueType(0), dl);
3118    Results.push_back(Tmp1);
3119    break;
3120  case ISD::SIGN_EXTEND_INREG: {
3121    // NOTE: we could fall back on load/store here too for targets without
3122    // SAR.  However, it is doubtful that any exist.
3123    EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3124    EVT VT = Node->getValueType(0);
3125    EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3126    if (VT.isVector())
3127      ShiftAmountTy = VT;
3128    unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3129                        ExtraVT.getScalarType().getSizeInBits();
3130    SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3131    Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3132                       Node->getOperand(0), ShiftCst);
3133    Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3134    Results.push_back(Tmp1);
3135    break;
3136  }
3137  case ISD::FP_ROUND_INREG: {
3138    // The only way we can lower this is to turn it into a TRUNCSTORE,
3139    // EXTLOAD pair, targeting a temporary location (a stack slot).
3140
3141    // NOTE: there is a choice here between constantly creating new stack
3142    // slots and always reusing the same one.  We currently always create
3143    // new ones, as reuse may inhibit scheduling.
3144    EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3145    Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3146                            Node->getValueType(0), dl);
3147    Results.push_back(Tmp1);
3148    break;
3149  }
3150  case ISD::SINT_TO_FP:
3151  case ISD::UINT_TO_FP:
3152    Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3153                                Node->getOperand(0), Node->getValueType(0), dl);
3154    Results.push_back(Tmp1);
3155    break;
3156  case ISD::FP_TO_SINT: {
3157    EVT VT = Node->getOperand(0).getValueType();
3158    EVT NVT = Node->getValueType(0);
3159
3160    // FIXME: Only f32 to i64 conversions are supported.
3161    if (VT != MVT::f32 || NVT != MVT::i64)
3162      break;
3163
3164    // Expand f32 -> i64 conversion
3165    // This algorithm comes from compiler-rt's implementation of fixsfdi:
3166    // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
3167    EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
3168                                  VT.getSizeInBits());
3169    SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
3170    SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
3171    SDValue Bias = DAG.getConstant(127, IntVT);
3172    SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
3173                                       IntVT);
3174    SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
3175    SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
3176
3177    SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
3178
3179    SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
3180        DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
3181        DAG.getZExtOrTrunc(ExponentLoBit, dl, TLI.getShiftAmountTy(IntVT)));
3182    SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
3183
3184    SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
3185        DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
3186        DAG.getZExtOrTrunc(SignLowBit, dl, TLI.getShiftAmountTy(IntVT)));
3187    Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
3188
3189    SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
3190        DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
3191        DAG.getConstant(0x00800000, IntVT));
3192
3193    R = DAG.getZExtOrTrunc(R, dl, NVT);
3194
3195
3196    R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
3197       DAG.getNode(ISD::SHL, dl, NVT, R,
3198                   DAG.getZExtOrTrunc(
3199                      DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
3200                      dl, TLI.getShiftAmountTy(IntVT))),
3201       DAG.getNode(ISD::SRL, dl, NVT, R,
3202                   DAG.getZExtOrTrunc(
3203                      DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3204                      dl, TLI.getShiftAmountTy(IntVT))),
3205       ISD::SETGT);
3206
3207    SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
3208        DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
3209        Sign);
3210
3211    Results.push_back(DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
3212        DAG.getConstant(0, NVT), Ret, ISD::SETLT));
3213    break;
3214  }
3215  case ISD::FP_TO_UINT: {
3216    SDValue True, False;
3217    EVT VT =  Node->getOperand(0).getValueType();
3218    EVT NVT = Node->getValueType(0);
3219    APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3220                APInt::getNullValue(VT.getSizeInBits()));
3221    APInt x = APInt::getSignBit(NVT.getSizeInBits());
3222    (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3223    Tmp1 = DAG.getConstantFP(apf, VT);
3224    Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3225                        Node->getOperand(0),
3226                        Tmp1, ISD::SETLT);
3227    True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3228    False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3229                        DAG.getNode(ISD::FSUB, dl, VT,
3230                                    Node->getOperand(0), Tmp1));
3231    False = DAG.getNode(ISD::XOR, dl, NVT, False,
3232                        DAG.getConstant(x, NVT));
3233    Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3234    Results.push_back(Tmp1);
3235    break;
3236  }
3237  case ISD::VAARG: {
3238    const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3239    EVT VT = Node->getValueType(0);
3240    Tmp1 = Node->getOperand(0);
3241    Tmp2 = Node->getOperand(1);
3242    unsigned Align = Node->getConstantOperandVal(3);
3243
3244    SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3245                                     MachinePointerInfo(V),
3246                                     false, false, false, 0);
3247    SDValue VAList = VAListLoad;
3248
3249    if (Align > TLI.getMinStackArgumentAlignment()) {
3250      assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3251
3252      VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3253                           DAG.getConstant(Align - 1,
3254                                           VAList.getValueType()));
3255
3256      VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3257                           DAG.getConstant(-(int64_t)Align,
3258                                           VAList.getValueType()));
3259    }
3260
3261    // Increment the pointer, VAList, to the next vaarg
3262    Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3263                       DAG.getConstant(TLI.getDataLayout()->
3264                          getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3265                                       VAList.getValueType()));
3266    // Store the incremented VAList to the legalized pointer
3267    Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3268                        MachinePointerInfo(V), false, false, 0);
3269    // Load the actual argument out of the pointer VAList
3270    Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3271                                  false, false, false, 0));
3272    Results.push_back(Results[0].getValue(1));
3273    break;
3274  }
3275  case ISD::VACOPY: {
3276    // This defaults to loading a pointer from the input and storing it to the
3277    // output, returning the chain.
3278    const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3279    const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3280    Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3281                       Node->getOperand(2), MachinePointerInfo(VS),
3282                       false, false, false, 0);
3283    Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3284                        MachinePointerInfo(VD), false, false, 0);
3285    Results.push_back(Tmp1);
3286    break;
3287  }
3288  case ISD::EXTRACT_VECTOR_ELT:
3289    if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3290      // This must be an access of the only element.  Return it.
3291      Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3292                         Node->getOperand(0));
3293    else
3294      Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3295    Results.push_back(Tmp1);
3296    break;
3297  case ISD::EXTRACT_SUBVECTOR:
3298    Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3299    break;
3300  case ISD::INSERT_SUBVECTOR:
3301    Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3302    break;
3303  case ISD::CONCAT_VECTORS: {
3304    Results.push_back(ExpandVectorBuildThroughStack(Node));
3305    break;
3306  }
3307  case ISD::SCALAR_TO_VECTOR:
3308    Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3309    break;
3310  case ISD::INSERT_VECTOR_ELT:
3311    Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3312                                              Node->getOperand(1),
3313                                              Node->getOperand(2), dl));
3314    break;
3315  case ISD::VECTOR_SHUFFLE: {
3316    SmallVector<int, 32> NewMask;
3317    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3318
3319    EVT VT = Node->getValueType(0);
3320    EVT EltVT = VT.getVectorElementType();
3321    SDValue Op0 = Node->getOperand(0);
3322    SDValue Op1 = Node->getOperand(1);
3323    if (!TLI.isTypeLegal(EltVT)) {
3324
3325      EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3326
3327      // BUILD_VECTOR operands are allowed to be wider than the element type.
3328      // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3329      // it.
3330      if (NewEltVT.bitsLT(EltVT)) {
3331
3332        // Convert shuffle node.
3333        // If original node was v4i64 and the new EltVT is i32,
3334        // cast operands to v8i32 and re-build the mask.
3335
3336        // Calculate new VT, the size of the new VT should be equal to original.
3337        EVT NewVT =
3338            EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3339                             VT.getSizeInBits() / NewEltVT.getSizeInBits());
3340        assert(NewVT.bitsEq(VT));
3341
3342        // cast operands to new VT
3343        Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3344        Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3345
3346        // Convert the shuffle mask
3347        unsigned int factor =
3348                         NewVT.getVectorNumElements()/VT.getVectorNumElements();
3349
3350        // EltVT gets smaller
3351        assert(factor > 0);
3352
3353        for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3354          if (Mask[i] < 0) {
3355            for (unsigned fi = 0; fi < factor; ++fi)
3356              NewMask.push_back(Mask[i]);
3357          }
3358          else {
3359            for (unsigned fi = 0; fi < factor; ++fi)
3360              NewMask.push_back(Mask[i]*factor+fi);
3361          }
3362        }
3363        Mask = NewMask;
3364        VT = NewVT;
3365      }
3366      EltVT = NewEltVT;
3367    }
3368    unsigned NumElems = VT.getVectorNumElements();
3369    SmallVector<SDValue, 16> Ops;
3370    for (unsigned i = 0; i != NumElems; ++i) {
3371      if (Mask[i] < 0) {
3372        Ops.push_back(DAG.getUNDEF(EltVT));
3373        continue;
3374      }
3375      unsigned Idx = Mask[i];
3376      if (Idx < NumElems)
3377        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3378                                  Op0,
3379                                  DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3380      else
3381        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3382                                  Op1,
3383                                  DAG.getConstant(Idx - NumElems,
3384                                                  TLI.getVectorIdxTy())));
3385    }
3386
3387    Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3388    // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3389    Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3390    Results.push_back(Tmp1);
3391    break;
3392  }
3393  case ISD::EXTRACT_ELEMENT: {
3394    EVT OpTy = Node->getOperand(0).getValueType();
3395    if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3396      // 1 -> Hi
3397      Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3398                         DAG.getConstant(OpTy.getSizeInBits()/2,
3399                    TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3400      Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3401    } else {
3402      // 0 -> Lo
3403      Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3404                         Node->getOperand(0));
3405    }
3406    Results.push_back(Tmp1);
3407    break;
3408  }
3409  case ISD::STACKSAVE:
3410    // Expand to CopyFromReg if the target set
3411    // StackPointerRegisterToSaveRestore.
3412    if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3413      Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3414                                           Node->getValueType(0)));
3415      Results.push_back(Results[0].getValue(1));
3416    } else {
3417      Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3418      Results.push_back(Node->getOperand(0));
3419    }
3420    break;
3421  case ISD::STACKRESTORE:
3422    // Expand to CopyToReg if the target set
3423    // StackPointerRegisterToSaveRestore.
3424    if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3425      Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3426                                         Node->getOperand(1)));
3427    } else {
3428      Results.push_back(Node->getOperand(0));
3429    }
3430    break;
3431  case ISD::FCOPYSIGN:
3432    Results.push_back(ExpandFCOPYSIGN(Node));
3433    break;
3434  case ISD::FNEG:
3435    // Expand Y = FNEG(X) ->  Y = SUB -0.0, X
3436    Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3437    Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3438                       Node->getOperand(0));
3439    Results.push_back(Tmp1);
3440    break;
3441  case ISD::FABS: {
3442    // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3443    EVT VT = Node->getValueType(0);
3444    Tmp1 = Node->getOperand(0);
3445    Tmp2 = DAG.getConstantFP(0.0, VT);
3446    Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3447                        Tmp1, Tmp2, ISD::SETUGT);
3448    Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3449    Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3450    Results.push_back(Tmp1);
3451    break;
3452  }
3453  case ISD::FSQRT:
3454    Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3455                                      RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3456                                      RTLIB::SQRT_PPCF128));
3457    break;
3458  case ISD::FSIN:
3459  case ISD::FCOS: {
3460    EVT VT = Node->getValueType(0);
3461    bool isSIN = Node->getOpcode() == ISD::FSIN;
3462    // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3463    // fcos which share the same operand and both are used.
3464    if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3465         canCombineSinCosLibcall(Node, TLI, TM))
3466        && useSinCos(Node)) {
3467      SDVTList VTs = DAG.getVTList(VT, VT);
3468      Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3469      if (!isSIN)
3470        Tmp1 = Tmp1.getValue(1);
3471      Results.push_back(Tmp1);
3472    } else if (isSIN) {
3473      Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3474                                        RTLIB::SIN_F80, RTLIB::SIN_F128,
3475                                        RTLIB::SIN_PPCF128));
3476    } else {
3477      Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3478                                        RTLIB::COS_F80, RTLIB::COS_F128,
3479                                        RTLIB::COS_PPCF128));
3480    }
3481    break;
3482  }
3483  case ISD::FSINCOS:
3484    // Expand into sincos libcall.
3485    ExpandSinCosLibCall(Node, Results);
3486    break;
3487  case ISD::FLOG:
3488    Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3489                                      RTLIB::LOG_F80, RTLIB::LOG_F128,
3490                                      RTLIB::LOG_PPCF128));
3491    break;
3492  case ISD::FLOG2:
3493    Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3494                                      RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3495                                      RTLIB::LOG2_PPCF128));
3496    break;
3497  case ISD::FLOG10:
3498    Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3499                                      RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3500                                      RTLIB::LOG10_PPCF128));
3501    break;
3502  case ISD::FEXP:
3503    Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3504                                      RTLIB::EXP_F80, RTLIB::EXP_F128,
3505                                      RTLIB::EXP_PPCF128));
3506    break;
3507  case ISD::FEXP2:
3508    Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3509                                      RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3510                                      RTLIB::EXP2_PPCF128));
3511    break;
3512  case ISD::FTRUNC:
3513    Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3514                                      RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3515                                      RTLIB::TRUNC_PPCF128));
3516    break;
3517  case ISD::FFLOOR:
3518    Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3519                                      RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3520                                      RTLIB::FLOOR_PPCF128));
3521    break;
3522  case ISD::FCEIL:
3523    Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3524                                      RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3525                                      RTLIB::CEIL_PPCF128));
3526    break;
3527  case ISD::FRINT:
3528    Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3529                                      RTLIB::RINT_F80, RTLIB::RINT_F128,
3530                                      RTLIB::RINT_PPCF128));
3531    break;
3532  case ISD::FNEARBYINT:
3533    Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3534                                      RTLIB::NEARBYINT_F64,
3535                                      RTLIB::NEARBYINT_F80,
3536                                      RTLIB::NEARBYINT_F128,
3537                                      RTLIB::NEARBYINT_PPCF128));
3538    break;
3539  case ISD::FROUND:
3540    Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3541                                      RTLIB::ROUND_F64,
3542                                      RTLIB::ROUND_F80,
3543                                      RTLIB::ROUND_F128,
3544                                      RTLIB::ROUND_PPCF128));
3545    break;
3546  case ISD::FPOWI:
3547    Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3548                                      RTLIB::POWI_F80, RTLIB::POWI_F128,
3549                                      RTLIB::POWI_PPCF128));
3550    break;
3551  case ISD::FPOW:
3552    Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3553                                      RTLIB::POW_F80, RTLIB::POW_F128,
3554                                      RTLIB::POW_PPCF128));
3555    break;
3556  case ISD::FDIV:
3557    Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3558                                      RTLIB::DIV_F80, RTLIB::DIV_F128,
3559                                      RTLIB::DIV_PPCF128));
3560    break;
3561  case ISD::FREM:
3562    Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3563                                      RTLIB::REM_F80, RTLIB::REM_F128,
3564                                      RTLIB::REM_PPCF128));
3565    break;
3566  case ISD::FMA:
3567    Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3568                                      RTLIB::FMA_F80, RTLIB::FMA_F128,
3569                                      RTLIB::FMA_PPCF128));
3570    break;
3571  case ISD::FP16_TO_FP32:
3572    Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3573    break;
3574  case ISD::FP32_TO_FP16:
3575    Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3576    break;
3577  case ISD::ConstantFP: {
3578    ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3579    // Check to see if this FP immediate is already legal.
3580    // If this is a legal constant, turn it into a TargetConstantFP node.
3581    if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3582      Results.push_back(ExpandConstantFP(CFP, true));
3583    break;
3584  }
3585  case ISD::FSUB: {
3586    EVT VT = Node->getValueType(0);
3587    assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3588           TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3589           "Don't know how to expand this FP subtraction!");
3590    Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3591    Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3592    Results.push_back(Tmp1);
3593    break;
3594  }
3595  case ISD::SUB: {
3596    EVT VT = Node->getValueType(0);
3597    assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3598           TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3599           "Don't know how to expand this subtraction!");
3600    Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3601               DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3602    Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3603    Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3604    break;
3605  }
3606  case ISD::UREM:
3607  case ISD::SREM: {
3608    EVT VT = Node->getValueType(0);
3609    bool isSigned = Node->getOpcode() == ISD::SREM;
3610    unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3611    unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3612    Tmp2 = Node->getOperand(0);
3613    Tmp3 = Node->getOperand(1);
3614    if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3615        (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3616         // If div is legal, it's better to do the normal expansion
3617         !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3618         useDivRem(Node, isSigned, false))) {
3619      SDVTList VTs = DAG.getVTList(VT, VT);
3620      Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3621    } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3622      // X % Y -> X-X/Y*Y
3623      Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3624      Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3625      Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3626    } else if (isSigned)
3627      Tmp1 = ExpandIntLibCall(Node, true,
3628                              RTLIB::SREM_I8,
3629                              RTLIB::SREM_I16, RTLIB::SREM_I32,
3630                              RTLIB::SREM_I64, RTLIB::SREM_I128);
3631    else
3632      Tmp1 = ExpandIntLibCall(Node, false,
3633                              RTLIB::UREM_I8,
3634                              RTLIB::UREM_I16, RTLIB::UREM_I32,
3635                              RTLIB::UREM_I64, RTLIB::UREM_I128);
3636    Results.push_back(Tmp1);
3637    break;
3638  }
3639  case ISD::UDIV:
3640  case ISD::SDIV: {
3641    bool isSigned = Node->getOpcode() == ISD::SDIV;
3642    unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3643    EVT VT = Node->getValueType(0);
3644    SDVTList VTs = DAG.getVTList(VT, VT);
3645    if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3646        (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3647         useDivRem(Node, isSigned, true)))
3648      Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3649                         Node->getOperand(1));
3650    else if (isSigned)
3651      Tmp1 = ExpandIntLibCall(Node, true,
3652                              RTLIB::SDIV_I8,
3653                              RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3654                              RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3655    else
3656      Tmp1 = ExpandIntLibCall(Node, false,
3657                              RTLIB::UDIV_I8,
3658                              RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3659                              RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3660    Results.push_back(Tmp1);
3661    break;
3662  }
3663  case ISD::MULHU:
3664  case ISD::MULHS: {
3665    unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3666                                                              ISD::SMUL_LOHI;
3667    EVT VT = Node->getValueType(0);
3668    SDVTList VTs = DAG.getVTList(VT, VT);
3669    assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3670           "If this wasn't legal, it shouldn't have been created!");
3671    Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3672                       Node->getOperand(1));
3673    Results.push_back(Tmp1.getValue(1));
3674    break;
3675  }
3676  case ISD::SDIVREM:
3677  case ISD::UDIVREM:
3678    // Expand into divrem libcall
3679    ExpandDivRemLibCall(Node, Results);
3680    break;
3681  case ISD::MUL: {
3682    EVT VT = Node->getValueType(0);
3683    SDVTList VTs = DAG.getVTList(VT, VT);
3684    // See if multiply or divide can be lowered using two-result operations.
3685    // We just need the low half of the multiply; try both the signed
3686    // and unsigned forms. If the target supports both SMUL_LOHI and
3687    // UMUL_LOHI, form a preference by checking which forms of plain
3688    // MULH it supports.
3689    bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3690    bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3691    bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3692    bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3693    unsigned OpToUse = 0;
3694    if (HasSMUL_LOHI && !HasMULHS) {
3695      OpToUse = ISD::SMUL_LOHI;
3696    } else if (HasUMUL_LOHI && !HasMULHU) {
3697      OpToUse = ISD::UMUL_LOHI;
3698    } else if (HasSMUL_LOHI) {
3699      OpToUse = ISD::SMUL_LOHI;
3700    } else if (HasUMUL_LOHI) {
3701      OpToUse = ISD::UMUL_LOHI;
3702    }
3703    if (OpToUse) {
3704      Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3705                                    Node->getOperand(1)));
3706      break;
3707    }
3708
3709    SDValue Lo, Hi;
3710    EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3711    if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3712        TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3713        TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3714        TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3715        TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3716      Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3717      Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3718      SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(),
3719                                      TLI.getShiftAmountTy(HalfType));
3720      Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3721      Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3722      break;
3723    }
3724
3725    Tmp1 = ExpandIntLibCall(Node, false,
3726                            RTLIB::MUL_I8,
3727                            RTLIB::MUL_I16, RTLIB::MUL_I32,
3728                            RTLIB::MUL_I64, RTLIB::MUL_I128);
3729    Results.push_back(Tmp1);
3730    break;
3731  }
3732  case ISD::SADDO:
3733  case ISD::SSUBO: {
3734    SDValue LHS = Node->getOperand(0);
3735    SDValue RHS = Node->getOperand(1);
3736    SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3737                              ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3738                              LHS, RHS);
3739    Results.push_back(Sum);
3740    EVT ResultType = Node->getValueType(1);
3741    EVT OType = getSetCCResultType(Node->getValueType(0));
3742
3743    SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3744
3745    //   LHSSign -> LHS >= 0
3746    //   RHSSign -> RHS >= 0
3747    //   SumSign -> Sum >= 0
3748    //
3749    //   Add:
3750    //   Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3751    //   Sub:
3752    //   Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3753    //
3754    SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3755    SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3756    SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3757                                      Node->getOpcode() == ISD::SADDO ?
3758                                      ISD::SETEQ : ISD::SETNE);
3759
3760    SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3761    SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3762
3763    SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3764    Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3765    break;
3766  }
3767  case ISD::UADDO:
3768  case ISD::USUBO: {
3769    SDValue LHS = Node->getOperand(0);
3770    SDValue RHS = Node->getOperand(1);
3771    SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3772                              ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3773                              LHS, RHS);
3774    Results.push_back(Sum);
3775
3776    EVT ResultType = Node->getValueType(1);
3777    EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3778    ISD::CondCode CC
3779      = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3780    SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3781
3782    Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3783    break;
3784  }
3785  case ISD::UMULO:
3786  case ISD::SMULO: {
3787    EVT VT = Node->getValueType(0);
3788    EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3789    SDValue LHS = Node->getOperand(0);
3790    SDValue RHS = Node->getOperand(1);
3791    SDValue BottomHalf;
3792    SDValue TopHalf;
3793    static const unsigned Ops[2][3] =
3794        { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3795          { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3796    bool isSigned = Node->getOpcode() == ISD::SMULO;
3797    if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3798      BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3799      TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3800    } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3801      BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3802                               RHS);
3803      TopHalf = BottomHalf.getValue(1);
3804    } else if (TLI.isTypeLegal(WideVT)) {
3805      LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3806      RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3807      Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3808      BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3809                               DAG.getIntPtrConstant(0));
3810      TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3811                            DAG.getIntPtrConstant(1));
3812    } else {
3813      // We can fall back to a libcall with an illegal type for the MUL if we
3814      // have a libcall big enough.
3815      // Also, we can fall back to a division in some cases, but that's a big
3816      // performance hit in the general case.
3817      RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3818      if (WideVT == MVT::i16)
3819        LC = RTLIB::MUL_I16;
3820      else if (WideVT == MVT::i32)
3821        LC = RTLIB::MUL_I32;
3822      else if (WideVT == MVT::i64)
3823        LC = RTLIB::MUL_I64;
3824      else if (WideVT == MVT::i128)
3825        LC = RTLIB::MUL_I128;
3826      assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3827
3828      // The high part is obtained by SRA'ing all but one of the bits of low
3829      // part.
3830      unsigned LoSize = VT.getSizeInBits();
3831      SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3832                                DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3833      SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3834                                DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3835
3836      // Here we're passing the 2 arguments explicitly as 4 arguments that are
3837      // pre-lowered to the correct types. This all depends upon WideVT not
3838      // being a legal type for the architecture and thus has to be split to
3839      // two arguments.
3840      SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3841      SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3842      BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3843                               DAG.getIntPtrConstant(0));
3844      TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3845                            DAG.getIntPtrConstant(1));
3846      // Ret is a node with an illegal type. Because such things are not
3847      // generally permitted during this phase of legalization, delete the
3848      // node. The above EXTRACT_ELEMENT nodes should have been folded.
3849      DAG.DeleteNode(Ret.getNode());
3850    }
3851
3852    if (isSigned) {
3853      Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3854                             TLI.getShiftAmountTy(BottomHalf.getValueType()));
3855      Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3856      TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3857                             ISD::SETNE);
3858    } else {
3859      TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3860                             DAG.getConstant(0, VT), ISD::SETNE);
3861    }
3862    Results.push_back(BottomHalf);
3863    Results.push_back(TopHalf);
3864    break;
3865  }
3866  case ISD::BUILD_PAIR: {
3867    EVT PairTy = Node->getValueType(0);
3868    Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3869    Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3870    Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3871                       DAG.getConstant(PairTy.getSizeInBits()/2,
3872                                       TLI.getShiftAmountTy(PairTy)));
3873    Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3874    break;
3875  }
3876  case ISD::SELECT:
3877    Tmp1 = Node->getOperand(0);
3878    Tmp2 = Node->getOperand(1);
3879    Tmp3 = Node->getOperand(2);
3880    if (Tmp1.getOpcode() == ISD::SETCC) {
3881      Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3882                             Tmp2, Tmp3,
3883                             cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3884    } else {
3885      Tmp1 = DAG.getSelectCC(dl, Tmp1,
3886                             DAG.getConstant(0, Tmp1.getValueType()),
3887                             Tmp2, Tmp3, ISD::SETNE);
3888    }
3889    Results.push_back(Tmp1);
3890    break;
3891  case ISD::BR_JT: {
3892    SDValue Chain = Node->getOperand(0);
3893    SDValue Table = Node->getOperand(1);
3894    SDValue Index = Node->getOperand(2);
3895
3896    EVT PTy = TLI.getPointerTy();
3897
3898    const DataLayout &TD = *TLI.getDataLayout();
3899    unsigned EntrySize =
3900      DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3901
3902    Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3903                       Index, DAG.getConstant(EntrySize, Index.getValueType()));
3904    SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3905                               Index, Table);
3906
3907    EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3908    SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3909                                MachinePointerInfo::getJumpTable(), MemVT,
3910                                false, false, 0);
3911    Addr = LD;
3912    if (TM.getRelocationModel() == Reloc::PIC_) {
3913      // For PIC, the sequence is:
3914      // BRIND(load(Jumptable + index) + RelocBase)
3915      // RelocBase can be JumpTable, GOT or some sort of global base.
3916      Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3917                          TLI.getPICJumpTableRelocBase(Table, DAG));
3918    }
3919    Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3920    Results.push_back(Tmp1);
3921    break;
3922  }
3923  case ISD::BRCOND:
3924    // Expand brcond's setcc into its constituent parts and create a BR_CC
3925    // Node.
3926    Tmp1 = Node->getOperand(0);
3927    Tmp2 = Node->getOperand(1);
3928    if (Tmp2.getOpcode() == ISD::SETCC) {
3929      Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3930                         Tmp1, Tmp2.getOperand(2),
3931                         Tmp2.getOperand(0), Tmp2.getOperand(1),
3932                         Node->getOperand(2));
3933    } else {
3934      // We test only the i1 bit.  Skip the AND if UNDEF.
3935      Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3936        DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3937                    DAG.getConstant(1, Tmp2.getValueType()));
3938      Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3939                         DAG.getCondCode(ISD::SETNE), Tmp3,
3940                         DAG.getConstant(0, Tmp3.getValueType()),
3941                         Node->getOperand(2));
3942    }
3943    Results.push_back(Tmp1);
3944    break;
3945  case ISD::SETCC: {
3946    Tmp1 = Node->getOperand(0);
3947    Tmp2 = Node->getOperand(1);
3948    Tmp3 = Node->getOperand(2);
3949    bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3950                                           Tmp3, NeedInvert, dl);
3951
3952    if (Legalized) {
3953      // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3954      // condition code, create a new SETCC node.
3955      if (Tmp3.getNode())
3956        Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3957                           Tmp1, Tmp2, Tmp3);
3958
3959      // If we expanded the SETCC by inverting the condition code, then wrap
3960      // the existing SETCC in a NOT to restore the intended condition.
3961      if (NeedInvert)
3962        Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3963
3964      Results.push_back(Tmp1);
3965      break;
3966    }
3967
3968    // Otherwise, SETCC for the given comparison type must be completely
3969    // illegal; expand it into a SELECT_CC.
3970    EVT VT = Node->getValueType(0);
3971    int TrueValue;
3972    switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3973    case TargetLowering::ZeroOrOneBooleanContent:
3974    case TargetLowering::UndefinedBooleanContent:
3975      TrueValue = 1;
3976      break;
3977    case TargetLowering::ZeroOrNegativeOneBooleanContent:
3978      TrueValue = -1;
3979      break;
3980    }
3981    Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3982                       DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3983                       Tmp3);
3984    Results.push_back(Tmp1);
3985    break;
3986  }
3987  case ISD::SELECT_CC: {
3988    Tmp1 = Node->getOperand(0);   // LHS
3989    Tmp2 = Node->getOperand(1);   // RHS
3990    Tmp3 = Node->getOperand(2);   // True
3991    Tmp4 = Node->getOperand(3);   // False
3992    EVT VT = Node->getValueType(0);
3993    SDValue CC = Node->getOperand(4);
3994    ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3995
3996    if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3997      // If the condition code is legal, then we need to expand this
3998      // node using SETCC and SELECT.
3999      EVT CmpVT = Tmp1.getValueType();
4000      assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
4001             "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
4002             "expanded.");
4003      EVT CCVT = TLI.getSetCCResultType(*DAG.getContext(), CmpVT);
4004      SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
4005      Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
4006      break;
4007    }
4008
4009    // SELECT_CC is legal, so the condition code must not be.
4010    bool Legalized = false;
4011    // Try to legalize by inverting the condition.  This is for targets that
4012    // might support an ordered version of a condition, but not the unordered
4013    // version (or vice versa).
4014    ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
4015                                               Tmp1.getValueType().isInteger());
4016    if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
4017      // Use the new condition code and swap true and false
4018      Legalized = true;
4019      Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
4020    } else {
4021      // If The inverse is not legal, then try to swap the arguments using
4022      // the inverse condition code.
4023      ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
4024      if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
4025        // The swapped inverse condition is legal, so swap true and false,
4026        // lhs and rhs.
4027        Legalized = true;
4028        Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
4029      }
4030    }
4031
4032    if (!Legalized) {
4033      Legalized = LegalizeSetCCCondCode(
4034          getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
4035          dl);
4036
4037      assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
4038
4039      // If we expanded the SETCC by inverting the condition code, then swap
4040      // the True/False operands to match.
4041      if (NeedInvert)
4042        std::swap(Tmp3, Tmp4);
4043
4044      // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
4045      // condition code, create a new SELECT_CC node.
4046      if (CC.getNode()) {
4047        Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
4048                           Tmp1, Tmp2, Tmp3, Tmp4, CC);
4049      } else {
4050        Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4051        CC = DAG.getCondCode(ISD::SETNE);
4052        Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
4053                           Tmp2, Tmp3, Tmp4, CC);
4054      }
4055    }
4056    Results.push_back(Tmp1);
4057    break;
4058  }
4059  case ISD::BR_CC: {
4060    Tmp1 = Node->getOperand(0);              // Chain
4061    Tmp2 = Node->getOperand(2);              // LHS
4062    Tmp3 = Node->getOperand(3);              // RHS
4063    Tmp4 = Node->getOperand(1);              // CC
4064
4065    bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
4066        Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
4067    (void)Legalized;
4068    assert(Legalized && "Can't legalize BR_CC with legal condition!");
4069
4070    // If we expanded the SETCC by inverting the condition code, then wrap
4071    // the existing SETCC in a NOT to restore the intended condition.
4072    if (NeedInvert)
4073      Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
4074
4075    // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4076    // node.
4077    if (Tmp4.getNode()) {
4078      Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
4079                         Tmp4, Tmp2, Tmp3, Node->getOperand(4));
4080    } else {
4081      Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
4082      Tmp4 = DAG.getCondCode(ISD::SETNE);
4083      Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4084                         Tmp2, Tmp3, Node->getOperand(4));
4085    }
4086    Results.push_back(Tmp1);
4087    break;
4088  }
4089  case ISD::BUILD_VECTOR:
4090    Results.push_back(ExpandBUILD_VECTOR(Node));
4091    break;
4092  case ISD::SRA:
4093  case ISD::SRL:
4094  case ISD::SHL: {
4095    // Scalarize vector SRA/SRL/SHL.
4096    EVT VT = Node->getValueType(0);
4097    assert(VT.isVector() && "Unable to legalize non-vector shift");
4098    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4099    unsigned NumElem = VT.getVectorNumElements();
4100
4101    SmallVector<SDValue, 8> Scalars;
4102    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4103      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4104                               VT.getScalarType(),
4105                               Node->getOperand(0), DAG.getConstant(Idx,
4106                                                    TLI.getVectorIdxTy()));
4107      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4108                               VT.getScalarType(),
4109                               Node->getOperand(1), DAG.getConstant(Idx,
4110                                                    TLI.getVectorIdxTy()));
4111      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4112                                    VT.getScalarType(), Ex, Sh));
4113    }
4114    SDValue Result =
4115      DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4116    ReplaceNode(SDValue(Node, 0), Result);
4117    break;
4118  }
4119  case ISD::GLOBAL_OFFSET_TABLE:
4120  case ISD::GlobalAddress:
4121  case ISD::GlobalTLSAddress:
4122  case ISD::ExternalSymbol:
4123  case ISD::ConstantPool:
4124  case ISD::JumpTable:
4125  case ISD::INTRINSIC_W_CHAIN:
4126  case ISD::INTRINSIC_WO_CHAIN:
4127  case ISD::INTRINSIC_VOID:
4128    // FIXME: Custom lowering for these operations shouldn't return null!
4129    break;
4130  }
4131
4132  // Replace the original node with the legalized result.
4133  if (!Results.empty())
4134    ReplaceNode(Node, Results.data());
4135}
4136
4137void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4138  SmallVector<SDValue, 8> Results;
4139  MVT OVT = Node->getSimpleValueType(0);
4140  if (Node->getOpcode() == ISD::UINT_TO_FP ||
4141      Node->getOpcode() == ISD::SINT_TO_FP ||
4142      Node->getOpcode() == ISD::SETCC) {
4143    OVT = Node->getOperand(0).getSimpleValueType();
4144  }
4145  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4146  SDLoc dl(Node);
4147  SDValue Tmp1, Tmp2, Tmp3;
4148  switch (Node->getOpcode()) {
4149  case ISD::CTTZ:
4150  case ISD::CTTZ_ZERO_UNDEF:
4151  case ISD::CTLZ:
4152  case ISD::CTLZ_ZERO_UNDEF:
4153  case ISD::CTPOP:
4154    // Zero extend the argument.
4155    Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4156    // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4157    // already the correct result.
4158    Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4159    if (Node->getOpcode() == ISD::CTTZ) {
4160      // FIXME: This should set a bit in the zero extended value instead.
4161      Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4162                          Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
4163                          ISD::SETEQ);
4164      Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4165                           DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
4166    } else if (Node->getOpcode() == ISD::CTLZ ||
4167               Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4168      // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4169      Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4170                          DAG.getConstant(NVT.getSizeInBits() -
4171                                          OVT.getSizeInBits(), NVT));
4172    }
4173    Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4174    break;
4175  case ISD::BSWAP: {
4176    unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4177    Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4178    Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4179    Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4180                          DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
4181    Results.push_back(Tmp1);
4182    break;
4183  }
4184  case ISD::FP_TO_UINT:
4185  case ISD::FP_TO_SINT:
4186    Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4187                                 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4188    Results.push_back(Tmp1);
4189    break;
4190  case ISD::UINT_TO_FP:
4191  case ISD::SINT_TO_FP:
4192    Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4193                                 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4194    Results.push_back(Tmp1);
4195    break;
4196  case ISD::VAARG: {
4197    SDValue Chain = Node->getOperand(0); // Get the chain.
4198    SDValue Ptr = Node->getOperand(1); // Get the pointer.
4199
4200    unsigned TruncOp;
4201    if (OVT.isVector()) {
4202      TruncOp = ISD::BITCAST;
4203    } else {
4204      assert(OVT.isInteger()
4205        && "VAARG promotion is supported only for vectors or integer types");
4206      TruncOp = ISD::TRUNCATE;
4207    }
4208
4209    // Perform the larger operation, then convert back
4210    Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4211             Node->getConstantOperandVal(3));
4212    Chain = Tmp1.getValue(1);
4213
4214    Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4215
4216    // Modified the chain result - switch anything that used the old chain to
4217    // use the new one.
4218    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4219    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4220    ReplacedNode(Node);
4221    break;
4222  }
4223  case ISD::AND:
4224  case ISD::OR:
4225  case ISD::XOR: {
4226    unsigned ExtOp, TruncOp;
4227    if (OVT.isVector()) {
4228      ExtOp   = ISD::BITCAST;
4229      TruncOp = ISD::BITCAST;
4230    } else {
4231      assert(OVT.isInteger() && "Cannot promote logic operation");
4232      ExtOp   = ISD::ANY_EXTEND;
4233      TruncOp = ISD::TRUNCATE;
4234    }
4235    // Promote each of the values to the new type.
4236    Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4237    Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4238    // Perform the larger operation, then convert back
4239    Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4240    Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4241    break;
4242  }
4243  case ISD::SELECT: {
4244    unsigned ExtOp, TruncOp;
4245    if (Node->getValueType(0).isVector() ||
4246        Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4247      ExtOp   = ISD::BITCAST;
4248      TruncOp = ISD::BITCAST;
4249    } else if (Node->getValueType(0).isInteger()) {
4250      ExtOp   = ISD::ANY_EXTEND;
4251      TruncOp = ISD::TRUNCATE;
4252    } else {
4253      ExtOp   = ISD::FP_EXTEND;
4254      TruncOp = ISD::FP_ROUND;
4255    }
4256    Tmp1 = Node->getOperand(0);
4257    // Promote each of the values to the new type.
4258    Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4259    Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4260    // Perform the larger operation, then round down.
4261    Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4262    if (TruncOp != ISD::FP_ROUND)
4263      Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4264    else
4265      Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4266                         DAG.getIntPtrConstant(0));
4267    Results.push_back(Tmp1);
4268    break;
4269  }
4270  case ISD::VECTOR_SHUFFLE: {
4271    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4272
4273    // Cast the two input vectors.
4274    Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4275    Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4276
4277    // Convert the shuffle mask to the right # elements.
4278    Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4279    Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4280    Results.push_back(Tmp1);
4281    break;
4282  }
4283  case ISD::SETCC: {
4284    unsigned ExtOp = ISD::FP_EXTEND;
4285    if (NVT.isInteger()) {
4286      ISD::CondCode CCCode =
4287        cast<CondCodeSDNode>(Node->getOperand(2))->get();
4288      ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4289    }
4290    Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4291    Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4292    Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4293                                  Tmp1, Tmp2, Node->getOperand(2)));
4294    break;
4295  }
4296  case ISD::FDIV:
4297  case ISD::FREM:
4298  case ISD::FPOW: {
4299    Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4300    Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4301    Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4302    Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4303                                  Tmp3, DAG.getIntPtrConstant(0)));
4304    break;
4305  }
4306  case ISD::FLOG2:
4307  case ISD::FEXP2:
4308  case ISD::FLOG:
4309  case ISD::FEXP: {
4310    Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4311    Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4312    Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4313                                  Tmp2, DAG.getIntPtrConstant(0)));
4314    break;
4315  }
4316  }
4317
4318  // Replace the original node with the legalized result.
4319  if (!Results.empty())
4320    ReplaceNode(Node, Results.data());
4321}
4322
4323// SelectionDAG::Legalize - This is the entry point for the file.
4324//
4325void SelectionDAG::Legalize() {
4326  /// run - This is the main entry point to this class.
4327  ///
4328  SelectionDAGLegalize(*this).LegalizeDAG();
4329}
4330