LegalizeDAG.cpp revision 0c8fbe33a4bdf7c60e0cfd5a9c86499c817d9f1a
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 } 83 void AddPromotedOperand(SDOperand From, SDOperand To) { 84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 85 assert(isNew && "Got into the map somehow?"); 86 } 87 88public: 89 90 SelectionDAGLegalize(SelectionDAG &DAG); 91 92 /// Run - While there is still lowering to do, perform a pass over the DAG. 93 /// Most regularization can be done in a single pass, but targets that require 94 /// large values to be split into registers multiple times (e.g. i64 -> 4x 95 /// i16) require iteration for these values (the first iteration will demote 96 /// to i32, the second will demote to i16). 97 void Run() { 98 do { 99 NeedsAnotherIteration = false; 100 LegalizeDAG(); 101 } while (NeedsAnotherIteration); 102 } 103 104 /// getTypeAction - Return how we should legalize values of this type, either 105 /// it is already legal or we need to expand it into multiple registers of 106 /// smaller integer type, or we need to promote it to a larger type. 107 LegalizeAction getTypeAction(MVT::ValueType VT) const { 108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 109 } 110 111 /// isTypeLegal - Return true if this type is legal on this target. 112 /// 113 bool isTypeLegal(MVT::ValueType VT) const { 114 return getTypeAction(VT) == Legal; 115 } 116 117private: 118 void LegalizeDAG(); 119 120 SDOperand LegalizeOp(SDOperand O); 121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 122 SDOperand PromoteOp(SDOperand O); 123 124 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 125 SDOperand &Hi); 126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 127 SDOperand Source); 128 129 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 130 SDOperand LegalOp, 131 MVT::ValueType DestVT); 132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 133 bool isSigned); 134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 135 bool isSigned); 136 137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 138 SDOperand &Lo, SDOperand &Hi); 139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 140 SDOperand &Lo, SDOperand &Hi); 141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 142 SDOperand &Lo, SDOperand &Hi); 143 144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 145 146 SDOperand getIntPtrConstant(uint64_t Val) { 147 return DAG.getConstant(Val, TLI.getPointerTy()); 148 } 149}; 150} 151 152 153SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 154 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 155 ValueTypeActions(TLI.getValueTypeActions()) { 156 assert(MVT::LAST_VALUETYPE <= 16 && 157 "Too many value types for ValueTypeActions to hold!"); 158} 159 160/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 161/// INT_TO_FP operation of the specified operand when the target requests that 162/// we expand it. At this point, we know that the result and operand types are 163/// legal for the target. 164SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 165 SDOperand Op0, 166 MVT::ValueType DestVT) { 167 if (Op0.getValueType() == MVT::i32) { 168 // simple 32-bit [signed|unsigned] integer to float/double expansion 169 170 // get the stack frame index of a 8 byte buffer 171 MachineFunction &MF = DAG.getMachineFunction(); 172 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 173 // get address of 8 byte buffer 174 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 175 // word offset constant for Hi/Lo address computation 176 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 177 // set up Hi and Lo (into buffer) address based on endian 178 SDOperand Hi, Lo; 179 if (TLI.isLittleEndian()) { 180 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 181 Lo = StackSlot; 182 } else { 183 Hi = StackSlot; 184 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 185 } 186 // if signed map to unsigned space 187 SDOperand Op0Mapped; 188 if (isSigned) { 189 // constant used to invert sign bit (signed to unsigned mapping) 190 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 191 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 192 } else { 193 Op0Mapped = Op0; 194 } 195 // store the lo of the constructed double - based on integer input 196 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 197 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 198 // initial hi portion of constructed double 199 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 200 // store the hi of the constructed double - biased exponent 201 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 202 InitialHi, Hi, DAG.getSrcValue(NULL)); 203 // load the constructed double 204 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 205 DAG.getSrcValue(NULL)); 206 // FP constant to bias correct the final result 207 SDOperand Bias = DAG.getConstantFP(isSigned ? 208 BitsToDouble(0x4330000080000000ULL) 209 : BitsToDouble(0x4330000000000000ULL), 210 MVT::f64); 211 // subtract the bias 212 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 213 // final result 214 SDOperand Result; 215 // handle final rounding 216 if (DestVT == MVT::f64) { 217 // do nothing 218 Result = Sub; 219 } else { 220 // if f32 then cast to f32 221 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 222 } 223 NeedsAnotherIteration = true; 224 return Result; 225 } 226 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 227 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 228 229 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 230 DAG.getConstant(0, Op0.getValueType()), 231 ISD::SETLT); 232 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 233 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 234 SignSet, Four, Zero); 235 236 // If the sign bit of the integer is set, the large number will be treated 237 // as a negative number. To counteract this, the dynamic code adds an 238 // offset depending on the data type. 239 uint64_t FF; 240 switch (Op0.getValueType()) { 241 default: assert(0 && "Unsupported integer type!"); 242 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 243 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 244 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 245 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 246 } 247 if (TLI.isLittleEndian()) FF <<= 32; 248 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 249 250 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 251 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 252 SDOperand FudgeInReg; 253 if (DestVT == MVT::f32) 254 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 255 DAG.getSrcValue(NULL)); 256 else { 257 assert(DestVT == MVT::f64 && "Unexpected conversion"); 258 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 259 DAG.getEntryNode(), CPIdx, 260 DAG.getSrcValue(NULL), MVT::f32)); 261 } 262 263 NeedsAnotherIteration = true; 264 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 265} 266 267/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 268/// *INT_TO_FP operation of the specified operand when the target requests that 269/// we promote it. At this point, we know that the result and operand types are 270/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 271/// operation that takes a larger input. 272SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 273 MVT::ValueType DestVT, 274 bool isSigned) { 275 // First step, figure out the appropriate *INT_TO_FP operation to use. 276 MVT::ValueType NewInTy = LegalOp.getValueType(); 277 278 unsigned OpToUse = 0; 279 280 // Scan for the appropriate larger type to use. 281 while (1) { 282 NewInTy = (MVT::ValueType)(NewInTy+1); 283 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 284 285 // If the target supports SINT_TO_FP of this type, use it. 286 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 287 default: break; 288 case TargetLowering::Legal: 289 if (!TLI.isTypeLegal(NewInTy)) 290 break; // Can't use this datatype. 291 // FALL THROUGH. 292 case TargetLowering::Custom: 293 OpToUse = ISD::SINT_TO_FP; 294 break; 295 } 296 if (OpToUse) break; 297 if (isSigned) continue; 298 299 // If the target supports UINT_TO_FP of this type, use it. 300 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 301 default: break; 302 case TargetLowering::Legal: 303 if (!TLI.isTypeLegal(NewInTy)) 304 break; // Can't use this datatype. 305 // FALL THROUGH. 306 case TargetLowering::Custom: 307 OpToUse = ISD::UINT_TO_FP; 308 break; 309 } 310 if (OpToUse) break; 311 312 // Otherwise, try a larger type. 313 } 314 315 // Make sure to legalize any nodes we create here in the next pass. 316 NeedsAnotherIteration = true; 317 318 // Okay, we found the operation and type to use. Zero extend our input to the 319 // desired type then run the operation on it. 320 return DAG.getNode(OpToUse, DestVT, 321 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 322 NewInTy, LegalOp)); 323} 324 325/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 326/// FP_TO_*INT operation of the specified operand when the target requests that 327/// we promote it. At this point, we know that the result and operand types are 328/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 329/// operation that returns a larger result. 330SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 331 MVT::ValueType DestVT, 332 bool isSigned) { 333 // First step, figure out the appropriate FP_TO*INT operation to use. 334 MVT::ValueType NewOutTy = DestVT; 335 336 unsigned OpToUse = 0; 337 338 // Scan for the appropriate larger type to use. 339 while (1) { 340 NewOutTy = (MVT::ValueType)(NewOutTy+1); 341 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 342 343 // If the target supports FP_TO_SINT returning this type, use it. 344 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 345 default: break; 346 case TargetLowering::Legal: 347 if (!TLI.isTypeLegal(NewOutTy)) 348 break; // Can't use this datatype. 349 // FALL THROUGH. 350 case TargetLowering::Custom: 351 OpToUse = ISD::FP_TO_SINT; 352 break; 353 } 354 if (OpToUse) break; 355 356 // If the target supports FP_TO_UINT of this type, use it. 357 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 358 default: break; 359 case TargetLowering::Legal: 360 if (!TLI.isTypeLegal(NewOutTy)) 361 break; // Can't use this datatype. 362 // FALL THROUGH. 363 case TargetLowering::Custom: 364 OpToUse = ISD::FP_TO_UINT; 365 break; 366 } 367 if (OpToUse) break; 368 369 // Otherwise, try a larger type. 370 } 371 372 // Make sure to legalize any nodes we create here in the next pass. 373 NeedsAnotherIteration = true; 374 375 // Okay, we found the operation and type to use. Truncate the result of the 376 // extended FP_TO_*INT operation to the desired size. 377 return DAG.getNode(ISD::TRUNCATE, DestVT, 378 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 379} 380 381/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 382/// not been visited yet and if all of its operands have already been visited. 383static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 384 std::map<SDNode*, unsigned> &Visited) { 385 if (++Visited[N] != N->getNumOperands()) 386 return; // Haven't visited all operands yet 387 388 Order.push_back(N); 389 390 if (N->hasOneUse()) { // Tail recurse in common case. 391 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 392 return; 393 } 394 395 // Now that we have N in, add anything that uses it if all of their operands 396 // are now done. 397 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 398 ComputeTopDownOrdering(*UI, Order, Visited); 399} 400 401 402void SelectionDAGLegalize::LegalizeDAG() { 403 // The legalize process is inherently a bottom-up recursive process (users 404 // legalize their uses before themselves). Given infinite stack space, we 405 // could just start legalizing on the root and traverse the whole graph. In 406 // practice however, this causes us to run out of stack space on large basic 407 // blocks. To avoid this problem, compute an ordering of the nodes where each 408 // node is only legalized after all of its operands are legalized. 409 std::map<SDNode*, unsigned> Visited; 410 std::vector<SDNode*> Order; 411 412 // Compute ordering from all of the leaves in the graphs, those (like the 413 // entry node) that have no operands. 414 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 415 E = DAG.allnodes_end(); I != E; ++I) { 416 if (I->getNumOperands() == 0) { 417 Visited[I] = 0 - 1U; 418 ComputeTopDownOrdering(I, Order, Visited); 419 } 420 } 421 422 assert(Order.size() == Visited.size() && 423 Order.size() == 424 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 425 "Error: DAG is cyclic!"); 426 Visited.clear(); 427 428 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 429 SDNode *N = Order[i]; 430 switch (getTypeAction(N->getValueType(0))) { 431 default: assert(0 && "Bad type action!"); 432 case Legal: 433 LegalizeOp(SDOperand(N, 0)); 434 break; 435 case Promote: 436 PromoteOp(SDOperand(N, 0)); 437 break; 438 case Expand: { 439 SDOperand X, Y; 440 ExpandOp(SDOperand(N, 0), X, Y); 441 break; 442 } 443 } 444 } 445 446 // Finally, it's possible the root changed. Get the new root. 447 SDOperand OldRoot = DAG.getRoot(); 448 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 449 DAG.setRoot(LegalizedNodes[OldRoot]); 450 451 ExpandedNodes.clear(); 452 LegalizedNodes.clear(); 453 PromotedNodes.clear(); 454 455 // Remove dead nodes now. 456 DAG.RemoveDeadNodes(OldRoot.Val); 457} 458 459SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 460 assert(isTypeLegal(Op.getValueType()) && 461 "Caller should expand or promote operands that are not legal!"); 462 SDNode *Node = Op.Val; 463 464 // If this operation defines any values that cannot be represented in a 465 // register on this target, make sure to expand or promote them. 466 if (Node->getNumValues() > 1) { 467 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 468 switch (getTypeAction(Node->getValueType(i))) { 469 case Legal: break; // Nothing to do. 470 case Expand: { 471 SDOperand T1, T2; 472 ExpandOp(Op.getValue(i), T1, T2); 473 assert(LegalizedNodes.count(Op) && 474 "Expansion didn't add legal operands!"); 475 return LegalizedNodes[Op]; 476 } 477 case Promote: 478 PromoteOp(Op.getValue(i)); 479 assert(LegalizedNodes.count(Op) && 480 "Expansion didn't add legal operands!"); 481 return LegalizedNodes[Op]; 482 } 483 } 484 485 // Note that LegalizeOp may be reentered even from single-use nodes, which 486 // means that we always must cache transformed nodes. 487 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 488 if (I != LegalizedNodes.end()) return I->second; 489 490 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 491 492 SDOperand Result = Op; 493 494 switch (Node->getOpcode()) { 495 default: 496 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 497 // If this is a target node, legalize it by legalizing the operands then 498 // passing it through. 499 std::vector<SDOperand> Ops; 500 bool Changed = false; 501 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 502 Ops.push_back(LegalizeOp(Node->getOperand(i))); 503 Changed = Changed || Node->getOperand(i) != Ops.back(); 504 } 505 if (Changed) 506 if (Node->getNumValues() == 1) 507 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 508 else { 509 std::vector<MVT::ValueType> VTs(Node->value_begin(), 510 Node->value_end()); 511 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 512 } 513 514 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 515 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 516 return Result.getValue(Op.ResNo); 517 } 518 // Otherwise this is an unhandled builtin node. splat. 519 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 520 assert(0 && "Do not know how to legalize this operator!"); 521 abort(); 522 case ISD::EntryToken: 523 case ISD::FrameIndex: 524 case ISD::TargetFrameIndex: 525 case ISD::Register: 526 case ISD::TargetConstant: 527 case ISD::GlobalAddress: 528 case ISD::TargetGlobalAddress: 529 case ISD::ExternalSymbol: 530 case ISD::ConstantPool: // Nothing to do. 531 case ISD::BasicBlock: 532 case ISD::CONDCODE: 533 case ISD::VALUETYPE: 534 case ISD::SRCVALUE: 535 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 536 default: assert(0 && "This action is not supported yet!"); 537 case TargetLowering::Custom: { 538 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 539 if (Tmp.Val) { 540 Result = LegalizeOp(Tmp); 541 break; 542 } 543 } // FALLTHROUGH if the target doesn't want to lower this op after all. 544 case TargetLowering::Legal: 545 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 546 break; 547 } 548 break; 549 case ISD::AssertSext: 550 case ISD::AssertZext: 551 Tmp1 = LegalizeOp(Node->getOperand(0)); 552 if (Tmp1 != Node->getOperand(0)) 553 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 554 Node->getOperand(1)); 555 break; 556 case ISD::CopyFromReg: 557 Tmp1 = LegalizeOp(Node->getOperand(0)); 558 if (Tmp1 != Node->getOperand(0)) 559 Result = DAG.getCopyFromReg(Tmp1, 560 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 561 Node->getValueType(0)); 562 else 563 Result = Op.getValue(0); 564 565 // Since CopyFromReg produces two values, make sure to remember that we 566 // legalized both of them. 567 AddLegalizedOperand(Op.getValue(0), Result); 568 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 569 return Result.getValue(Op.ResNo); 570 case ISD::ImplicitDef: 571 Tmp1 = LegalizeOp(Node->getOperand(0)); 572 if (Tmp1 != Node->getOperand(0)) 573 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 574 Tmp1, Node->getOperand(1)); 575 break; 576 case ISD::UNDEF: { 577 MVT::ValueType VT = Op.getValueType(); 578 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 579 default: assert(0 && "This action is not supported yet!"); 580 case TargetLowering::Expand: 581 case TargetLowering::Promote: 582 if (MVT::isInteger(VT)) 583 Result = DAG.getConstant(0, VT); 584 else if (MVT::isFloatingPoint(VT)) 585 Result = DAG.getConstantFP(0, VT); 586 else 587 assert(0 && "Unknown value type!"); 588 break; 589 case TargetLowering::Legal: 590 break; 591 } 592 break; 593 } 594 case ISD::Constant: 595 // We know we don't need to expand constants here, constants only have one 596 // value and we check that it is fine above. 597 598 // FIXME: Maybe we should handle things like targets that don't support full 599 // 32-bit immediates? 600 break; 601 case ISD::ConstantFP: { 602 // Spill FP immediates to the constant pool if the target cannot directly 603 // codegen them. Targets often have some immediate values that can be 604 // efficiently generated into an FP register without a load. We explicitly 605 // leave these constants as ConstantFP nodes for the target to deal with. 606 607 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 608 609 // Check to see if this FP immediate is already legal. 610 bool isLegal = false; 611 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 612 E = TLI.legal_fpimm_end(); I != E; ++I) 613 if (CFP->isExactlyValue(*I)) { 614 isLegal = true; 615 break; 616 } 617 618 if (!isLegal) { 619 // Otherwise we need to spill the constant to memory. 620 bool Extend = false; 621 622 // If a FP immediate is precise when represented as a float, we put it 623 // into the constant pool as a float, even if it's is statically typed 624 // as a double. 625 MVT::ValueType VT = CFP->getValueType(0); 626 bool isDouble = VT == MVT::f64; 627 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 628 Type::FloatTy, CFP->getValue()); 629 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 630 // Only do this if the target has a native EXTLOAD instruction from 631 // f32. 632 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 633 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 634 VT = MVT::f32; 635 Extend = true; 636 } 637 638 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 639 if (Extend) { 640 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 641 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 642 } else { 643 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 644 DAG.getSrcValue(NULL)); 645 } 646 } 647 break; 648 } 649 case ISD::TokenFactor: 650 if (Node->getNumOperands() == 2) { 651 bool Changed = false; 652 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 653 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 654 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 655 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 656 } else { 657 std::vector<SDOperand> Ops; 658 bool Changed = false; 659 // Legalize the operands. 660 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 661 SDOperand Op = Node->getOperand(i); 662 Ops.push_back(LegalizeOp(Op)); 663 Changed |= Ops[i] != Op; 664 } 665 if (Changed) 666 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 667 } 668 break; 669 670 case ISD::CALLSEQ_START: 671 case ISD::CALLSEQ_END: 672 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 673 // Do not try to legalize the target-specific arguments (#1+) 674 Tmp2 = Node->getOperand(0); 675 if (Tmp1 != Tmp2) 676 Node->setAdjCallChain(Tmp1); 677 678 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 679 // nodes are treated specially and are mutated in place. This makes the dag 680 // legalization process more efficient and also makes libcall insertion 681 // easier. 682 break; 683 case ISD::DYNAMIC_STACKALLOC: 684 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 685 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 686 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 687 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 688 Tmp3 != Node->getOperand(2)) { 689 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 690 std::vector<SDOperand> Ops; 691 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 692 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 693 } else 694 Result = Op.getValue(0); 695 696 // Since this op produces two values, make sure to remember that we 697 // legalized both of them. 698 AddLegalizedOperand(SDOperand(Node, 0), Result); 699 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 700 return Result.getValue(Op.ResNo); 701 702 case ISD::TAILCALL: 703 case ISD::CALL: { 704 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 705 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 706 707 bool Changed = false; 708 std::vector<SDOperand> Ops; 709 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 710 Ops.push_back(LegalizeOp(Node->getOperand(i))); 711 Changed |= Ops.back() != Node->getOperand(i); 712 } 713 714 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 715 std::vector<MVT::ValueType> RetTyVTs; 716 RetTyVTs.reserve(Node->getNumValues()); 717 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 718 RetTyVTs.push_back(Node->getValueType(i)); 719 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 720 Node->getOpcode() == ISD::TAILCALL), 0); 721 } else { 722 Result = Result.getValue(0); 723 } 724 // Since calls produce multiple values, make sure to remember that we 725 // legalized all of them. 726 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 727 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 728 return Result.getValue(Op.ResNo); 729 } 730 case ISD::BR: 731 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 732 if (Tmp1 != Node->getOperand(0)) 733 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 734 break; 735 736 case ISD::BRCOND: 737 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 738 739 switch (getTypeAction(Node->getOperand(1).getValueType())) { 740 case Expand: assert(0 && "It's impossible to expand bools"); 741 case Legal: 742 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 743 break; 744 case Promote: 745 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 746 break; 747 } 748 749 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 750 default: assert(0 && "This action is not supported yet!"); 751 case TargetLowering::Expand: 752 // Expand brcond's setcc into its constituent parts and create a BR_CC 753 // Node. 754 if (Tmp2.getOpcode() == ISD::SETCC) { 755 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 756 Tmp2.getOperand(0), Tmp2.getOperand(1), 757 Node->getOperand(2)); 758 } else { 759 // Make sure the condition is either zero or one. It may have been 760 // promoted from something else. 761 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 762 763 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 764 DAG.getCondCode(ISD::SETNE), Tmp2, 765 DAG.getConstant(0, Tmp2.getValueType()), 766 Node->getOperand(2)); 767 } 768 break; 769 case TargetLowering::Legal: 770 // Basic block destination (Op#2) is always legal. 771 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 772 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 773 Node->getOperand(2)); 774 break; 775 } 776 break; 777 case ISD::BR_CC: 778 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 779 780 if (isTypeLegal(Node->getOperand(2).getValueType())) { 781 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 782 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 783 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 784 Tmp3 != Node->getOperand(3)) { 785 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 786 Tmp2, Tmp3, Node->getOperand(4)); 787 } 788 break; 789 } else { 790 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 791 Node->getOperand(2), // LHS 792 Node->getOperand(3), // RHS 793 Node->getOperand(1))); 794 // If we get a SETCC back from legalizing the SETCC node we just 795 // created, then use its LHS, RHS, and CC directly in creating a new 796 // node. Otherwise, select between the true and false value based on 797 // comparing the result of the legalized with zero. 798 if (Tmp2.getOpcode() == ISD::SETCC) { 799 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 800 Tmp2.getOperand(0), Tmp2.getOperand(1), 801 Node->getOperand(4)); 802 } else { 803 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 804 DAG.getCondCode(ISD::SETNE), 805 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 806 Node->getOperand(4)); 807 } 808 } 809 break; 810 case ISD::BRCONDTWOWAY: 811 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 812 switch (getTypeAction(Node->getOperand(1).getValueType())) { 813 case Expand: assert(0 && "It's impossible to expand bools"); 814 case Legal: 815 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 816 break; 817 case Promote: 818 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 819 break; 820 } 821 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 822 // pair. 823 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 824 case TargetLowering::Promote: 825 default: assert(0 && "This action is not supported yet!"); 826 case TargetLowering::Legal: 827 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 828 std::vector<SDOperand> Ops; 829 Ops.push_back(Tmp1); 830 Ops.push_back(Tmp2); 831 Ops.push_back(Node->getOperand(2)); 832 Ops.push_back(Node->getOperand(3)); 833 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 834 } 835 break; 836 case TargetLowering::Expand: 837 // If BRTWOWAY_CC is legal for this target, then simply expand this node 838 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 839 // BRCOND/BR pair. 840 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 841 if (Tmp2.getOpcode() == ISD::SETCC) { 842 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 843 Tmp2.getOperand(0), Tmp2.getOperand(1), 844 Node->getOperand(2), Node->getOperand(3)); 845 } else { 846 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 847 DAG.getConstant(0, Tmp2.getValueType()), 848 Node->getOperand(2), Node->getOperand(3)); 849 } 850 } else { 851 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 852 Node->getOperand(2)); 853 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 854 } 855 break; 856 } 857 break; 858 case ISD::BRTWOWAY_CC: 859 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 860 if (isTypeLegal(Node->getOperand(2).getValueType())) { 861 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 862 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 863 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 864 Tmp3 != Node->getOperand(3)) { 865 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 866 Node->getOperand(4), Node->getOperand(5)); 867 } 868 break; 869 } else { 870 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 871 Node->getOperand(2), // LHS 872 Node->getOperand(3), // RHS 873 Node->getOperand(1))); 874 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 875 // pair. 876 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 877 default: assert(0 && "This action is not supported yet!"); 878 case TargetLowering::Legal: 879 // If we get a SETCC back from legalizing the SETCC node we just 880 // created, then use its LHS, RHS, and CC directly in creating a new 881 // node. Otherwise, select between the true and false value based on 882 // comparing the result of the legalized with zero. 883 if (Tmp2.getOpcode() == ISD::SETCC) { 884 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 885 Tmp2.getOperand(0), Tmp2.getOperand(1), 886 Node->getOperand(4), Node->getOperand(5)); 887 } else { 888 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 889 DAG.getConstant(0, Tmp2.getValueType()), 890 Node->getOperand(4), Node->getOperand(5)); 891 } 892 break; 893 case TargetLowering::Expand: 894 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 895 Node->getOperand(4)); 896 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 897 break; 898 } 899 } 900 break; 901 case ISD::LOAD: 902 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 903 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 904 905 if (Tmp1 != Node->getOperand(0) || 906 Tmp2 != Node->getOperand(1)) 907 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 908 Node->getOperand(2)); 909 else 910 Result = SDOperand(Node, 0); 911 912 // Since loads produce two values, make sure to remember that we legalized 913 // both of them. 914 AddLegalizedOperand(SDOperand(Node, 0), Result); 915 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 916 return Result.getValue(Op.ResNo); 917 918 case ISD::EXTLOAD: 919 case ISD::SEXTLOAD: 920 case ISD::ZEXTLOAD: { 921 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 922 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 923 924 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 925 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 926 default: assert(0 && "This action is not supported yet!"); 927 case TargetLowering::Promote: 928 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 929 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 930 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 931 // Since loads produce two values, make sure to remember that we legalized 932 // both of them. 933 AddLegalizedOperand(SDOperand(Node, 0), Result); 934 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 935 return Result.getValue(Op.ResNo); 936 937 case TargetLowering::Legal: 938 if (Tmp1 != Node->getOperand(0) || 939 Tmp2 != Node->getOperand(1)) 940 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 941 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 942 else 943 Result = SDOperand(Node, 0); 944 945 // Since loads produce two values, make sure to remember that we legalized 946 // both of them. 947 AddLegalizedOperand(SDOperand(Node, 0), Result); 948 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 949 return Result.getValue(Op.ResNo); 950 case TargetLowering::Expand: 951 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 952 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 953 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 954 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 955 if (Op.ResNo) 956 return Load.getValue(1); 957 return Result; 958 } 959 assert(Node->getOpcode() != ISD::EXTLOAD && 960 "EXTLOAD should always be supported!"); 961 // Turn the unsupported load into an EXTLOAD followed by an explicit 962 // zero/sign extend inreg. 963 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 964 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 965 SDOperand ValRes; 966 if (Node->getOpcode() == ISD::SEXTLOAD) 967 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 968 Result, DAG.getValueType(SrcVT)); 969 else 970 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 971 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 972 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 973 if (Op.ResNo) 974 return Result.getValue(1); 975 return ValRes; 976 } 977 assert(0 && "Unreachable"); 978 } 979 case ISD::EXTRACT_ELEMENT: { 980 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 981 switch (getTypeAction(OpTy)) { 982 default: 983 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 984 break; 985 case Legal: 986 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 987 // 1 -> Hi 988 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 989 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 990 TLI.getShiftAmountTy())); 991 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 992 } else { 993 // 0 -> Lo 994 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 995 Node->getOperand(0)); 996 } 997 Result = LegalizeOp(Result); 998 break; 999 case Expand: 1000 // Get both the low and high parts. 1001 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1002 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1003 Result = Tmp2; // 1 -> Hi 1004 else 1005 Result = Tmp1; // 0 -> Lo 1006 break; 1007 } 1008 break; 1009 } 1010 1011 case ISD::CopyToReg: 1012 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1013 1014 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1015 "Register type must be legal!"); 1016 // Legalize the incoming value (must be legal). 1017 Tmp2 = LegalizeOp(Node->getOperand(2)); 1018 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1019 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1020 Node->getOperand(1), Tmp2); 1021 break; 1022 1023 case ISD::RET: 1024 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1025 switch (Node->getNumOperands()) { 1026 case 2: // ret val 1027 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1028 case Legal: 1029 Tmp2 = LegalizeOp(Node->getOperand(1)); 1030 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1031 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1032 break; 1033 case Expand: { 1034 SDOperand Lo, Hi; 1035 ExpandOp(Node->getOperand(1), Lo, Hi); 1036 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1037 break; 1038 } 1039 case Promote: 1040 Tmp2 = PromoteOp(Node->getOperand(1)); 1041 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1042 break; 1043 } 1044 break; 1045 case 1: // ret void 1046 if (Tmp1 != Node->getOperand(0)) 1047 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1048 break; 1049 default: { // ret <values> 1050 std::vector<SDOperand> NewValues; 1051 NewValues.push_back(Tmp1); 1052 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1053 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1054 case Legal: 1055 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1056 break; 1057 case Expand: { 1058 SDOperand Lo, Hi; 1059 ExpandOp(Node->getOperand(i), Lo, Hi); 1060 NewValues.push_back(Lo); 1061 NewValues.push_back(Hi); 1062 break; 1063 } 1064 case Promote: 1065 assert(0 && "Can't promote multiple return value yet!"); 1066 } 1067 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1068 break; 1069 } 1070 } 1071 break; 1072 case ISD::STORE: 1073 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1074 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1075 1076 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1077 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1078 if (CFP->getValueType(0) == MVT::f32) { 1079 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1080 DAG.getConstant(FloatToBits(CFP->getValue()), 1081 MVT::i32), 1082 Tmp2, 1083 Node->getOperand(3)); 1084 } else { 1085 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1086 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1087 DAG.getConstant(DoubleToBits(CFP->getValue()), 1088 MVT::i64), 1089 Tmp2, 1090 Node->getOperand(3)); 1091 } 1092 Node = Result.Val; 1093 } 1094 1095 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1096 case Legal: { 1097 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1098 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1099 Tmp2 != Node->getOperand(2)) 1100 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1101 Node->getOperand(3)); 1102 break; 1103 } 1104 case Promote: 1105 // Truncate the value and store the result. 1106 Tmp3 = PromoteOp(Node->getOperand(1)); 1107 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1108 Node->getOperand(3), 1109 DAG.getValueType(Node->getOperand(1).getValueType())); 1110 break; 1111 1112 case Expand: 1113 SDOperand Lo, Hi; 1114 ExpandOp(Node->getOperand(1), Lo, Hi); 1115 1116 if (!TLI.isLittleEndian()) 1117 std::swap(Lo, Hi); 1118 1119 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1120 Node->getOperand(3)); 1121 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1122 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1123 getIntPtrConstant(IncrementSize)); 1124 assert(isTypeLegal(Tmp2.getValueType()) && 1125 "Pointers must be legal!"); 1126 //Again, claiming both parts of the store came form the same Instr 1127 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1128 Node->getOperand(3)); 1129 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1130 break; 1131 } 1132 break; 1133 case ISD::PCMARKER: 1134 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1135 if (Tmp1 != Node->getOperand(0)) 1136 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1137 break; 1138 case ISD::READCYCLECOUNTER: 1139 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1140 if (Tmp1 != Node->getOperand(0)) 1141 Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1); 1142 break; 1143 case ISD::TRUNCSTORE: 1144 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1145 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1146 1147 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1148 case Legal: 1149 Tmp2 = LegalizeOp(Node->getOperand(1)); 1150 1151 // The only promote case we handle is TRUNCSTORE:i1 X into 1152 // -> TRUNCSTORE:i8 (and X, 1) 1153 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1154 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1155 TargetLowering::Promote) { 1156 // Promote the bool to a mask then store. 1157 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1158 DAG.getConstant(1, Tmp2.getValueType())); 1159 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1160 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1161 1162 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1163 Tmp3 != Node->getOperand(2)) { 1164 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1165 Node->getOperand(3), Node->getOperand(4)); 1166 } 1167 break; 1168 case Promote: 1169 case Expand: 1170 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1171 } 1172 break; 1173 case ISD::SELECT: 1174 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1175 case Expand: assert(0 && "It's impossible to expand bools"); 1176 case Legal: 1177 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1178 break; 1179 case Promote: 1180 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1181 break; 1182 } 1183 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1184 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1185 1186 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1187 default: assert(0 && "This action is not supported yet!"); 1188 case TargetLowering::Expand: 1189 if (Tmp1.getOpcode() == ISD::SETCC) { 1190 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1191 Tmp2, Tmp3, 1192 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1193 } else { 1194 // Make sure the condition is either zero or one. It may have been 1195 // promoted from something else. 1196 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1197 Result = DAG.getSelectCC(Tmp1, 1198 DAG.getConstant(0, Tmp1.getValueType()), 1199 Tmp2, Tmp3, ISD::SETNE); 1200 } 1201 break; 1202 case TargetLowering::Legal: 1203 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1204 Tmp3 != Node->getOperand(2)) 1205 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1206 Tmp1, Tmp2, Tmp3); 1207 break; 1208 case TargetLowering::Promote: { 1209 MVT::ValueType NVT = 1210 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1211 unsigned ExtOp, TruncOp; 1212 if (MVT::isInteger(Tmp2.getValueType())) { 1213 ExtOp = ISD::ANY_EXTEND; 1214 TruncOp = ISD::TRUNCATE; 1215 } else { 1216 ExtOp = ISD::FP_EXTEND; 1217 TruncOp = ISD::FP_ROUND; 1218 } 1219 // Promote each of the values to the new type. 1220 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1221 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1222 // Perform the larger operation, then round down. 1223 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1224 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1225 break; 1226 } 1227 } 1228 break; 1229 case ISD::SELECT_CC: 1230 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1231 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1232 1233 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1234 // Everything is legal, see if we should expand this op or something. 1235 switch (TLI.getOperationAction(ISD::SELECT_CC, 1236 Node->getOperand(0).getValueType())) { 1237 default: assert(0 && "This action is not supported yet!"); 1238 case TargetLowering::Custom: { 1239 SDOperand Tmp = 1240 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1241 Node->getOperand(0), 1242 Node->getOperand(1), Tmp3, Tmp4, 1243 Node->getOperand(4)), DAG); 1244 if (Tmp.Val) { 1245 Result = LegalizeOp(Tmp); 1246 break; 1247 } 1248 } // FALLTHROUGH if the target can't lower this operation after all. 1249 case TargetLowering::Legal: 1250 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1251 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1252 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1253 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1254 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1255 Tmp3, Tmp4, Node->getOperand(4)); 1256 } 1257 break; 1258 } 1259 break; 1260 } else { 1261 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1262 Node->getOperand(0), // LHS 1263 Node->getOperand(1), // RHS 1264 Node->getOperand(4))); 1265 // If we get a SETCC back from legalizing the SETCC node we just 1266 // created, then use its LHS, RHS, and CC directly in creating a new 1267 // node. Otherwise, select between the true and false value based on 1268 // comparing the result of the legalized with zero. 1269 if (Tmp1.getOpcode() == ISD::SETCC) { 1270 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1271 Tmp1.getOperand(0), Tmp1.getOperand(1), 1272 Tmp3, Tmp4, Tmp1.getOperand(2)); 1273 } else { 1274 Result = DAG.getSelectCC(Tmp1, 1275 DAG.getConstant(0, Tmp1.getValueType()), 1276 Tmp3, Tmp4, ISD::SETNE); 1277 } 1278 } 1279 break; 1280 case ISD::SETCC: 1281 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1282 case Legal: 1283 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1284 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1285 break; 1286 case Promote: 1287 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1288 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1289 1290 // If this is an FP compare, the operands have already been extended. 1291 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1292 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1293 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1294 1295 // Otherwise, we have to insert explicit sign or zero extends. Note 1296 // that we could insert sign extends for ALL conditions, but zero extend 1297 // is cheaper on many machines (an AND instead of two shifts), so prefer 1298 // it. 1299 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1300 default: assert(0 && "Unknown integer comparison!"); 1301 case ISD::SETEQ: 1302 case ISD::SETNE: 1303 case ISD::SETUGE: 1304 case ISD::SETUGT: 1305 case ISD::SETULE: 1306 case ISD::SETULT: 1307 // ALL of these operations will work if we either sign or zero extend 1308 // the operands (including the unsigned comparisons!). Zero extend is 1309 // usually a simpler/cheaper operation, so prefer it. 1310 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1311 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1312 break; 1313 case ISD::SETGE: 1314 case ISD::SETGT: 1315 case ISD::SETLT: 1316 case ISD::SETLE: 1317 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1318 DAG.getValueType(VT)); 1319 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1320 DAG.getValueType(VT)); 1321 break; 1322 } 1323 } 1324 break; 1325 case Expand: 1326 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1327 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1328 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1329 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1330 case ISD::SETEQ: 1331 case ISD::SETNE: 1332 if (RHSLo == RHSHi) 1333 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1334 if (RHSCST->isAllOnesValue()) { 1335 // Comparison to -1. 1336 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1337 Tmp2 = RHSLo; 1338 break; 1339 } 1340 1341 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1342 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1343 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1344 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1345 break; 1346 default: 1347 // If this is a comparison of the sign bit, just look at the top part. 1348 // X > -1, x < 0 1349 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1350 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1351 CST->getValue() == 0) || // X < 0 1352 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1353 (CST->isAllOnesValue()))) { // X > -1 1354 Tmp1 = LHSHi; 1355 Tmp2 = RHSHi; 1356 break; 1357 } 1358 1359 // FIXME: This generated code sucks. 1360 ISD::CondCode LowCC; 1361 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1362 default: assert(0 && "Unknown integer setcc!"); 1363 case ISD::SETLT: 1364 case ISD::SETULT: LowCC = ISD::SETULT; break; 1365 case ISD::SETGT: 1366 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1367 case ISD::SETLE: 1368 case ISD::SETULE: LowCC = ISD::SETULE; break; 1369 case ISD::SETGE: 1370 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1371 } 1372 1373 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1374 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1375 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1376 1377 // NOTE: on targets without efficient SELECT of bools, we can always use 1378 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1379 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1380 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1381 Node->getOperand(2)); 1382 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1383 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1384 Result, Tmp1, Tmp2)); 1385 return Result; 1386 } 1387 } 1388 1389 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1390 default: 1391 assert(0 && "Cannot handle this action for SETCC yet!"); 1392 break; 1393 case TargetLowering::Promote: 1394 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1395 Node->getOperand(2)); 1396 break; 1397 case TargetLowering::Legal: 1398 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1399 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1400 Node->getOperand(2)); 1401 break; 1402 case TargetLowering::Expand: 1403 // Expand a setcc node into a select_cc of the same condition, lhs, and 1404 // rhs that selects between const 1 (true) and const 0 (false). 1405 MVT::ValueType VT = Node->getValueType(0); 1406 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1407 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1408 Node->getOperand(2)); 1409 Result = LegalizeOp(Result); 1410 break; 1411 } 1412 break; 1413 1414 case ISD::MEMSET: 1415 case ISD::MEMCPY: 1416 case ISD::MEMMOVE: { 1417 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1418 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1419 1420 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1421 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1422 case Expand: assert(0 && "Cannot expand a byte!"); 1423 case Legal: 1424 Tmp3 = LegalizeOp(Node->getOperand(2)); 1425 break; 1426 case Promote: 1427 Tmp3 = PromoteOp(Node->getOperand(2)); 1428 break; 1429 } 1430 } else { 1431 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1432 } 1433 1434 SDOperand Tmp4; 1435 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1436 case Expand: { 1437 // Length is too big, just take the lo-part of the length. 1438 SDOperand HiPart; 1439 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1440 break; 1441 } 1442 case Legal: 1443 Tmp4 = LegalizeOp(Node->getOperand(3)); 1444 break; 1445 case Promote: 1446 Tmp4 = PromoteOp(Node->getOperand(3)); 1447 break; 1448 } 1449 1450 SDOperand Tmp5; 1451 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1452 case Expand: assert(0 && "Cannot expand this yet!"); 1453 case Legal: 1454 Tmp5 = LegalizeOp(Node->getOperand(4)); 1455 break; 1456 case Promote: 1457 Tmp5 = PromoteOp(Node->getOperand(4)); 1458 break; 1459 } 1460 1461 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1462 default: assert(0 && "This action not implemented for this operation!"); 1463 case TargetLowering::Custom: { 1464 SDOperand Tmp = 1465 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1466 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1467 if (Tmp.Val) { 1468 Result = LegalizeOp(Tmp); 1469 break; 1470 } 1471 // FALLTHROUGH if the target thinks it is legal. 1472 } 1473 case TargetLowering::Legal: 1474 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1475 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1476 Tmp5 != Node->getOperand(4)) { 1477 std::vector<SDOperand> Ops; 1478 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1479 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1480 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1481 } 1482 break; 1483 case TargetLowering::Expand: { 1484 // Otherwise, the target does not support this operation. Lower the 1485 // operation to an explicit libcall as appropriate. 1486 MVT::ValueType IntPtr = TLI.getPointerTy(); 1487 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1488 std::vector<std::pair<SDOperand, const Type*> > Args; 1489 1490 const char *FnName = 0; 1491 if (Node->getOpcode() == ISD::MEMSET) { 1492 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1493 // Extend the ubyte argument to be an int value for the call. 1494 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1495 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1496 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1497 1498 FnName = "memset"; 1499 } else if (Node->getOpcode() == ISD::MEMCPY || 1500 Node->getOpcode() == ISD::MEMMOVE) { 1501 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1502 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1503 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1504 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1505 } else { 1506 assert(0 && "Unknown op!"); 1507 } 1508 1509 std::pair<SDOperand,SDOperand> CallResult = 1510 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1511 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1512 Result = CallResult.second; 1513 NeedsAnotherIteration = true; 1514 break; 1515 } 1516 } 1517 break; 1518 } 1519 1520 case ISD::READPORT: 1521 Tmp1 = LegalizeOp(Node->getOperand(0)); 1522 Tmp2 = LegalizeOp(Node->getOperand(1)); 1523 1524 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1525 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1526 std::vector<SDOperand> Ops; 1527 Ops.push_back(Tmp1); 1528 Ops.push_back(Tmp2); 1529 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1530 } else 1531 Result = SDOperand(Node, 0); 1532 // Since these produce two values, make sure to remember that we legalized 1533 // both of them. 1534 AddLegalizedOperand(SDOperand(Node, 0), Result); 1535 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1536 return Result.getValue(Op.ResNo); 1537 case ISD::WRITEPORT: 1538 Tmp1 = LegalizeOp(Node->getOperand(0)); 1539 Tmp2 = LegalizeOp(Node->getOperand(1)); 1540 Tmp3 = LegalizeOp(Node->getOperand(2)); 1541 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1542 Tmp3 != Node->getOperand(2)) 1543 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1544 break; 1545 1546 case ISD::READIO: 1547 Tmp1 = LegalizeOp(Node->getOperand(0)); 1548 Tmp2 = LegalizeOp(Node->getOperand(1)); 1549 1550 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1551 case TargetLowering::Custom: 1552 default: assert(0 && "This action not implemented for this operation!"); 1553 case TargetLowering::Legal: 1554 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1555 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1556 std::vector<SDOperand> Ops; 1557 Ops.push_back(Tmp1); 1558 Ops.push_back(Tmp2); 1559 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1560 } else 1561 Result = SDOperand(Node, 0); 1562 break; 1563 case TargetLowering::Expand: 1564 // Replace this with a load from memory. 1565 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1566 Node->getOperand(1), DAG.getSrcValue(NULL)); 1567 Result = LegalizeOp(Result); 1568 break; 1569 } 1570 1571 // Since these produce two values, make sure to remember that we legalized 1572 // both of them. 1573 AddLegalizedOperand(SDOperand(Node, 0), Result); 1574 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1575 return Result.getValue(Op.ResNo); 1576 1577 case ISD::WRITEIO: 1578 Tmp1 = LegalizeOp(Node->getOperand(0)); 1579 Tmp2 = LegalizeOp(Node->getOperand(1)); 1580 Tmp3 = LegalizeOp(Node->getOperand(2)); 1581 1582 switch (TLI.getOperationAction(Node->getOpcode(), 1583 Node->getOperand(1).getValueType())) { 1584 case TargetLowering::Custom: 1585 default: assert(0 && "This action not implemented for this operation!"); 1586 case TargetLowering::Legal: 1587 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1588 Tmp3 != Node->getOperand(2)) 1589 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1590 break; 1591 case TargetLowering::Expand: 1592 // Replace this with a store to memory. 1593 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1594 Node->getOperand(1), Node->getOperand(2), 1595 DAG.getSrcValue(NULL)); 1596 Result = LegalizeOp(Result); 1597 break; 1598 } 1599 break; 1600 1601 case ISD::ADD_PARTS: 1602 case ISD::SUB_PARTS: 1603 case ISD::SHL_PARTS: 1604 case ISD::SRA_PARTS: 1605 case ISD::SRL_PARTS: { 1606 std::vector<SDOperand> Ops; 1607 bool Changed = false; 1608 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1609 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1610 Changed |= Ops.back() != Node->getOperand(i); 1611 } 1612 if (Changed) { 1613 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1614 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1615 } 1616 1617 // Since these produce multiple values, make sure to remember that we 1618 // legalized all of them. 1619 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1620 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1621 return Result.getValue(Op.ResNo); 1622 } 1623 1624 // Binary operators 1625 case ISD::ADD: 1626 case ISD::SUB: 1627 case ISD::MUL: 1628 case ISD::MULHS: 1629 case ISD::MULHU: 1630 case ISD::UDIV: 1631 case ISD::SDIV: 1632 case ISD::AND: 1633 case ISD::OR: 1634 case ISD::XOR: 1635 case ISD::SHL: 1636 case ISD::SRL: 1637 case ISD::SRA: 1638 case ISD::FADD: 1639 case ISD::FSUB: 1640 case ISD::FMUL: 1641 case ISD::FDIV: 1642 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1643 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1644 case Expand: assert(0 && "Not possible"); 1645 case Legal: 1646 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1647 break; 1648 case Promote: 1649 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1650 break; 1651 } 1652 if (Tmp1 != Node->getOperand(0) || 1653 Tmp2 != Node->getOperand(1)) 1654 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1655 break; 1656 1657 case ISD::BUILD_PAIR: { 1658 MVT::ValueType PairTy = Node->getValueType(0); 1659 // TODO: handle the case where the Lo and Hi operands are not of legal type 1660 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1661 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1662 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1663 case TargetLowering::Legal: 1664 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1665 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1666 break; 1667 case TargetLowering::Promote: 1668 case TargetLowering::Custom: 1669 assert(0 && "Cannot promote/custom this yet!"); 1670 case TargetLowering::Expand: 1671 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1672 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1673 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1674 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1675 TLI.getShiftAmountTy())); 1676 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1677 break; 1678 } 1679 break; 1680 } 1681 1682 case ISD::UREM: 1683 case ISD::SREM: 1684 case ISD::FREM: 1685 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1686 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1687 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1688 case TargetLowering::Legal: 1689 if (Tmp1 != Node->getOperand(0) || 1690 Tmp2 != Node->getOperand(1)) 1691 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1692 Tmp2); 1693 break; 1694 case TargetLowering::Promote: 1695 case TargetLowering::Custom: 1696 assert(0 && "Cannot promote/custom handle this yet!"); 1697 case TargetLowering::Expand: 1698 if (MVT::isInteger(Node->getValueType(0))) { 1699 MVT::ValueType VT = Node->getValueType(0); 1700 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1701 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1702 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1703 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1704 } else { 1705 // Floating point mod -> fmod libcall. 1706 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1707 SDOperand Dummy; 1708 Result = ExpandLibCall(FnName, Node, Dummy); 1709 } 1710 break; 1711 } 1712 break; 1713 1714 case ISD::CTPOP: 1715 case ISD::CTTZ: 1716 case ISD::CTLZ: 1717 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1718 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1719 case TargetLowering::Legal: 1720 if (Tmp1 != Node->getOperand(0)) 1721 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1722 break; 1723 case TargetLowering::Promote: { 1724 MVT::ValueType OVT = Tmp1.getValueType(); 1725 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1726 1727 // Zero extend the argument. 1728 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1729 // Perform the larger operation, then subtract if needed. 1730 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1731 switch(Node->getOpcode()) 1732 { 1733 case ISD::CTPOP: 1734 Result = Tmp1; 1735 break; 1736 case ISD::CTTZ: 1737 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1738 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1739 DAG.getConstant(getSizeInBits(NVT), NVT), 1740 ISD::SETEQ); 1741 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1742 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1743 break; 1744 case ISD::CTLZ: 1745 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1746 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1747 DAG.getConstant(getSizeInBits(NVT) - 1748 getSizeInBits(OVT), NVT)); 1749 break; 1750 } 1751 break; 1752 } 1753 case TargetLowering::Custom: 1754 assert(0 && "Cannot custom handle this yet!"); 1755 case TargetLowering::Expand: 1756 switch(Node->getOpcode()) 1757 { 1758 case ISD::CTPOP: { 1759 static const uint64_t mask[6] = { 1760 0x5555555555555555ULL, 0x3333333333333333ULL, 1761 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1762 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1763 }; 1764 MVT::ValueType VT = Tmp1.getValueType(); 1765 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1766 unsigned len = getSizeInBits(VT); 1767 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1768 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1769 Tmp2 = DAG.getConstant(mask[i], VT); 1770 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1771 Tmp1 = DAG.getNode(ISD::ADD, VT, 1772 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1773 DAG.getNode(ISD::AND, VT, 1774 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1775 Tmp2)); 1776 } 1777 Result = Tmp1; 1778 break; 1779 } 1780 case ISD::CTLZ: { 1781 /* for now, we do this: 1782 x = x | (x >> 1); 1783 x = x | (x >> 2); 1784 ... 1785 x = x | (x >>16); 1786 x = x | (x >>32); // for 64-bit input 1787 return popcount(~x); 1788 1789 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 1790 MVT::ValueType VT = Tmp1.getValueType(); 1791 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1792 unsigned len = getSizeInBits(VT); 1793 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1794 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1795 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 1796 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 1797 } 1798 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 1799 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1800 break; 1801 } 1802 case ISD::CTTZ: { 1803 // for now, we use: { return popcount(~x & (x - 1)); } 1804 // unless the target has ctlz but not ctpop, in which case we use: 1805 // { return 32 - nlz(~x & (x-1)); } 1806 // see also http://www.hackersdelight.org/HDcode/ntz.cc 1807 MVT::ValueType VT = Tmp1.getValueType(); 1808 Tmp2 = DAG.getConstant(~0ULL, VT); 1809 Tmp3 = DAG.getNode(ISD::AND, VT, 1810 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 1811 DAG.getNode(ISD::SUB, VT, Tmp1, 1812 DAG.getConstant(1, VT))); 1813 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 1814 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 1815 TLI.isOperationLegal(ISD::CTLZ, VT)) { 1816 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 1817 DAG.getConstant(getSizeInBits(VT), VT), 1818 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 1819 } else { 1820 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1821 } 1822 break; 1823 } 1824 default: 1825 assert(0 && "Cannot expand this yet!"); 1826 break; 1827 } 1828 break; 1829 } 1830 break; 1831 1832 // Unary operators 1833 case ISD::FABS: 1834 case ISD::FNEG: 1835 case ISD::FSQRT: 1836 case ISD::FSIN: 1837 case ISD::FCOS: 1838 Tmp1 = LegalizeOp(Node->getOperand(0)); 1839 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1840 case TargetLowering::Legal: 1841 if (Tmp1 != Node->getOperand(0)) 1842 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1843 break; 1844 case TargetLowering::Promote: 1845 case TargetLowering::Custom: 1846 assert(0 && "Cannot promote/custom handle this yet!"); 1847 case TargetLowering::Expand: 1848 switch(Node->getOpcode()) { 1849 case ISD::FNEG: { 1850 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1851 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1852 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 1853 Tmp2, Tmp1)); 1854 break; 1855 } 1856 case ISD::FABS: { 1857 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1858 MVT::ValueType VT = Node->getValueType(0); 1859 Tmp2 = DAG.getConstantFP(0.0, VT); 1860 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 1861 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1862 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1863 Result = LegalizeOp(Result); 1864 break; 1865 } 1866 case ISD::FSQRT: 1867 case ISD::FSIN: 1868 case ISD::FCOS: { 1869 MVT::ValueType VT = Node->getValueType(0); 1870 const char *FnName = 0; 1871 switch(Node->getOpcode()) { 1872 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1873 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1874 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1875 default: assert(0 && "Unreachable!"); 1876 } 1877 SDOperand Dummy; 1878 Result = ExpandLibCall(FnName, Node, Dummy); 1879 break; 1880 } 1881 default: 1882 assert(0 && "Unreachable!"); 1883 } 1884 break; 1885 } 1886 break; 1887 1888 // Conversion operators. The source and destination have different types. 1889 case ISD::SINT_TO_FP: 1890 case ISD::UINT_TO_FP: { 1891 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 1892 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1893 case Legal: 1894 switch (TLI.getOperationAction(Node->getOpcode(), 1895 Node->getOperand(0).getValueType())) { 1896 default: assert(0 && "Unknown operation action!"); 1897 case TargetLowering::Expand: 1898 Result = ExpandLegalINT_TO_FP(isSigned, 1899 LegalizeOp(Node->getOperand(0)), 1900 Node->getValueType(0)); 1901 AddLegalizedOperand(Op, Result); 1902 return Result; 1903 case TargetLowering::Promote: 1904 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 1905 Node->getValueType(0), 1906 isSigned); 1907 AddLegalizedOperand(Op, Result); 1908 return Result; 1909 case TargetLowering::Legal: 1910 break; 1911 } 1912 1913 Tmp1 = LegalizeOp(Node->getOperand(0)); 1914 if (Tmp1 != Node->getOperand(0)) 1915 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1916 break; 1917 case Expand: 1918 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 1919 Node->getValueType(0), Node->getOperand(0)); 1920 break; 1921 case Promote: 1922 if (isSigned) { 1923 Result = PromoteOp(Node->getOperand(0)); 1924 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1925 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 1926 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 1927 } else { 1928 Result = PromoteOp(Node->getOperand(0)); 1929 Result = DAG.getZeroExtendInReg(Result, 1930 Node->getOperand(0).getValueType()); 1931 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 1932 } 1933 break; 1934 } 1935 break; 1936 } 1937 case ISD::TRUNCATE: 1938 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1939 case Legal: 1940 Tmp1 = LegalizeOp(Node->getOperand(0)); 1941 if (Tmp1 != Node->getOperand(0)) 1942 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1943 break; 1944 case Expand: 1945 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1946 1947 // Since the result is legal, we should just be able to truncate the low 1948 // part of the source. 1949 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 1950 break; 1951 case Promote: 1952 Result = PromoteOp(Node->getOperand(0)); 1953 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 1954 break; 1955 } 1956 break; 1957 1958 case ISD::FP_TO_SINT: 1959 case ISD::FP_TO_UINT: 1960 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1961 case Legal: 1962 Tmp1 = LegalizeOp(Node->getOperand(0)); 1963 1964 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 1965 default: assert(0 && "Unknown operation action!"); 1966 case TargetLowering::Expand: 1967 if (Node->getOpcode() == ISD::FP_TO_UINT) { 1968 SDOperand True, False; 1969 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1970 MVT::ValueType NVT = Node->getValueType(0); 1971 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 1972 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 1973 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 1974 Node->getOperand(0), Tmp2, ISD::SETLT); 1975 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 1976 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 1977 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 1978 Tmp2)); 1979 False = DAG.getNode(ISD::XOR, NVT, False, 1980 DAG.getConstant(1ULL << ShiftAmt, NVT)); 1981 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 1982 return Result; 1983 } else { 1984 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 1985 } 1986 break; 1987 case TargetLowering::Promote: 1988 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 1989 Node->getOpcode() == ISD::FP_TO_SINT); 1990 AddLegalizedOperand(Op, Result); 1991 return Result; 1992 case TargetLowering::Custom: { 1993 SDOperand Tmp = 1994 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1995 Tmp = TLI.LowerOperation(Tmp, DAG); 1996 if (Tmp.Val) { 1997 AddLegalizedOperand(Op, Tmp); 1998 NeedsAnotherIteration = true; 1999 return Tmp; 2000 } else { 2001 // The target thinks this is legal afterall. 2002 break; 2003 } 2004 } 2005 case TargetLowering::Legal: 2006 break; 2007 } 2008 2009 if (Tmp1 != Node->getOperand(0)) 2010 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2011 break; 2012 case Expand: 2013 assert(0 && "Shouldn't need to expand other operators here!"); 2014 case Promote: 2015 Result = PromoteOp(Node->getOperand(0)); 2016 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2017 break; 2018 } 2019 break; 2020 2021 case ISD::ANY_EXTEND: 2022 case ISD::ZERO_EXTEND: 2023 case ISD::SIGN_EXTEND: 2024 case ISD::FP_EXTEND: 2025 case ISD::FP_ROUND: 2026 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2027 case Legal: 2028 Tmp1 = LegalizeOp(Node->getOperand(0)); 2029 if (Tmp1 != Node->getOperand(0)) 2030 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2031 break; 2032 case Expand: 2033 assert(0 && "Shouldn't need to expand other operators here!"); 2034 2035 case Promote: 2036 switch (Node->getOpcode()) { 2037 case ISD::ANY_EXTEND: 2038 Result = PromoteOp(Node->getOperand(0)); 2039 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2040 break; 2041 case ISD::ZERO_EXTEND: 2042 Result = PromoteOp(Node->getOperand(0)); 2043 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2044 Result = DAG.getZeroExtendInReg(Result, 2045 Node->getOperand(0).getValueType()); 2046 break; 2047 case ISD::SIGN_EXTEND: 2048 Result = PromoteOp(Node->getOperand(0)); 2049 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2050 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2051 Result, 2052 DAG.getValueType(Node->getOperand(0).getValueType())); 2053 break; 2054 case ISD::FP_EXTEND: 2055 Result = PromoteOp(Node->getOperand(0)); 2056 if (Result.getValueType() != Op.getValueType()) 2057 // Dynamically dead while we have only 2 FP types. 2058 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2059 break; 2060 case ISD::FP_ROUND: 2061 Result = PromoteOp(Node->getOperand(0)); 2062 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2063 break; 2064 } 2065 } 2066 break; 2067 case ISD::FP_ROUND_INREG: 2068 case ISD::SIGN_EXTEND_INREG: { 2069 Tmp1 = LegalizeOp(Node->getOperand(0)); 2070 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2071 2072 // If this operation is not supported, convert it to a shl/shr or load/store 2073 // pair. 2074 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2075 default: assert(0 && "This action not supported for this op yet!"); 2076 case TargetLowering::Legal: 2077 if (Tmp1 != Node->getOperand(0)) 2078 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2079 DAG.getValueType(ExtraVT)); 2080 break; 2081 case TargetLowering::Expand: 2082 // If this is an integer extend and shifts are supported, do that. 2083 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2084 // NOTE: we could fall back on load/store here too for targets without 2085 // SAR. However, it is doubtful that any exist. 2086 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2087 MVT::getSizeInBits(ExtraVT); 2088 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2089 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2090 Node->getOperand(0), ShiftCst); 2091 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2092 Result, ShiftCst); 2093 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2094 // The only way we can lower this is to turn it into a STORETRUNC, 2095 // EXTLOAD pair, targetting a temporary location (a stack slot). 2096 2097 // NOTE: there is a choice here between constantly creating new stack 2098 // slots and always reusing the same one. We currently always create 2099 // new ones, as reuse may inhibit scheduling. 2100 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2101 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2102 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2103 MachineFunction &MF = DAG.getMachineFunction(); 2104 int SSFI = 2105 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2106 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2107 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2108 Node->getOperand(0), StackSlot, 2109 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2110 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2111 Result, StackSlot, DAG.getSrcValue(NULL), 2112 ExtraVT); 2113 } else { 2114 assert(0 && "Unknown op"); 2115 } 2116 Result = LegalizeOp(Result); 2117 break; 2118 } 2119 break; 2120 } 2121 } 2122 2123 // Note that LegalizeOp may be reentered even from single-use nodes, which 2124 // means that we always must cache transformed nodes. 2125 AddLegalizedOperand(Op, Result); 2126 return Result; 2127} 2128 2129/// PromoteOp - Given an operation that produces a value in an invalid type, 2130/// promote it to compute the value into a larger type. The produced value will 2131/// have the correct bits for the low portion of the register, but no guarantee 2132/// is made about the top bits: it may be zero, sign-extended, or garbage. 2133SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2134 MVT::ValueType VT = Op.getValueType(); 2135 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2136 assert(getTypeAction(VT) == Promote && 2137 "Caller should expand or legalize operands that are not promotable!"); 2138 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2139 "Cannot promote to smaller type!"); 2140 2141 SDOperand Tmp1, Tmp2, Tmp3; 2142 2143 SDOperand Result; 2144 SDNode *Node = Op.Val; 2145 2146 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2147 if (I != PromotedNodes.end()) return I->second; 2148 2149 // Promotion needs an optimization step to clean up after it, and is not 2150 // careful to avoid operations the target does not support. Make sure that 2151 // all generated operations are legalized in the next iteration. 2152 NeedsAnotherIteration = true; 2153 2154 switch (Node->getOpcode()) { 2155 case ISD::CopyFromReg: 2156 assert(0 && "CopyFromReg must be legal!"); 2157 default: 2158 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2159 assert(0 && "Do not know how to promote this operator!"); 2160 abort(); 2161 case ISD::UNDEF: 2162 Result = DAG.getNode(ISD::UNDEF, NVT); 2163 break; 2164 case ISD::Constant: 2165 if (VT != MVT::i1) 2166 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2167 else 2168 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2169 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2170 break; 2171 case ISD::ConstantFP: 2172 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2173 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2174 break; 2175 2176 case ISD::SETCC: 2177 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2178 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2179 Node->getOperand(1), Node->getOperand(2)); 2180 Result = LegalizeOp(Result); 2181 break; 2182 2183 case ISD::TRUNCATE: 2184 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2185 case Legal: 2186 Result = LegalizeOp(Node->getOperand(0)); 2187 assert(Result.getValueType() >= NVT && 2188 "This truncation doesn't make sense!"); 2189 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2190 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2191 break; 2192 case Promote: 2193 // The truncation is not required, because we don't guarantee anything 2194 // about high bits anyway. 2195 Result = PromoteOp(Node->getOperand(0)); 2196 break; 2197 case Expand: 2198 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2199 // Truncate the low part of the expanded value to the result type 2200 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2201 } 2202 break; 2203 case ISD::SIGN_EXTEND: 2204 case ISD::ZERO_EXTEND: 2205 case ISD::ANY_EXTEND: 2206 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2207 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2208 case Legal: 2209 // Input is legal? Just do extend all the way to the larger type. 2210 Result = LegalizeOp(Node->getOperand(0)); 2211 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2212 break; 2213 case Promote: 2214 // Promote the reg if it's smaller. 2215 Result = PromoteOp(Node->getOperand(0)); 2216 // The high bits are not guaranteed to be anything. Insert an extend. 2217 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2218 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2219 DAG.getValueType(Node->getOperand(0).getValueType())); 2220 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2221 Result = DAG.getZeroExtendInReg(Result, 2222 Node->getOperand(0).getValueType()); 2223 break; 2224 } 2225 break; 2226 2227 case ISD::FP_EXTEND: 2228 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2229 case ISD::FP_ROUND: 2230 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2231 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2232 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2233 case Legal: 2234 // Input is legal? Do an FP_ROUND_INREG. 2235 Result = LegalizeOp(Node->getOperand(0)); 2236 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2237 DAG.getValueType(VT)); 2238 break; 2239 } 2240 break; 2241 2242 case ISD::SINT_TO_FP: 2243 case ISD::UINT_TO_FP: 2244 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2245 case Legal: 2246 Result = LegalizeOp(Node->getOperand(0)); 2247 // No extra round required here. 2248 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2249 break; 2250 2251 case Promote: 2252 Result = PromoteOp(Node->getOperand(0)); 2253 if (Node->getOpcode() == ISD::SINT_TO_FP) 2254 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2255 Result, 2256 DAG.getValueType(Node->getOperand(0).getValueType())); 2257 else 2258 Result = DAG.getZeroExtendInReg(Result, 2259 Node->getOperand(0).getValueType()); 2260 // No extra round required here. 2261 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2262 break; 2263 case Expand: 2264 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2265 Node->getOperand(0)); 2266 // Round if we cannot tolerate excess precision. 2267 if (NoExcessFPPrecision) 2268 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2269 DAG.getValueType(VT)); 2270 break; 2271 } 2272 break; 2273 2274 case ISD::FP_TO_SINT: 2275 case ISD::FP_TO_UINT: 2276 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2277 case Legal: 2278 Tmp1 = LegalizeOp(Node->getOperand(0)); 2279 break; 2280 case Promote: 2281 // The input result is prerounded, so we don't have to do anything 2282 // special. 2283 Tmp1 = PromoteOp(Node->getOperand(0)); 2284 break; 2285 case Expand: 2286 assert(0 && "not implemented"); 2287 } 2288 // If we're promoting a UINT to a larger size, check to see if the new node 2289 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2290 // we can use that instead. This allows us to generate better code for 2291 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2292 // legal, such as PowerPC. 2293 if (Node->getOpcode() == ISD::FP_TO_UINT && 2294 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2295 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2296 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2297 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2298 } else { 2299 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2300 } 2301 break; 2302 2303 case ISD::FABS: 2304 case ISD::FNEG: 2305 Tmp1 = PromoteOp(Node->getOperand(0)); 2306 assert(Tmp1.getValueType() == NVT); 2307 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2308 // NOTE: we do not have to do any extra rounding here for 2309 // NoExcessFPPrecision, because we know the input will have the appropriate 2310 // precision, and these operations don't modify precision at all. 2311 break; 2312 2313 case ISD::FSQRT: 2314 case ISD::FSIN: 2315 case ISD::FCOS: 2316 Tmp1 = PromoteOp(Node->getOperand(0)); 2317 assert(Tmp1.getValueType() == NVT); 2318 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2319 if(NoExcessFPPrecision) 2320 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2321 DAG.getValueType(VT)); 2322 break; 2323 2324 case ISD::AND: 2325 case ISD::OR: 2326 case ISD::XOR: 2327 case ISD::ADD: 2328 case ISD::SUB: 2329 case ISD::MUL: 2330 // The input may have strange things in the top bits of the registers, but 2331 // these operations don't care. They may have weird bits going out, but 2332 // that too is okay if they are integer operations. 2333 Tmp1 = PromoteOp(Node->getOperand(0)); 2334 Tmp2 = PromoteOp(Node->getOperand(1)); 2335 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2336 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2337 break; 2338 case ISD::FADD: 2339 case ISD::FSUB: 2340 case ISD::FMUL: 2341 // The input may have strange things in the top bits of the registers, but 2342 // these operations don't care. 2343 Tmp1 = PromoteOp(Node->getOperand(0)); 2344 Tmp2 = PromoteOp(Node->getOperand(1)); 2345 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2346 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2347 2348 // Floating point operations will give excess precision that we may not be 2349 // able to tolerate. If we DO allow excess precision, just leave it, 2350 // otherwise excise it. 2351 // FIXME: Why would we need to round FP ops more than integer ones? 2352 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2353 if (NoExcessFPPrecision) 2354 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2355 DAG.getValueType(VT)); 2356 break; 2357 2358 case ISD::SDIV: 2359 case ISD::SREM: 2360 // These operators require that their input be sign extended. 2361 Tmp1 = PromoteOp(Node->getOperand(0)); 2362 Tmp2 = PromoteOp(Node->getOperand(1)); 2363 if (MVT::isInteger(NVT)) { 2364 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2365 DAG.getValueType(VT)); 2366 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2367 DAG.getValueType(VT)); 2368 } 2369 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2370 2371 // Perform FP_ROUND: this is probably overly pessimistic. 2372 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2373 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2374 DAG.getValueType(VT)); 2375 break; 2376 case ISD::FDIV: 2377 case ISD::FREM: 2378 // These operators require that their input be fp extended. 2379 Tmp1 = PromoteOp(Node->getOperand(0)); 2380 Tmp2 = PromoteOp(Node->getOperand(1)); 2381 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2382 2383 // Perform FP_ROUND: this is probably overly pessimistic. 2384 if (NoExcessFPPrecision) 2385 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2386 DAG.getValueType(VT)); 2387 break; 2388 2389 case ISD::UDIV: 2390 case ISD::UREM: 2391 // These operators require that their input be zero extended. 2392 Tmp1 = PromoteOp(Node->getOperand(0)); 2393 Tmp2 = PromoteOp(Node->getOperand(1)); 2394 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2395 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2396 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2397 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2398 break; 2399 2400 case ISD::SHL: 2401 Tmp1 = PromoteOp(Node->getOperand(0)); 2402 Tmp2 = LegalizeOp(Node->getOperand(1)); 2403 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2404 break; 2405 case ISD::SRA: 2406 // The input value must be properly sign extended. 2407 Tmp1 = PromoteOp(Node->getOperand(0)); 2408 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2409 DAG.getValueType(VT)); 2410 Tmp2 = LegalizeOp(Node->getOperand(1)); 2411 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2412 break; 2413 case ISD::SRL: 2414 // The input value must be properly zero extended. 2415 Tmp1 = PromoteOp(Node->getOperand(0)); 2416 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2417 Tmp2 = LegalizeOp(Node->getOperand(1)); 2418 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2419 break; 2420 case ISD::LOAD: 2421 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2422 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2423 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2424 Node->getOperand(2), VT); 2425 // Remember that we legalized the chain. 2426 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2427 break; 2428 case ISD::SEXTLOAD: 2429 case ISD::ZEXTLOAD: 2430 case ISD::EXTLOAD: 2431 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2432 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2433 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2434 Node->getOperand(2), 2435 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2436 // Remember that we legalized the chain. 2437 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2438 break; 2439 case ISD::SELECT: 2440 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2441 case Expand: assert(0 && "It's impossible to expand bools"); 2442 case Legal: 2443 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2444 break; 2445 case Promote: 2446 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2447 break; 2448 } 2449 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2450 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2451 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2452 break; 2453 case ISD::SELECT_CC: 2454 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2455 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2456 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2457 Node->getOperand(1), Tmp2, Tmp3, 2458 Node->getOperand(4)); 2459 break; 2460 case ISD::TAILCALL: 2461 case ISD::CALL: { 2462 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2463 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2464 2465 std::vector<SDOperand> Ops; 2466 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2467 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2468 2469 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2470 "Can only promote single result calls"); 2471 std::vector<MVT::ValueType> RetTyVTs; 2472 RetTyVTs.reserve(2); 2473 RetTyVTs.push_back(NVT); 2474 RetTyVTs.push_back(MVT::Other); 2475 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2476 Node->getOpcode() == ISD::TAILCALL); 2477 Result = SDOperand(NC, 0); 2478 2479 // Insert the new chain mapping. 2480 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2481 break; 2482 } 2483 case ISD::CTPOP: 2484 case ISD::CTTZ: 2485 case ISD::CTLZ: 2486 Tmp1 = Node->getOperand(0); 2487 //Zero extend the argument 2488 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2489 // Perform the larger operation, then subtract if needed. 2490 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2491 switch(Node->getOpcode()) 2492 { 2493 case ISD::CTPOP: 2494 Result = Tmp1; 2495 break; 2496 case ISD::CTTZ: 2497 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2498 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2499 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2500 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2501 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2502 break; 2503 case ISD::CTLZ: 2504 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2505 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2506 DAG.getConstant(getSizeInBits(NVT) - 2507 getSizeInBits(VT), NVT)); 2508 break; 2509 } 2510 break; 2511 } 2512 2513 assert(Result.Val && "Didn't set a result!"); 2514 AddPromotedOperand(Op, Result); 2515 return Result; 2516} 2517 2518/// ExpandAddSub - Find a clever way to expand this add operation into 2519/// subcomponents. 2520void SelectionDAGLegalize:: 2521ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2522 SDOperand &Lo, SDOperand &Hi) { 2523 // Expand the subcomponents. 2524 SDOperand LHSL, LHSH, RHSL, RHSH; 2525 ExpandOp(LHS, LHSL, LHSH); 2526 ExpandOp(RHS, RHSL, RHSH); 2527 2528 std::vector<SDOperand> Ops; 2529 Ops.push_back(LHSL); 2530 Ops.push_back(LHSH); 2531 Ops.push_back(RHSL); 2532 Ops.push_back(RHSH); 2533 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2534 Lo = DAG.getNode(NodeOp, VTs, Ops); 2535 Hi = Lo.getValue(1); 2536} 2537 2538void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2539 SDOperand Op, SDOperand Amt, 2540 SDOperand &Lo, SDOperand &Hi) { 2541 // Expand the subcomponents. 2542 SDOperand LHSL, LHSH; 2543 ExpandOp(Op, LHSL, LHSH); 2544 2545 std::vector<SDOperand> Ops; 2546 Ops.push_back(LHSL); 2547 Ops.push_back(LHSH); 2548 Ops.push_back(Amt); 2549 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2550 Lo = DAG.getNode(NodeOp, VTs, Ops); 2551 Hi = Lo.getValue(1); 2552} 2553 2554 2555/// ExpandShift - Try to find a clever way to expand this shift operation out to 2556/// smaller elements. If we can't find a way that is more efficient than a 2557/// libcall on this target, return false. Otherwise, return true with the 2558/// low-parts expanded into Lo and Hi. 2559bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2560 SDOperand &Lo, SDOperand &Hi) { 2561 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2562 "This is not a shift!"); 2563 2564 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2565 SDOperand ShAmt = LegalizeOp(Amt); 2566 MVT::ValueType ShTy = ShAmt.getValueType(); 2567 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2568 unsigned NVTBits = MVT::getSizeInBits(NVT); 2569 2570 // Handle the case when Amt is an immediate. Other cases are currently broken 2571 // and are disabled. 2572 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2573 unsigned Cst = CN->getValue(); 2574 // Expand the incoming operand to be shifted, so that we have its parts 2575 SDOperand InL, InH; 2576 ExpandOp(Op, InL, InH); 2577 switch(Opc) { 2578 case ISD::SHL: 2579 if (Cst > VTBits) { 2580 Lo = DAG.getConstant(0, NVT); 2581 Hi = DAG.getConstant(0, NVT); 2582 } else if (Cst > NVTBits) { 2583 Lo = DAG.getConstant(0, NVT); 2584 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2585 } else if (Cst == NVTBits) { 2586 Lo = DAG.getConstant(0, NVT); 2587 Hi = InL; 2588 } else { 2589 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2590 Hi = DAG.getNode(ISD::OR, NVT, 2591 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2592 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2593 } 2594 return true; 2595 case ISD::SRL: 2596 if (Cst > VTBits) { 2597 Lo = DAG.getConstant(0, NVT); 2598 Hi = DAG.getConstant(0, NVT); 2599 } else if (Cst > NVTBits) { 2600 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2601 Hi = DAG.getConstant(0, NVT); 2602 } else if (Cst == NVTBits) { 2603 Lo = InH; 2604 Hi = DAG.getConstant(0, NVT); 2605 } else { 2606 Lo = DAG.getNode(ISD::OR, NVT, 2607 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2608 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2609 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2610 } 2611 return true; 2612 case ISD::SRA: 2613 if (Cst > VTBits) { 2614 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2615 DAG.getConstant(NVTBits-1, ShTy)); 2616 } else if (Cst > NVTBits) { 2617 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2618 DAG.getConstant(Cst-NVTBits, ShTy)); 2619 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2620 DAG.getConstant(NVTBits-1, ShTy)); 2621 } else if (Cst == NVTBits) { 2622 Lo = InH; 2623 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2624 DAG.getConstant(NVTBits-1, ShTy)); 2625 } else { 2626 Lo = DAG.getNode(ISD::OR, NVT, 2627 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2628 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2629 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2630 } 2631 return true; 2632 } 2633 } 2634 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2635 // so disable it for now. Currently targets are handling this via SHL_PARTS 2636 // and friends. 2637 return false; 2638 2639 // If we have an efficient select operation (or if the selects will all fold 2640 // away), lower to some complex code, otherwise just emit the libcall. 2641 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2642 return false; 2643 2644 SDOperand InL, InH; 2645 ExpandOp(Op, InL, InH); 2646 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2647 DAG.getConstant(NVTBits, ShTy), ShAmt); 2648 2649 // Compare the unmasked shift amount against 32. 2650 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2651 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2652 2653 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2654 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2655 DAG.getConstant(NVTBits-1, ShTy)); 2656 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2657 DAG.getConstant(NVTBits-1, ShTy)); 2658 } 2659 2660 if (Opc == ISD::SHL) { 2661 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2662 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2663 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2664 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2665 2666 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2667 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2668 } else { 2669 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2670 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2671 DAG.getConstant(32, ShTy), 2672 ISD::SETEQ), 2673 DAG.getConstant(0, NVT), 2674 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2675 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2676 HiLoPart, 2677 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2678 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2679 2680 SDOperand HiPart; 2681 if (Opc == ISD::SRA) 2682 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2683 DAG.getConstant(NVTBits-1, ShTy)); 2684 else 2685 HiPart = DAG.getConstant(0, NVT); 2686 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2687 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2688 } 2689 return true; 2690} 2691 2692/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2693/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2694/// Found. 2695static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2696 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2697 2698 // If we found an CALLSEQ_START, we already know this node occurs later 2699 // than the Found node. Just remember this node and return. 2700 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2701 Found = Node; 2702 return; 2703 } 2704 2705 // Otherwise, scan the operands of Node to see if any of them is a call. 2706 assert(Node->getNumOperands() != 0 && 2707 "All leaves should have depth equal to the entry node!"); 2708 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2709 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2710 2711 // Tail recurse for the last iteration. 2712 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2713 Found); 2714} 2715 2716 2717/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2718/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2719/// than Found. 2720static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2721 std::set<SDNode*> &Visited) { 2722 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2723 !Visited.insert(Node).second) return; 2724 2725 // If we found an CALLSEQ_END, we already know this node occurs earlier 2726 // than the Found node. Just remember this node and return. 2727 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2728 Found = Node; 2729 return; 2730 } 2731 2732 // Otherwise, scan the operands of Node to see if any of them is a call. 2733 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2734 if (UI == E) return; 2735 for (--E; UI != E; ++UI) 2736 FindEarliestCallSeqEnd(*UI, Found, Visited); 2737 2738 // Tail recurse for the last iteration. 2739 FindEarliestCallSeqEnd(*UI, Found, Visited); 2740} 2741 2742/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2743/// find the CALLSEQ_END node that terminates the call sequence. 2744static SDNode *FindCallSeqEnd(SDNode *Node) { 2745 if (Node->getOpcode() == ISD::CALLSEQ_END) 2746 return Node; 2747 if (Node->use_empty()) 2748 return 0; // No CallSeqEnd 2749 2750 SDOperand TheChain(Node, Node->getNumValues()-1); 2751 if (TheChain.getValueType() != MVT::Other) 2752 TheChain = SDOperand(Node, 0); 2753 if (TheChain.getValueType() != MVT::Other) 2754 return 0; 2755 2756 for (SDNode::use_iterator UI = Node->use_begin(), 2757 E = Node->use_end(); UI != E; ++UI) { 2758 2759 // Make sure to only follow users of our token chain. 2760 SDNode *User = *UI; 2761 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2762 if (User->getOperand(i) == TheChain) 2763 if (SDNode *Result = FindCallSeqEnd(User)) 2764 return Result; 2765 } 2766 return 0; 2767} 2768 2769/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2770/// find the CALLSEQ_START node that initiates the call sequence. 2771static SDNode *FindCallSeqStart(SDNode *Node) { 2772 assert(Node && "Didn't find callseq_start for a call??"); 2773 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2774 2775 assert(Node->getOperand(0).getValueType() == MVT::Other && 2776 "Node doesn't have a token chain argument!"); 2777 return FindCallSeqStart(Node->getOperand(0).Val); 2778} 2779 2780 2781/// FindInputOutputChains - If we are replacing an operation with a call we need 2782/// to find the call that occurs before and the call that occurs after it to 2783/// properly serialize the calls in the block. The returned operand is the 2784/// input chain value for the new call (e.g. the entry node or the previous 2785/// call), and OutChain is set to be the chain node to update to point to the 2786/// end of the call chain. 2787static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2788 SDOperand Entry) { 2789 SDNode *LatestCallSeqStart = Entry.Val; 2790 SDNode *LatestCallSeqEnd = 0; 2791 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 2792 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2793 2794 // It is possible that no ISD::CALLSEQ_START was found because there is no 2795 // previous call in the function. LatestCallStackDown may in that case be 2796 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2797 // unless LatestCallStackDown is an CALLSEQ_START. 2798 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2799 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2800 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2801 } else { 2802 LatestCallSeqEnd = Entry.Val; 2803 } 2804 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2805 2806 // Finally, find the first call that this must come before, first we find the 2807 // CallSeqEnd that ends the call. 2808 OutChain = 0; 2809 std::set<SDNode*> Visited; 2810 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2811 2812 // If we found one, translate from the adj up to the callseq_start. 2813 if (OutChain) 2814 OutChain = FindCallSeqStart(OutChain); 2815 2816 return SDOperand(LatestCallSeqEnd, 0); 2817} 2818 2819/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2820void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2821 SDNode *OutChain) { 2822 // Nothing to splice it into? 2823 if (OutChain == 0) return; 2824 2825 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2826 //OutChain->dump(); 2827 2828 // Form a token factor node merging the old inval and the new inval. 2829 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2830 OutChain->getOperand(0)); 2831 // Change the node to refer to the new token. 2832 OutChain->setAdjCallChain(InToken); 2833} 2834 2835 2836// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2837// does not fit into a register, return the lo part and set the hi part to the 2838// by-reg argument. If it does fit into a single register, return the result 2839// and leave the Hi part unset. 2840SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2841 SDOperand &Hi) { 2842 SDNode *OutChain; 2843 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2844 DAG.getEntryNode()); 2845 if (InChain.Val == 0) 2846 InChain = DAG.getEntryNode(); 2847 2848 TargetLowering::ArgListTy Args; 2849 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2850 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2851 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2852 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2853 } 2854 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2855 2856 // Splice the libcall in wherever FindInputOutputChains tells us to. 2857 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2858 std::pair<SDOperand,SDOperand> CallInfo = 2859 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2860 Callee, Args, DAG); 2861 2862 SDOperand Result; 2863 switch (getTypeAction(CallInfo.first.getValueType())) { 2864 default: assert(0 && "Unknown thing"); 2865 case Legal: 2866 Result = CallInfo.first; 2867 break; 2868 case Promote: 2869 assert(0 && "Cannot promote this yet!"); 2870 case Expand: 2871 ExpandOp(CallInfo.first, Result, Hi); 2872 CallInfo.second = LegalizeOp(CallInfo.second); 2873 break; 2874 } 2875 2876 SpliceCallInto(CallInfo.second, OutChain); 2877 NeedsAnotherIteration = true; 2878 return Result; 2879} 2880 2881 2882/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 2883/// destination type is legal. 2884SDOperand SelectionDAGLegalize:: 2885ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 2886 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 2887 assert(getTypeAction(Source.getValueType()) == Expand && 2888 "This is not an expansion!"); 2889 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 2890 2891 if (!isSigned) { 2892 assert(Source.getValueType() == MVT::i64 && 2893 "This only works for 64-bit -> FP"); 2894 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 2895 // incoming integer is set. To handle this, we dynamically test to see if 2896 // it is set, and, if so, add a fudge factor. 2897 SDOperand Lo, Hi; 2898 ExpandOp(Source, Lo, Hi); 2899 2900 // If this is unsigned, and not supported, first perform the conversion to 2901 // signed, then adjust the result if the sign bit is set. 2902 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 2903 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 2904 2905 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 2906 DAG.getConstant(0, Hi.getValueType()), 2907 ISD::SETLT); 2908 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 2909 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 2910 SignSet, Four, Zero); 2911 uint64_t FF = 0x5f800000ULL; 2912 if (TLI.isLittleEndian()) FF <<= 32; 2913 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 2914 2915 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2916 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 2917 SDOperand FudgeInReg; 2918 if (DestTy == MVT::f32) 2919 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 2920 DAG.getSrcValue(NULL)); 2921 else { 2922 assert(DestTy == MVT::f64 && "Unexpected conversion"); 2923 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 2924 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 2925 } 2926 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 2927 } 2928 2929 // Check to see if the target has a custom way to lower this. If so, use it. 2930 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 2931 default: assert(0 && "This action not implemented for this operation!"); 2932 case TargetLowering::Legal: 2933 case TargetLowering::Expand: 2934 break; // This case is handled below. 2935 case TargetLowering::Custom: { 2936 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 2937 Source), DAG); 2938 if (NV.Val) 2939 return LegalizeOp(NV); 2940 break; // The target decided this was legal after all 2941 } 2942 } 2943 2944 // Expand the source, then glue it back together for the call. We must expand 2945 // the source in case it is shared (this pass of legalize must traverse it). 2946 SDOperand SrcLo, SrcHi; 2947 ExpandOp(Source, SrcLo, SrcHi); 2948 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 2949 2950 SDNode *OutChain = 0; 2951 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 2952 DAG.getEntryNode()); 2953 const char *FnName = 0; 2954 if (DestTy == MVT::f32) 2955 FnName = "__floatdisf"; 2956 else { 2957 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 2958 FnName = "__floatdidf"; 2959 } 2960 2961 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 2962 2963 TargetLowering::ArgListTy Args; 2964 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 2965 2966 Args.push_back(std::make_pair(Source, ArgTy)); 2967 2968 // We don't care about token chains for libcalls. We just use the entry 2969 // node as our input and ignore the output chain. This allows us to place 2970 // calls wherever we need them to satisfy data dependences. 2971 const Type *RetTy = MVT::getTypeForValueType(DestTy); 2972 2973 std::pair<SDOperand,SDOperand> CallResult = 2974 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 2975 Callee, Args, DAG); 2976 2977 SpliceCallInto(CallResult.second, OutChain); 2978 return CallResult.first; 2979} 2980 2981 2982 2983/// ExpandOp - Expand the specified SDOperand into its two component pieces 2984/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 2985/// LegalizeNodes map is filled in for any results that are not expanded, the 2986/// ExpandedNodes map is filled in for any results that are expanded, and the 2987/// Lo/Hi values are returned. 2988void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 2989 MVT::ValueType VT = Op.getValueType(); 2990 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2991 SDNode *Node = Op.Val; 2992 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 2993 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 2994 assert(MVT::isInteger(NVT) && NVT < VT && 2995 "Cannot expand to FP value or to larger int value!"); 2996 2997 // See if we already expanded it. 2998 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 2999 = ExpandedNodes.find(Op); 3000 if (I != ExpandedNodes.end()) { 3001 Lo = I->second.first; 3002 Hi = I->second.second; 3003 return; 3004 } 3005 3006 // Expanding to multiple registers needs to perform an optimization step, and 3007 // is not careful to avoid operations the target does not support. Make sure 3008 // that all generated operations are legalized in the next iteration. 3009 NeedsAnotherIteration = true; 3010 3011 switch (Node->getOpcode()) { 3012 case ISD::CopyFromReg: 3013 assert(0 && "CopyFromReg must be legal!"); 3014 default: 3015 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3016 assert(0 && "Do not know how to expand this operator!"); 3017 abort(); 3018 case ISD::UNDEF: 3019 Lo = DAG.getNode(ISD::UNDEF, NVT); 3020 Hi = DAG.getNode(ISD::UNDEF, NVT); 3021 break; 3022 case ISD::Constant: { 3023 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3024 Lo = DAG.getConstant(Cst, NVT); 3025 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3026 break; 3027 } 3028 3029 case ISD::BUILD_PAIR: 3030 // Legalize both operands. FIXME: in the future we should handle the case 3031 // where the two elements are not legal. 3032 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3033 Lo = LegalizeOp(Node->getOperand(0)); 3034 Hi = LegalizeOp(Node->getOperand(1)); 3035 break; 3036 3037 case ISD::CTPOP: 3038 ExpandOp(Node->getOperand(0), Lo, Hi); 3039 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3040 DAG.getNode(ISD::CTPOP, NVT, Lo), 3041 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3042 Hi = DAG.getConstant(0, NVT); 3043 break; 3044 3045 case ISD::CTLZ: { 3046 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3047 ExpandOp(Node->getOperand(0), Lo, Hi); 3048 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3049 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3050 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3051 ISD::SETNE); 3052 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3053 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3054 3055 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3056 Hi = DAG.getConstant(0, NVT); 3057 break; 3058 } 3059 3060 case ISD::CTTZ: { 3061 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3062 ExpandOp(Node->getOperand(0), Lo, Hi); 3063 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3064 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3065 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3066 ISD::SETNE); 3067 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3068 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3069 3070 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3071 Hi = DAG.getConstant(0, NVT); 3072 break; 3073 } 3074 3075 case ISD::LOAD: { 3076 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3077 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3078 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3079 3080 // Increment the pointer to the other half. 3081 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3082 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3083 getIntPtrConstant(IncrementSize)); 3084 //Is this safe? declaring that the two parts of the split load 3085 //are from the same instruction? 3086 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3087 3088 // Build a factor node to remember that this load is independent of the 3089 // other one. 3090 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3091 Hi.getValue(1)); 3092 3093 // Remember that we legalized the chain. 3094 AddLegalizedOperand(Op.getValue(1), TF); 3095 if (!TLI.isLittleEndian()) 3096 std::swap(Lo, Hi); 3097 break; 3098 } 3099 case ISD::TAILCALL: 3100 case ISD::CALL: { 3101 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3102 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3103 3104 bool Changed = false; 3105 std::vector<SDOperand> Ops; 3106 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3107 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3108 Changed |= Ops.back() != Node->getOperand(i); 3109 } 3110 3111 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3112 "Can only expand a call once so far, not i64 -> i16!"); 3113 3114 std::vector<MVT::ValueType> RetTyVTs; 3115 RetTyVTs.reserve(3); 3116 RetTyVTs.push_back(NVT); 3117 RetTyVTs.push_back(NVT); 3118 RetTyVTs.push_back(MVT::Other); 3119 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3120 Node->getOpcode() == ISD::TAILCALL); 3121 Lo = SDOperand(NC, 0); 3122 Hi = SDOperand(NC, 1); 3123 3124 // Insert the new chain mapping. 3125 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3126 break; 3127 } 3128 case ISD::AND: 3129 case ISD::OR: 3130 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3131 SDOperand LL, LH, RL, RH; 3132 ExpandOp(Node->getOperand(0), LL, LH); 3133 ExpandOp(Node->getOperand(1), RL, RH); 3134 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3135 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3136 break; 3137 } 3138 case ISD::SELECT: { 3139 SDOperand C, LL, LH, RL, RH; 3140 3141 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3142 case Expand: assert(0 && "It's impossible to expand bools"); 3143 case Legal: 3144 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3145 break; 3146 case Promote: 3147 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3148 break; 3149 } 3150 ExpandOp(Node->getOperand(1), LL, LH); 3151 ExpandOp(Node->getOperand(2), RL, RH); 3152 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3153 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3154 break; 3155 } 3156 case ISD::SELECT_CC: { 3157 SDOperand TL, TH, FL, FH; 3158 ExpandOp(Node->getOperand(2), TL, TH); 3159 ExpandOp(Node->getOperand(3), FL, FH); 3160 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3161 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3162 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3163 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3164 Lo = LegalizeOp(Lo); 3165 Hi = LegalizeOp(Hi); 3166 break; 3167 } 3168 case ISD::SEXTLOAD: { 3169 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3170 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3171 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3172 3173 if (EVT == NVT) 3174 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3175 else 3176 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3177 EVT); 3178 3179 // Remember that we legalized the chain. 3180 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3181 3182 // The high part is obtained by SRA'ing all but one of the bits of the lo 3183 // part. 3184 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3185 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3186 TLI.getShiftAmountTy())); 3187 Lo = LegalizeOp(Lo); 3188 Hi = LegalizeOp(Hi); 3189 break; 3190 } 3191 case ISD::ZEXTLOAD: { 3192 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3193 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3194 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3195 3196 if (EVT == NVT) 3197 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3198 else 3199 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3200 EVT); 3201 3202 // Remember that we legalized the chain. 3203 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3204 3205 // The high part is just a zero. 3206 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3207 Lo = LegalizeOp(Lo); 3208 break; 3209 } 3210 case ISD::EXTLOAD: { 3211 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3212 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3213 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3214 3215 if (EVT == NVT) 3216 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3217 else 3218 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3219 EVT); 3220 3221 // Remember that we legalized the chain. 3222 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3223 3224 // The high part is undefined. 3225 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3226 Lo = LegalizeOp(Lo); 3227 break; 3228 } 3229 case ISD::ANY_EXTEND: { 3230 SDOperand In; 3231 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3232 case Expand: assert(0 && "expand-expand not implemented yet!"); 3233 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3234 case Promote: 3235 In = PromoteOp(Node->getOperand(0)); 3236 break; 3237 } 3238 3239 // The low part is any extension of the input (which degenerates to a copy). 3240 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3241 // The high part is undefined. 3242 Hi = DAG.getNode(ISD::UNDEF, NVT); 3243 break; 3244 } 3245 case ISD::SIGN_EXTEND: { 3246 SDOperand In; 3247 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3248 case Expand: assert(0 && "expand-expand not implemented yet!"); 3249 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3250 case Promote: 3251 In = PromoteOp(Node->getOperand(0)); 3252 // Emit the appropriate sign_extend_inreg to get the value we want. 3253 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3254 DAG.getValueType(Node->getOperand(0).getValueType())); 3255 break; 3256 } 3257 3258 // The low part is just a sign extension of the input (which degenerates to 3259 // a copy). 3260 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3261 3262 // The high part is obtained by SRA'ing all but one of the bits of the lo 3263 // part. 3264 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3265 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3266 TLI.getShiftAmountTy())); 3267 break; 3268 } 3269 case ISD::ZERO_EXTEND: { 3270 SDOperand In; 3271 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3272 case Expand: assert(0 && "expand-expand not implemented yet!"); 3273 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3274 case Promote: 3275 In = PromoteOp(Node->getOperand(0)); 3276 // Emit the appropriate zero_extend_inreg to get the value we want. 3277 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3278 break; 3279 } 3280 3281 // The low part is just a zero extension of the input (which degenerates to 3282 // a copy). 3283 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3284 3285 // The high part is just a zero. 3286 Hi = DAG.getConstant(0, NVT); 3287 break; 3288 } 3289 // These operators cannot be expanded directly, emit them as calls to 3290 // library functions. 3291 case ISD::FP_TO_SINT: 3292 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3293 SDOperand Op; 3294 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3295 case Expand: assert(0 && "cannot expand FP!"); 3296 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3297 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3298 } 3299 3300 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3301 3302 // Now that the custom expander is done, expand the result, which is still 3303 // VT. 3304 if (Op.Val) { 3305 ExpandOp(Op, Lo, Hi); 3306 break; 3307 } 3308 } 3309 3310 if (Node->getOperand(0).getValueType() == MVT::f32) 3311 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3312 else 3313 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3314 break; 3315 3316 case ISD::FP_TO_UINT: 3317 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3318 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3319 LegalizeOp(Node->getOperand(0))); 3320 // Now that the custom expander is done, expand the result, which is still 3321 // VT. 3322 Op = TLI.LowerOperation(Op, DAG); 3323 if (Op.Val) { 3324 ExpandOp(Op, Lo, Hi); 3325 break; 3326 } 3327 } 3328 3329 if (Node->getOperand(0).getValueType() == MVT::f32) 3330 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3331 else 3332 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3333 break; 3334 3335 case ISD::SHL: 3336 // If the target wants custom lowering, do so. 3337 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3338 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3339 LegalizeOp(Node->getOperand(1))); 3340 Op = TLI.LowerOperation(Op, DAG); 3341 if (Op.Val) { 3342 // Now that the custom expander is done, expand the result, which is 3343 // still VT. 3344 ExpandOp(Op, Lo, Hi); 3345 break; 3346 } 3347 } 3348 3349 // If we can emit an efficient shift operation, do so now. 3350 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3351 break; 3352 3353 // If this target supports SHL_PARTS, use it. 3354 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3355 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3356 Lo, Hi); 3357 break; 3358 } 3359 3360 // Otherwise, emit a libcall. 3361 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3362 break; 3363 3364 case ISD::SRA: 3365 // If the target wants custom lowering, do so. 3366 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3367 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3368 LegalizeOp(Node->getOperand(1))); 3369 Op = TLI.LowerOperation(Op, DAG); 3370 if (Op.Val) { 3371 // Now that the custom expander is done, expand the result, which is 3372 // still VT. 3373 ExpandOp(Op, Lo, Hi); 3374 break; 3375 } 3376 } 3377 3378 // If we can emit an efficient shift operation, do so now. 3379 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3380 break; 3381 3382 // If this target supports SRA_PARTS, use it. 3383 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3384 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3385 Lo, Hi); 3386 break; 3387 } 3388 3389 // Otherwise, emit a libcall. 3390 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3391 break; 3392 case ISD::SRL: 3393 // If the target wants custom lowering, do so. 3394 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3395 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3396 LegalizeOp(Node->getOperand(1))); 3397 Op = TLI.LowerOperation(Op, DAG); 3398 if (Op.Val) { 3399 // Now that the custom expander is done, expand the result, which is 3400 // still VT. 3401 ExpandOp(Op, Lo, Hi); 3402 break; 3403 } 3404 } 3405 3406 // If we can emit an efficient shift operation, do so now. 3407 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3408 break; 3409 3410 // If this target supports SRL_PARTS, use it. 3411 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3412 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3413 Lo, Hi); 3414 break; 3415 } 3416 3417 // Otherwise, emit a libcall. 3418 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3419 break; 3420 3421 case ISD::ADD: 3422 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3423 Lo, Hi); 3424 break; 3425 case ISD::SUB: 3426 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3427 Lo, Hi); 3428 break; 3429 case ISD::MUL: { 3430 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3431 SDOperand LL, LH, RL, RH; 3432 ExpandOp(Node->getOperand(0), LL, LH); 3433 ExpandOp(Node->getOperand(1), RL, RH); 3434 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3435 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3436 // extended the sign bit of the low half through the upper half, and if so 3437 // emit a MULHS instead of the alternate sequence that is valid for any 3438 // i64 x i64 multiply. 3439 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3440 // is RH an extension of the sign bit of RL? 3441 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3442 RH.getOperand(1).getOpcode() == ISD::Constant && 3443 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3444 // is LH an extension of the sign bit of LL? 3445 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3446 LH.getOperand(1).getOpcode() == ISD::Constant && 3447 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3448 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3449 } else { 3450 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3451 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3452 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3453 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3454 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3455 } 3456 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3457 } else { 3458 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3459 } 3460 break; 3461 } 3462 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3463 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3464 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3465 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3466 } 3467 3468 // Remember in a map if the values will be reused later. 3469 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3470 std::make_pair(Lo, Hi))).second; 3471 assert(isNew && "Value already expanded?!?"); 3472} 3473 3474 3475// SelectionDAG::Legalize - This is the entry point for the file. 3476// 3477void SelectionDAG::Legalize() { 3478 /// run - This is the main entry point to this class. 3479 /// 3480 SelectionDAGLegalize(*this).Run(); 3481} 3482 3483