LegalizeDAG.cpp revision 17495ded2595481ff1ba2aa9299b04f8397bc913
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38#ifndef NDEBUG 39static cl::opt<bool> 40ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 41 cl::desc("Pop up a window to show dags before legalize")); 42#else 43static const bool ViewLegalizeDAGs = 0; 44#endif 45 46//===----------------------------------------------------------------------===// 47/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 48/// hacks on it until the target machine can handle it. This involves 49/// eliminating value sizes the machine cannot handle (promoting small sizes to 50/// large sizes or splitting up large values into small values) as well as 51/// eliminating operations the machine cannot handle. 52/// 53/// This code also does a small amount of optimization and recognition of idioms 54/// as part of its processing. For example, if a target does not support a 55/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 56/// will attempt merge setcc and brc instructions into brcc's. 57/// 58namespace { 59class VISIBILITY_HIDDEN SelectionDAGLegalize { 60 TargetLowering &TLI; 61 SelectionDAG &DAG; 62 63 // Libcall insertion helpers. 64 65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 66 /// legalized. We use this to ensure that calls are properly serialized 67 /// against each other, including inserted libcalls. 68 SDOperand LastCALLSEQ_END; 69 70 /// IsLegalizingCall - This member is used *only* for purposes of providing 71 /// helpful assertions that a libcall isn't created while another call is 72 /// being legalized (which could lead to non-serialized call sequences). 73 bool IsLegalizingCall; 74 75 enum LegalizeAction { 76 Legal, // The target natively supports this operation. 77 Promote, // This operation should be executed in a larger type. 78 Expand // Try to expand this to other ops, otherwise use a libcall. 79 }; 80 81 /// ValueTypeActions - This is a bitvector that contains two bits for each 82 /// value type, where the two bits correspond to the LegalizeAction enum. 83 /// This can be queried with "getTypeAction(VT)". 84 TargetLowering::ValueTypeActionImpl ValueTypeActions; 85 86 /// LegalizedNodes - For nodes that are of legal width, and that have more 87 /// than one use, this map indicates what regularized operand to use. This 88 /// allows us to avoid legalizing the same thing more than once. 89 DenseMap<SDOperand, SDOperand> LegalizedNodes; 90 91 /// PromotedNodes - For nodes that are below legal width, and that have more 92 /// than one use, this map indicates what promoted value to use. This allows 93 /// us to avoid promoting the same thing more than once. 94 DenseMap<SDOperand, SDOperand> PromotedNodes; 95 96 /// ExpandedNodes - For nodes that need to be expanded this map indicates 97 /// which which operands are the expanded version of the input. This allows 98 /// us to avoid expanding the same node more than once. 99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 100 101 /// SplitNodes - For vector nodes that need to be split, this map indicates 102 /// which which operands are the split version of the input. This allows us 103 /// to avoid splitting the same node more than once. 104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 105 106 /// ScalarizedNodes - For nodes that need to be converted from vector types to 107 /// scalar types, this contains the mapping of ones we have already 108 /// processed to the result. 109 std::map<SDOperand, SDOperand> ScalarizedNodes; 110 111 void AddLegalizedOperand(SDOperand From, SDOperand To) { 112 LegalizedNodes.insert(std::make_pair(From, To)); 113 // If someone requests legalization of the new node, return itself. 114 if (From != To) 115 LegalizedNodes.insert(std::make_pair(To, To)); 116 } 117 void AddPromotedOperand(SDOperand From, SDOperand To) { 118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 119 assert(isNew && "Got into the map somehow?"); 120 // If someone requests legalization of the new node, return itself. 121 LegalizedNodes.insert(std::make_pair(To, To)); 122 } 123 124public: 125 126 SelectionDAGLegalize(SelectionDAG &DAG); 127 128 /// getTypeAction - Return how we should legalize values of this type, either 129 /// it is already legal or we need to expand it into multiple registers of 130 /// smaller integer type, or we need to promote it to a larger type. 131 LegalizeAction getTypeAction(MVT VT) const { 132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 133 } 134 135 /// isTypeLegal - Return true if this type is legal on this target. 136 /// 137 bool isTypeLegal(MVT VT) const { 138 return getTypeAction(VT) == Legal; 139 } 140 141 void LegalizeDAG(); 142 143private: 144 /// HandleOp - Legalize, Promote, or Expand the specified operand as 145 /// appropriate for its type. 146 void HandleOp(SDOperand Op); 147 148 /// LegalizeOp - We know that the specified value has a legal type. 149 /// Recursively ensure that the operands have legal types, then return the 150 /// result. 151 SDOperand LegalizeOp(SDOperand O); 152 153 /// UnrollVectorOp - We know that the given vector has a legal type, however 154 /// the operation it performs is not legal and is an operation that we have 155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 156 /// operating on each element individually. 157 SDOperand UnrollVectorOp(SDOperand O); 158 159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 161 /// is necessary to spill the vector being inserted into to memory, perform 162 /// the insert there, and then read the result back. 163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, 164 SDOperand Idx); 165 166 /// PromoteOp - Given an operation that produces a value in an invalid type, 167 /// promote it to compute the value into a larger type. The produced value 168 /// will have the correct bits for the low portion of the register, but no 169 /// guarantee is made about the top bits: it may be zero, sign-extended, or 170 /// garbage. 171 SDOperand PromoteOp(SDOperand O); 172 173 /// ExpandOp - Expand the specified SDOperand into its two component pieces 174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 175 /// the LegalizeNodes map is filled in for any results that are not expanded, 176 /// the ExpandedNodes map is filled in for any results that are expanded, and 177 /// the Lo/Hi values are returned. This applies to integer types and Vector 178 /// types. 179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 180 181 /// SplitVectorOp - Given an operand of vector type, break it down into 182 /// two smaller values. 183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 184 185 /// ScalarizeVectorOp - Given an operand of single-element vector type 186 /// (e.g. v1f32), convert it into the equivalent operation that returns a 187 /// scalar (e.g. f32) value. 188 SDOperand ScalarizeVectorOp(SDOperand O); 189 190 /// isShuffleLegal - Return true if a vector shuffle is legal with the 191 /// specified mask and type. Targets can specify exactly which masks they 192 /// support and the code generator is tasked with not creating illegal masks. 193 /// 194 /// Note that this will also return true for shuffles that are promoted to a 195 /// different type. 196 /// 197 /// If this is a legal shuffle, this method returns the (possibly promoted) 198 /// build_vector Mask. If it's not a legal shuffle, it returns null. 199 SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const; 200 201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 203 204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 205 206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 207 SDOperand &Hi); 208 SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source); 209 210 SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT); 211 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 212 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 213 SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT); 214 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned); 215 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned); 216 217 SDOperand ExpandBSWAP(SDOperand Op); 218 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 219 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 220 SDOperand &Lo, SDOperand &Hi); 221 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 222 SDOperand &Lo, SDOperand &Hi); 223 224 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 225 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 226}; 227} 228 229/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 230/// specified mask and type. Targets can specify exactly which masks they 231/// support and the code generator is tasked with not creating illegal masks. 232/// 233/// Note that this will also return true for shuffles that are promoted to a 234/// different type. 235SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const { 236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 237 default: return 0; 238 case TargetLowering::Legal: 239 case TargetLowering::Custom: 240 break; 241 case TargetLowering::Promote: { 242 // If this is promoted to a different type, convert the shuffle mask and 243 // ask if it is legal in the promoted type! 244 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 245 246 // If we changed # elements, change the shuffle mask. 247 unsigned NumEltsGrowth = 248 NVT.getVectorNumElements() / VT.getVectorNumElements(); 249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 250 if (NumEltsGrowth > 1) { 251 // Renumber the elements. 252 SmallVector<SDOperand, 8> Ops; 253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 254 SDOperand InOp = Mask.getOperand(i); 255 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 256 if (InOp.getOpcode() == ISD::UNDEF) 257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 258 else { 259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 261 } 262 } 263 } 264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 265 } 266 VT = NVT; 267 break; 268 } 269 } 270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 271} 272 273SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 274 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 275 ValueTypeActions(TLI.getValueTypeActions()) { 276 assert(MVT::LAST_VALUETYPE <= 32 && 277 "Too many value types for ValueTypeActions to hold!"); 278} 279 280/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 281/// contains all of a nodes operands before it contains the node. 282static void ComputeTopDownOrdering(SelectionDAG &DAG, 283 SmallVector<SDNode*, 64> &Order) { 284 285 DenseMap<SDNode*, unsigned> Visited; 286 std::vector<SDNode*> Worklist; 287 Worklist.reserve(128); 288 289 // Compute ordering from all of the leaves in the graphs, those (like the 290 // entry node) that have no operands. 291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 292 E = DAG.allnodes_end(); I != E; ++I) { 293 if (I->getNumOperands() == 0) { 294 Visited[I] = 0 - 1U; 295 Worklist.push_back(I); 296 } 297 } 298 299 while (!Worklist.empty()) { 300 SDNode *N = Worklist.back(); 301 Worklist.pop_back(); 302 303 if (++Visited[N] != N->getNumOperands()) 304 continue; // Haven't visited all operands yet 305 306 Order.push_back(N); 307 308 // Now that we have N in, add anything that uses it if all of their operands 309 // are now done. 310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 311 UI != E; ++UI) 312 Worklist.push_back(UI->getUser()); 313 } 314 315 assert(Order.size() == Visited.size() && 316 Order.size() == DAG.allnodes_size() && 317 "Error: DAG is cyclic!"); 318} 319 320 321void SelectionDAGLegalize::LegalizeDAG() { 322 LastCALLSEQ_END = DAG.getEntryNode(); 323 IsLegalizingCall = false; 324 325 // The legalize process is inherently a bottom-up recursive process (users 326 // legalize their uses before themselves). Given infinite stack space, we 327 // could just start legalizing on the root and traverse the whole graph. In 328 // practice however, this causes us to run out of stack space on large basic 329 // blocks. To avoid this problem, compute an ordering of the nodes where each 330 // node is only legalized after all of its operands are legalized. 331 SmallVector<SDNode*, 64> Order; 332 ComputeTopDownOrdering(DAG, Order); 333 334 for (unsigned i = 0, e = Order.size(); i != e; ++i) 335 HandleOp(SDOperand(Order[i], 0)); 336 337 // Finally, it's possible the root changed. Get the new root. 338 SDOperand OldRoot = DAG.getRoot(); 339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 340 DAG.setRoot(LegalizedNodes[OldRoot]); 341 342 ExpandedNodes.clear(); 343 LegalizedNodes.clear(); 344 PromotedNodes.clear(); 345 SplitNodes.clear(); 346 ScalarizedNodes.clear(); 347 348 // Remove dead nodes now. 349 DAG.RemoveDeadNodes(); 350} 351 352 353/// FindCallEndFromCallStart - Given a chained node that is part of a call 354/// sequence, find the CALLSEQ_END node that terminates the call sequence. 355static SDNode *FindCallEndFromCallStart(SDNode *Node) { 356 if (Node->getOpcode() == ISD::CALLSEQ_END) 357 return Node; 358 if (Node->use_empty()) 359 return 0; // No CallSeqEnd 360 361 // The chain is usually at the end. 362 SDOperand TheChain(Node, Node->getNumValues()-1); 363 if (TheChain.getValueType() != MVT::Other) { 364 // Sometimes it's at the beginning. 365 TheChain = SDOperand(Node, 0); 366 if (TheChain.getValueType() != MVT::Other) { 367 // Otherwise, hunt for it. 368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 369 if (Node->getValueType(i) == MVT::Other) { 370 TheChain = SDOperand(Node, i); 371 break; 372 } 373 374 // Otherwise, we walked into a node without a chain. 375 if (TheChain.getValueType() != MVT::Other) 376 return 0; 377 } 378 } 379 380 for (SDNode::use_iterator UI = Node->use_begin(), 381 E = Node->use_end(); UI != E; ++UI) { 382 383 // Make sure to only follow users of our token chain. 384 SDNode *User = UI->getUser(); 385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 386 if (User->getOperand(i) == TheChain) 387 if (SDNode *Result = FindCallEndFromCallStart(User)) 388 return Result; 389 } 390 return 0; 391} 392 393/// FindCallStartFromCallEnd - Given a chained node that is part of a call 394/// sequence, find the CALLSEQ_START node that initiates the call sequence. 395static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 396 assert(Node && "Didn't find callseq_start for a call??"); 397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 398 399 assert(Node->getOperand(0).getValueType() == MVT::Other && 400 "Node doesn't have a token chain argument!"); 401 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 402} 403 404/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 405/// see if any uses can reach Dest. If no dest operands can get to dest, 406/// legalize them, legalize ourself, and return false, otherwise, return true. 407/// 408/// Keep track of the nodes we fine that actually do lead to Dest in 409/// NodesLeadingTo. This avoids retraversing them exponential number of times. 410/// 411bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 413 if (N == Dest) return true; // N certainly leads to Dest :) 414 415 // If we've already processed this node and it does lead to Dest, there is no 416 // need to reprocess it. 417 if (NodesLeadingTo.count(N)) return true; 418 419 // If the first result of this node has been already legalized, then it cannot 420 // reach N. 421 switch (getTypeAction(N->getValueType(0))) { 422 case Legal: 423 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 424 break; 425 case Promote: 426 if (PromotedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 case Expand: 429 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 430 break; 431 } 432 433 // Okay, this node has not already been legalized. Check and legalize all 434 // operands. If none lead to Dest, then we can legalize this node. 435 bool OperandsLeadToDest = false; 436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 437 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 439 440 if (OperandsLeadToDest) { 441 NodesLeadingTo.insert(N); 442 return true; 443 } 444 445 // Okay, this node looks safe, legalize it and return false. 446 HandleOp(SDOperand(N, 0)); 447 return false; 448} 449 450/// HandleOp - Legalize, Promote, or Expand the specified operand as 451/// appropriate for its type. 452void SelectionDAGLegalize::HandleOp(SDOperand Op) { 453 MVT VT = Op.getValueType(); 454 switch (getTypeAction(VT)) { 455 default: assert(0 && "Bad type action!"); 456 case Legal: (void)LegalizeOp(Op); break; 457 case Promote: (void)PromoteOp(Op); break; 458 case Expand: 459 if (!VT.isVector()) { 460 // If this is an illegal scalar, expand it into its two component 461 // pieces. 462 SDOperand X, Y; 463 if (Op.getOpcode() == ISD::TargetConstant) 464 break; // Allow illegal target nodes. 465 ExpandOp(Op, X, Y); 466 } else if (VT.getVectorNumElements() == 1) { 467 // If this is an illegal single element vector, convert it to a 468 // scalar operation. 469 (void)ScalarizeVectorOp(Op); 470 } else { 471 // Otherwise, this is an illegal multiple element vector. 472 // Split it in half and legalize both parts. 473 SDOperand X, Y; 474 SplitVectorOp(Op, X, Y); 475 } 476 break; 477 } 478} 479 480/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 481/// a load from the constant pool. 482static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 483 SelectionDAG &DAG, TargetLowering &TLI) { 484 bool Extend = false; 485 486 // If a FP immediate is precise when represented as a float and if the 487 // target can do an extending load from float to double, we put it into 488 // the constant pool as a float, even if it's is statically typed as a 489 // double. This shrinks FP constants and canonicalizes them for targets where 490 // an FP extending load is the same cost as a normal load (such as on the x87 491 // fp stack or PPC FP unit). 492 MVT VT = CFP->getValueType(0); 493 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 494 if (!UseCP) { 495 if (VT!=MVT::f64 && VT!=MVT::f32) 496 assert(0 && "Invalid type expansion"); 497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 498 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 499 } 500 501 MVT OrigVT = VT; 502 MVT SVT = VT; 503 while (SVT != MVT::f32) { 504 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 505 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 506 // Only do this if the target has a native EXTLOAD instruction from 507 // smaller type. 508 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 509 TLI.ShouldShrinkFPConstant(OrigVT)) { 510 const Type *SType = SVT.getTypeForMVT(); 511 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 512 VT = SVT; 513 Extend = true; 514 } 515 } 516 517 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 518 if (Extend) 519 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 520 CPIdx, PseudoSourceValue::getConstantPool(), 521 0, VT); 522 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 523 PseudoSourceValue::getConstantPool(), 0); 524} 525 526 527/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 528/// operations. 529static 530SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 531 SelectionDAG &DAG, TargetLowering &TLI) { 532 MVT VT = Node->getValueType(0); 533 MVT SrcVT = Node->getOperand(1).getValueType(); 534 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 535 "fcopysign expansion only supported for f32 and f64"); 536 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 537 538 // First get the sign bit of second operand. 539 SDOperand Mask1 = (SrcVT == MVT::f64) 540 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 541 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 542 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 543 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 544 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 545 // Shift right or sign-extend it if the two operands have different types. 546 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 547 if (SizeDiff > 0) { 548 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 549 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 550 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 551 } else if (SizeDiff < 0) 552 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 553 554 // Clear the sign bit of first operand. 555 SDOperand Mask2 = (VT == MVT::f64) 556 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 557 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 558 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 559 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 560 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 561 562 // Or the value with the sign bit. 563 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 564 return Result; 565} 566 567/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 568static 569SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 570 TargetLowering &TLI) { 571 SDOperand Chain = ST->getChain(); 572 SDOperand Ptr = ST->getBasePtr(); 573 SDOperand Val = ST->getValue(); 574 MVT VT = Val.getValueType(); 575 int Alignment = ST->getAlignment(); 576 int SVOffset = ST->getSrcValueOffset(); 577 if (ST->getMemoryVT().isFloatingPoint() || 578 ST->getMemoryVT().isVector()) { 579 // Expand to a bitconvert of the value to the integer type of the 580 // same size, then a (misaligned) int store. 581 MVT intVT; 582 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) 583 intVT = MVT::i128; 584 else if (VT.is64BitVector() || VT==MVT::f64) 585 intVT = MVT::i64; 586 else if (VT==MVT::f32) 587 intVT = MVT::i32; 588 else 589 assert(0 && "Unaligned store of unsupported type"); 590 591 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 592 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 593 SVOffset, ST->isVolatile(), Alignment); 594 } 595 assert(ST->getMemoryVT().isInteger() && 596 !ST->getMemoryVT().isVector() && 597 "Unaligned store of unknown type."); 598 // Get the half-size VT 599 MVT NewStoredVT = 600 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 601 int NumBits = NewStoredVT.getSizeInBits(); 602 int IncrementSize = NumBits / 8; 603 604 // Divide the stored value in two parts. 605 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 606 SDOperand Lo = Val; 607 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 608 609 // Store the two parts 610 SDOperand Store1, Store2; 611 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 612 ST->getSrcValue(), SVOffset, NewStoredVT, 613 ST->isVolatile(), Alignment); 614 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 615 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 616 Alignment = MinAlign(Alignment, IncrementSize); 617 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 618 ST->getSrcValue(), SVOffset + IncrementSize, 619 NewStoredVT, ST->isVolatile(), Alignment); 620 621 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 622} 623 624/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 625static 626SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 627 TargetLowering &TLI) { 628 int SVOffset = LD->getSrcValueOffset(); 629 SDOperand Chain = LD->getChain(); 630 SDOperand Ptr = LD->getBasePtr(); 631 MVT VT = LD->getValueType(0); 632 MVT LoadedVT = LD->getMemoryVT(); 633 if (VT.isFloatingPoint() || VT.isVector()) { 634 // Expand to a (misaligned) integer load of the same size, 635 // then bitconvert to floating point or vector. 636 MVT intVT; 637 if (LoadedVT.is128BitVector() || 638 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 639 intVT = MVT::i128; 640 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) 641 intVT = MVT::i64; 642 else if (LoadedVT == MVT::f32) 643 intVT = MVT::i32; 644 else 645 assert(0 && "Unaligned load of unsupported type"); 646 647 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 648 SVOffset, LD->isVolatile(), 649 LD->getAlignment()); 650 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 651 if (VT.isFloatingPoint() && LoadedVT != VT) 652 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 653 654 SDOperand Ops[] = { Result, Chain }; 655 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 656 Ops, 2); 657 } 658 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 659 "Unaligned load of unsupported type."); 660 661 // Compute the new VT that is half the size of the old one. This is an 662 // integer MVT. 663 unsigned NumBits = LoadedVT.getSizeInBits(); 664 MVT NewLoadedVT; 665 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 666 NumBits >>= 1; 667 668 unsigned Alignment = LD->getAlignment(); 669 unsigned IncrementSize = NumBits / 8; 670 ISD::LoadExtType HiExtType = LD->getExtensionType(); 671 672 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 673 if (HiExtType == ISD::NON_EXTLOAD) 674 HiExtType = ISD::ZEXTLOAD; 675 676 // Load the value in two parts 677 SDOperand Lo, Hi; 678 if (TLI.isLittleEndian()) { 679 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 680 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 681 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 682 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 683 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 684 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 685 MinAlign(Alignment, IncrementSize)); 686 } else { 687 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 688 NewLoadedVT,LD->isVolatile(), Alignment); 689 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 690 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 691 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 692 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 693 MinAlign(Alignment, IncrementSize)); 694 } 695 696 // aggregate the two parts 697 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 698 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 699 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 700 701 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 702 Hi.getValue(1)); 703 704 SDOperand Ops[] = { Result, TF }; 705 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 706} 707 708/// UnrollVectorOp - We know that the given vector has a legal type, however 709/// the operation it performs is not legal and is an operation that we have 710/// no way of lowering. "Unroll" the vector, splitting out the scalars and 711/// operating on each element individually. 712SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 713 MVT VT = Op.getValueType(); 714 assert(isTypeLegal(VT) && 715 "Caller should expand or promote operands that are not legal!"); 716 assert(Op.Val->getNumValues() == 1 && 717 "Can't unroll a vector with multiple results!"); 718 unsigned NE = VT.getVectorNumElements(); 719 MVT EltVT = VT.getVectorElementType(); 720 721 SmallVector<SDOperand, 8> Scalars; 722 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 723 for (unsigned i = 0; i != NE; ++i) { 724 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 725 SDOperand Operand = Op.getOperand(j); 726 MVT OperandVT = Operand.getValueType(); 727 if (OperandVT.isVector()) { 728 // A vector operand; extract a single element. 729 MVT OperandEltVT = OperandVT.getVectorElementType(); 730 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 731 OperandEltVT, 732 Operand, 733 DAG.getConstant(i, MVT::i32)); 734 } else { 735 // A scalar operand; just use it as is. 736 Operands[j] = Operand; 737 } 738 } 739 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 740 &Operands[0], Operands.size())); 741 } 742 743 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 744} 745 746/// GetFPLibCall - Return the right libcall for the given floating point type. 747static RTLIB::Libcall GetFPLibCall(MVT VT, 748 RTLIB::Libcall Call_F32, 749 RTLIB::Libcall Call_F64, 750 RTLIB::Libcall Call_F80, 751 RTLIB::Libcall Call_PPCF128) { 752 return 753 VT == MVT::f32 ? Call_F32 : 754 VT == MVT::f64 ? Call_F64 : 755 VT == MVT::f80 ? Call_F80 : 756 VT == MVT::ppcf128 ? Call_PPCF128 : 757 RTLIB::UNKNOWN_LIBCALL; 758} 759 760/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 761/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 762/// is necessary to spill the vector being inserted into to memory, perform 763/// the insert there, and then read the result back. 764SDOperand SelectionDAGLegalize:: 765PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { 766 SDOperand Tmp1 = Vec; 767 SDOperand Tmp2 = Val; 768 SDOperand Tmp3 = Idx; 769 770 // If the target doesn't support this, we have to spill the input vector 771 // to a temporary stack slot, update the element, then reload it. This is 772 // badness. We could also load the value into a vector register (either 773 // with a "move to register" or "extload into register" instruction, then 774 // permute it into place, if the idx is a constant and if the idx is 775 // supported by the target. 776 MVT VT = Tmp1.getValueType(); 777 MVT EltVT = VT.getVectorElementType(); 778 MVT IdxVT = Tmp3.getValueType(); 779 MVT PtrVT = TLI.getPointerTy(); 780 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 781 782 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); 783 int SPFI = StackPtrFI->getIndex(); 784 785 // Store the vector. 786 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 787 PseudoSourceValue::getFixedStack(), 788 SPFI); 789 790 // Truncate or zero extend offset to target pointer type. 791 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 792 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 793 // Add the offset to the index. 794 unsigned EltSize = EltVT.getSizeInBits()/8; 795 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 796 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 797 // Store the scalar value. 798 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 799 PseudoSourceValue::getFixedStack(), SPFI, EltVT); 800 // Load the updated vector. 801 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI); 802} 803 804/// LegalizeOp - We know that the specified value has a legal type, and 805/// that its operands are legal. Now ensure that the operation itself 806/// is legal, recursively ensuring that the operands' operations remain 807/// legal. 808SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 809 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 810 return Op; 811 812 assert(isTypeLegal(Op.getValueType()) && 813 "Caller should expand or promote operands that are not legal!"); 814 SDNode *Node = Op.Val; 815 816 // If this operation defines any values that cannot be represented in a 817 // register on this target, make sure to expand or promote them. 818 if (Node->getNumValues() > 1) { 819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 820 if (getTypeAction(Node->getValueType(i)) != Legal) { 821 HandleOp(Op.getValue(i)); 822 assert(LegalizedNodes.count(Op) && 823 "Handling didn't add legal operands!"); 824 return LegalizedNodes[Op]; 825 } 826 } 827 828 // Note that LegalizeOp may be reentered even from single-use nodes, which 829 // means that we always must cache transformed nodes. 830 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 831 if (I != LegalizedNodes.end()) return I->second; 832 833 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 834 SDOperand Result = Op; 835 bool isCustom = false; 836 837 switch (Node->getOpcode()) { 838 case ISD::FrameIndex: 839 case ISD::EntryToken: 840 case ISD::Register: 841 case ISD::BasicBlock: 842 case ISD::TargetFrameIndex: 843 case ISD::TargetJumpTable: 844 case ISD::TargetConstant: 845 case ISD::TargetConstantFP: 846 case ISD::TargetConstantPool: 847 case ISD::TargetGlobalAddress: 848 case ISD::TargetGlobalTLSAddress: 849 case ISD::TargetExternalSymbol: 850 case ISD::VALUETYPE: 851 case ISD::SRCVALUE: 852 case ISD::MEMOPERAND: 853 case ISD::STRING: 854 case ISD::CONDCODE: 855 case ISD::ARG_FLAGS: 856 // Primitives must all be legal. 857 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 858 "This must be legal!"); 859 break; 860 default: 861 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 862 // If this is a target node, legalize it by legalizing the operands then 863 // passing it through. 864 SmallVector<SDOperand, 8> Ops; 865 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 866 Ops.push_back(LegalizeOp(Node->getOperand(i))); 867 868 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 869 870 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 871 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 872 return Result.getValue(Op.ResNo); 873 } 874 // Otherwise this is an unhandled builtin node. splat. 875#ifndef NDEBUG 876 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 877#endif 878 assert(0 && "Do not know how to legalize this operator!"); 879 abort(); 880 case ISD::GLOBAL_OFFSET_TABLE: 881 case ISD::GlobalAddress: 882 case ISD::GlobalTLSAddress: 883 case ISD::ExternalSymbol: 884 case ISD::ConstantPool: 885 case ISD::JumpTable: // Nothing to do. 886 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 887 default: assert(0 && "This action is not supported yet!"); 888 case TargetLowering::Custom: 889 Tmp1 = TLI.LowerOperation(Op, DAG); 890 if (Tmp1.Val) Result = Tmp1; 891 // FALLTHROUGH if the target doesn't want to lower this op after all. 892 case TargetLowering::Legal: 893 break; 894 } 895 break; 896 case ISD::FRAMEADDR: 897 case ISD::RETURNADDR: 898 // The only option for these nodes is to custom lower them. If the target 899 // does not custom lower them, then return zero. 900 Tmp1 = TLI.LowerOperation(Op, DAG); 901 if (Tmp1.Val) 902 Result = Tmp1; 903 else 904 Result = DAG.getConstant(0, TLI.getPointerTy()); 905 break; 906 case ISD::FRAME_TO_ARGS_OFFSET: { 907 MVT VT = Node->getValueType(0); 908 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 909 default: assert(0 && "This action is not supported yet!"); 910 case TargetLowering::Custom: 911 Result = TLI.LowerOperation(Op, DAG); 912 if (Result.Val) break; 913 // Fall Thru 914 case TargetLowering::Legal: 915 Result = DAG.getConstant(0, VT); 916 break; 917 } 918 } 919 break; 920 case ISD::EXCEPTIONADDR: { 921 Tmp1 = LegalizeOp(Node->getOperand(0)); 922 MVT VT = Node->getValueType(0); 923 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 924 default: assert(0 && "This action is not supported yet!"); 925 case TargetLowering::Expand: { 926 unsigned Reg = TLI.getExceptionAddressRegister(); 927 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 928 } 929 break; 930 case TargetLowering::Custom: 931 Result = TLI.LowerOperation(Op, DAG); 932 if (Result.Val) break; 933 // Fall Thru 934 case TargetLowering::Legal: { 935 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 936 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 937 Ops, 2); 938 break; 939 } 940 } 941 } 942 if (Result.Val->getNumValues() == 1) break; 943 944 assert(Result.Val->getNumValues() == 2 && 945 "Cannot return more than two values!"); 946 947 // Since we produced two values, make sure to remember that we 948 // legalized both of them. 949 Tmp1 = LegalizeOp(Result); 950 Tmp2 = LegalizeOp(Result.getValue(1)); 951 AddLegalizedOperand(Op.getValue(0), Tmp1); 952 AddLegalizedOperand(Op.getValue(1), Tmp2); 953 return Op.ResNo ? Tmp2 : Tmp1; 954 case ISD::EHSELECTION: { 955 Tmp1 = LegalizeOp(Node->getOperand(0)); 956 Tmp2 = LegalizeOp(Node->getOperand(1)); 957 MVT VT = Node->getValueType(0); 958 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 959 default: assert(0 && "This action is not supported yet!"); 960 case TargetLowering::Expand: { 961 unsigned Reg = TLI.getExceptionSelectorRegister(); 962 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 963 } 964 break; 965 case TargetLowering::Custom: 966 Result = TLI.LowerOperation(Op, DAG); 967 if (Result.Val) break; 968 // Fall Thru 969 case TargetLowering::Legal: { 970 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 971 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 972 Ops, 2); 973 break; 974 } 975 } 976 } 977 if (Result.Val->getNumValues() == 1) break; 978 979 assert(Result.Val->getNumValues() == 2 && 980 "Cannot return more than two values!"); 981 982 // Since we produced two values, make sure to remember that we 983 // legalized both of them. 984 Tmp1 = LegalizeOp(Result); 985 Tmp2 = LegalizeOp(Result.getValue(1)); 986 AddLegalizedOperand(Op.getValue(0), Tmp1); 987 AddLegalizedOperand(Op.getValue(1), Tmp2); 988 return Op.ResNo ? Tmp2 : Tmp1; 989 case ISD::EH_RETURN: { 990 MVT VT = Node->getValueType(0); 991 // The only "good" option for this node is to custom lower it. 992 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 993 default: assert(0 && "This action is not supported at all!"); 994 case TargetLowering::Custom: 995 Result = TLI.LowerOperation(Op, DAG); 996 if (Result.Val) break; 997 // Fall Thru 998 case TargetLowering::Legal: 999 // Target does not know, how to lower this, lower to noop 1000 Result = LegalizeOp(Node->getOperand(0)); 1001 break; 1002 } 1003 } 1004 break; 1005 case ISD::AssertSext: 1006 case ISD::AssertZext: 1007 Tmp1 = LegalizeOp(Node->getOperand(0)); 1008 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1009 break; 1010 case ISD::MERGE_VALUES: 1011 // Legalize eliminates MERGE_VALUES nodes. 1012 Result = Node->getOperand(Op.ResNo); 1013 break; 1014 case ISD::CopyFromReg: 1015 Tmp1 = LegalizeOp(Node->getOperand(0)); 1016 Result = Op.getValue(0); 1017 if (Node->getNumValues() == 2) { 1018 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1019 } else { 1020 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1021 if (Node->getNumOperands() == 3) { 1022 Tmp2 = LegalizeOp(Node->getOperand(2)); 1023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1024 } else { 1025 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1026 } 1027 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1028 } 1029 // Since CopyFromReg produces two values, make sure to remember that we 1030 // legalized both of them. 1031 AddLegalizedOperand(Op.getValue(0), Result); 1032 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1033 return Result.getValue(Op.ResNo); 1034 case ISD::UNDEF: { 1035 MVT VT = Op.getValueType(); 1036 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1037 default: assert(0 && "This action is not supported yet!"); 1038 case TargetLowering::Expand: 1039 if (VT.isInteger()) 1040 Result = DAG.getConstant(0, VT); 1041 else if (VT.isFloatingPoint()) 1042 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1043 VT); 1044 else 1045 assert(0 && "Unknown value type!"); 1046 break; 1047 case TargetLowering::Legal: 1048 break; 1049 } 1050 break; 1051 } 1052 1053 case ISD::INTRINSIC_W_CHAIN: 1054 case ISD::INTRINSIC_WO_CHAIN: 1055 case ISD::INTRINSIC_VOID: { 1056 SmallVector<SDOperand, 8> Ops; 1057 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1058 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1059 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1060 1061 // Allow the target to custom lower its intrinsics if it wants to. 1062 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1063 TargetLowering::Custom) { 1064 Tmp3 = TLI.LowerOperation(Result, DAG); 1065 if (Tmp3.Val) Result = Tmp3; 1066 } 1067 1068 if (Result.Val->getNumValues() == 1) break; 1069 1070 // Must have return value and chain result. 1071 assert(Result.Val->getNumValues() == 2 && 1072 "Cannot return more than two values!"); 1073 1074 // Since loads produce two values, make sure to remember that we 1075 // legalized both of them. 1076 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1077 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1078 return Result.getValue(Op.ResNo); 1079 } 1080 1081 case ISD::LOCATION: 1082 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1083 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1084 1085 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1086 case TargetLowering::Promote: 1087 default: assert(0 && "This action is not supported yet!"); 1088 case TargetLowering::Expand: { 1089 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1090 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1091 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1092 1093 if (MMI && (useDEBUG_LOC || useLABEL)) { 1094 const std::string &FName = 1095 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1096 const std::string &DirName = 1097 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1098 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1099 1100 SmallVector<SDOperand, 8> Ops; 1101 Ops.push_back(Tmp1); // chain 1102 SDOperand LineOp = Node->getOperand(1); 1103 SDOperand ColOp = Node->getOperand(2); 1104 1105 if (useDEBUG_LOC) { 1106 Ops.push_back(LineOp); // line # 1107 Ops.push_back(ColOp); // col # 1108 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1109 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1110 } else { 1111 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1112 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1113 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1114 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1115 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label 1116 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size()); 1117 } 1118 } else { 1119 Result = Tmp1; // chain 1120 } 1121 break; 1122 } 1123 case TargetLowering::Legal: 1124 if (Tmp1 != Node->getOperand(0) || 1125 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1126 SmallVector<SDOperand, 8> Ops; 1127 Ops.push_back(Tmp1); 1128 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1129 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1130 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1131 } else { 1132 // Otherwise promote them. 1133 Ops.push_back(PromoteOp(Node->getOperand(1))); 1134 Ops.push_back(PromoteOp(Node->getOperand(2))); 1135 } 1136 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1137 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1138 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1139 } 1140 break; 1141 } 1142 break; 1143 1144 case ISD::DECLARE: 1145 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1146 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1147 default: assert(0 && "This action is not supported yet!"); 1148 case TargetLowering::Legal: 1149 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1150 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1151 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1153 break; 1154 case TargetLowering::Expand: 1155 Result = LegalizeOp(Node->getOperand(0)); 1156 break; 1157 } 1158 break; 1159 1160 case ISD::DEBUG_LOC: 1161 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1162 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1163 default: assert(0 && "This action is not supported yet!"); 1164 case TargetLowering::Legal: 1165 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1166 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1167 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1168 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1169 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1170 break; 1171 } 1172 break; 1173 1174 case ISD::LABEL: 1175 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!"); 1176 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1177 default: assert(0 && "This action is not supported yet!"); 1178 case TargetLowering::Legal: 1179 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1180 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1181 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand. 1182 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1183 break; 1184 case TargetLowering::Expand: 1185 Result = LegalizeOp(Node->getOperand(0)); 1186 break; 1187 } 1188 break; 1189 1190 case ISD::PREFETCH: 1191 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1192 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1193 default: assert(0 && "This action is not supported yet!"); 1194 case TargetLowering::Legal: 1195 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1196 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1197 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1198 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1199 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1200 break; 1201 case TargetLowering::Expand: 1202 // It's a noop. 1203 Result = LegalizeOp(Node->getOperand(0)); 1204 break; 1205 } 1206 break; 1207 1208 case ISD::MEMBARRIER: { 1209 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1210 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1211 default: assert(0 && "This action is not supported yet!"); 1212 case TargetLowering::Legal: { 1213 SDOperand Ops[6]; 1214 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1215 for (int x = 1; x < 6; ++x) { 1216 Ops[x] = Node->getOperand(x); 1217 if (!isTypeLegal(Ops[x].getValueType())) 1218 Ops[x] = PromoteOp(Ops[x]); 1219 } 1220 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1221 break; 1222 } 1223 case TargetLowering::Expand: 1224 //There is no libgcc call for this op 1225 Result = Node->getOperand(0); // Noop 1226 break; 1227 } 1228 break; 1229 } 1230 1231 case ISD::ATOMIC_LCS: { 1232 unsigned int num_operands = 4; 1233 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1234 SDOperand Ops[4]; 1235 for (unsigned int x = 0; x < num_operands; ++x) 1236 Ops[x] = LegalizeOp(Node->getOperand(x)); 1237 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1238 1239 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1240 default: assert(0 && "This action is not supported yet!"); 1241 case TargetLowering::Custom: 1242 Result = TLI.LowerOperation(Result, DAG); 1243 break; 1244 case TargetLowering::Legal: 1245 break; 1246 } 1247 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1248 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1249 return Result.getValue(Op.ResNo); 1250 } 1251 case ISD::ATOMIC_LAS: 1252 case ISD::ATOMIC_LSS: 1253 case ISD::ATOMIC_LOAD_AND: 1254 case ISD::ATOMIC_LOAD_OR: 1255 case ISD::ATOMIC_LOAD_XOR: 1256 case ISD::ATOMIC_LOAD_NAND: 1257 case ISD::ATOMIC_LOAD_MIN: 1258 case ISD::ATOMIC_LOAD_MAX: 1259 case ISD::ATOMIC_LOAD_UMIN: 1260 case ISD::ATOMIC_LOAD_UMAX: 1261 case ISD::ATOMIC_SWAP: { 1262 unsigned int num_operands = 3; 1263 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1264 SDOperand Ops[3]; 1265 for (unsigned int x = 0; x < num_operands; ++x) 1266 Ops[x] = LegalizeOp(Node->getOperand(x)); 1267 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1268 1269 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1270 default: assert(0 && "This action is not supported yet!"); 1271 case TargetLowering::Custom: 1272 Result = TLI.LowerOperation(Result, DAG); 1273 break; 1274 case TargetLowering::Expand: 1275 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0); 1276 break; 1277 case TargetLowering::Legal: 1278 break; 1279 } 1280 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1281 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1282 return Result.getValue(Op.ResNo); 1283 } 1284 case ISD::Constant: { 1285 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1286 unsigned opAction = 1287 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1288 1289 // We know we don't need to expand constants here, constants only have one 1290 // value and we check that it is fine above. 1291 1292 if (opAction == TargetLowering::Custom) { 1293 Tmp1 = TLI.LowerOperation(Result, DAG); 1294 if (Tmp1.Val) 1295 Result = Tmp1; 1296 } 1297 break; 1298 } 1299 case ISD::ConstantFP: { 1300 // Spill FP immediates to the constant pool if the target cannot directly 1301 // codegen them. Targets often have some immediate values that can be 1302 // efficiently generated into an FP register without a load. We explicitly 1303 // leave these constants as ConstantFP nodes for the target to deal with. 1304 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1305 1306 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1307 default: assert(0 && "This action is not supported yet!"); 1308 case TargetLowering::Legal: 1309 break; 1310 case TargetLowering::Custom: 1311 Tmp3 = TLI.LowerOperation(Result, DAG); 1312 if (Tmp3.Val) { 1313 Result = Tmp3; 1314 break; 1315 } 1316 // FALLTHROUGH 1317 case TargetLowering::Expand: { 1318 // Check to see if this FP immediate is already legal. 1319 bool isLegal = false; 1320 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1321 E = TLI.legal_fpimm_end(); I != E; ++I) { 1322 if (CFP->isExactlyValue(*I)) { 1323 isLegal = true; 1324 break; 1325 } 1326 } 1327 // If this is a legal constant, turn it into a TargetConstantFP node. 1328 if (isLegal) 1329 break; 1330 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1331 } 1332 } 1333 break; 1334 } 1335 case ISD::TokenFactor: 1336 if (Node->getNumOperands() == 2) { 1337 Tmp1 = LegalizeOp(Node->getOperand(0)); 1338 Tmp2 = LegalizeOp(Node->getOperand(1)); 1339 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1340 } else if (Node->getNumOperands() == 3) { 1341 Tmp1 = LegalizeOp(Node->getOperand(0)); 1342 Tmp2 = LegalizeOp(Node->getOperand(1)); 1343 Tmp3 = LegalizeOp(Node->getOperand(2)); 1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1345 } else { 1346 SmallVector<SDOperand, 8> Ops; 1347 // Legalize the operands. 1348 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1349 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1350 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1351 } 1352 break; 1353 1354 case ISD::FORMAL_ARGUMENTS: 1355 case ISD::CALL: 1356 // The only option for this is to custom lower it. 1357 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1358 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1359 // A call within a calling sequence must be legalized to something 1360 // other than the normal CALLSEQ_END. Violating this gets Legalize 1361 // into an infinite loop. 1362 assert ((!IsLegalizingCall || 1363 Node->getOpcode() != ISD::CALL || 1364 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1365 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1366 1367 // The number of incoming and outgoing values should match; unless the final 1368 // outgoing value is a flag. 1369 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1370 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1371 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1372 MVT::Flag)) && 1373 "Lowering call/formal_arguments produced unexpected # results!"); 1374 1375 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1376 // remember that we legalized all of them, so it doesn't get relegalized. 1377 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1378 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1379 continue; 1380 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1381 if (Op.ResNo == i) 1382 Tmp2 = Tmp1; 1383 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1384 } 1385 return Tmp2; 1386 case ISD::EXTRACT_SUBREG: { 1387 Tmp1 = LegalizeOp(Node->getOperand(0)); 1388 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1389 assert(idx && "Operand must be a constant"); 1390 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1392 } 1393 break; 1394 case ISD::INSERT_SUBREG: { 1395 Tmp1 = LegalizeOp(Node->getOperand(0)); 1396 Tmp2 = LegalizeOp(Node->getOperand(1)); 1397 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1398 assert(idx && "Operand must be a constant"); 1399 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1400 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1401 } 1402 break; 1403 case ISD::BUILD_VECTOR: 1404 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1405 default: assert(0 && "This action is not supported yet!"); 1406 case TargetLowering::Custom: 1407 Tmp3 = TLI.LowerOperation(Result, DAG); 1408 if (Tmp3.Val) { 1409 Result = Tmp3; 1410 break; 1411 } 1412 // FALLTHROUGH 1413 case TargetLowering::Expand: 1414 Result = ExpandBUILD_VECTOR(Result.Val); 1415 break; 1416 } 1417 break; 1418 case ISD::INSERT_VECTOR_ELT: 1419 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1420 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1421 1422 // The type of the value to insert may not be legal, even though the vector 1423 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1424 // here. 1425 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1426 default: assert(0 && "Cannot expand insert element operand"); 1427 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1428 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1429 } 1430 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1431 1432 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1433 Node->getValueType(0))) { 1434 default: assert(0 && "This action is not supported yet!"); 1435 case TargetLowering::Legal: 1436 break; 1437 case TargetLowering::Custom: 1438 Tmp4 = TLI.LowerOperation(Result, DAG); 1439 if (Tmp4.Val) { 1440 Result = Tmp4; 1441 break; 1442 } 1443 // FALLTHROUGH 1444 case TargetLowering::Expand: { 1445 // If the insert index is a constant, codegen this as a scalar_to_vector, 1446 // then a shuffle that inserts it into the right position in the vector. 1447 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1448 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1449 // match the element type of the vector being created. 1450 if (Tmp2.getValueType() == 1451 Op.getValueType().getVectorElementType()) { 1452 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1453 Tmp1.getValueType(), Tmp2); 1454 1455 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1456 MVT ShufMaskVT = 1457 MVT::getIntVectorWithNumElements(NumElts); 1458 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1459 1460 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1461 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1462 // elt 0 of the RHS. 1463 SmallVector<SDOperand, 8> ShufOps; 1464 for (unsigned i = 0; i != NumElts; ++i) { 1465 if (i != InsertPos->getValue()) 1466 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1467 else 1468 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1469 } 1470 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1471 &ShufOps[0], ShufOps.size()); 1472 1473 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1474 Tmp1, ScVec, ShufMask); 1475 Result = LegalizeOp(Result); 1476 break; 1477 } 1478 } 1479 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1480 break; 1481 } 1482 } 1483 break; 1484 case ISD::SCALAR_TO_VECTOR: 1485 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1486 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1487 break; 1488 } 1489 1490 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1491 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1492 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1493 Node->getValueType(0))) { 1494 default: assert(0 && "This action is not supported yet!"); 1495 case TargetLowering::Legal: 1496 break; 1497 case TargetLowering::Custom: 1498 Tmp3 = TLI.LowerOperation(Result, DAG); 1499 if (Tmp3.Val) { 1500 Result = Tmp3; 1501 break; 1502 } 1503 // FALLTHROUGH 1504 case TargetLowering::Expand: 1505 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1506 break; 1507 } 1508 break; 1509 case ISD::VECTOR_SHUFFLE: 1510 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1511 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1513 1514 // Allow targets to custom lower the SHUFFLEs they support. 1515 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1516 default: assert(0 && "Unknown operation action!"); 1517 case TargetLowering::Legal: 1518 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1519 "vector shuffle should not be created if not legal!"); 1520 break; 1521 case TargetLowering::Custom: 1522 Tmp3 = TLI.LowerOperation(Result, DAG); 1523 if (Tmp3.Val) { 1524 Result = Tmp3; 1525 break; 1526 } 1527 // FALLTHROUGH 1528 case TargetLowering::Expand: { 1529 MVT VT = Node->getValueType(0); 1530 MVT EltVT = VT.getVectorElementType(); 1531 MVT PtrVT = TLI.getPointerTy(); 1532 SDOperand Mask = Node->getOperand(2); 1533 unsigned NumElems = Mask.getNumOperands(); 1534 SmallVector<SDOperand,8> Ops; 1535 for (unsigned i = 0; i != NumElems; ++i) { 1536 SDOperand Arg = Mask.getOperand(i); 1537 if (Arg.getOpcode() == ISD::UNDEF) { 1538 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1539 } else { 1540 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1541 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1542 if (Idx < NumElems) 1543 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1544 DAG.getConstant(Idx, PtrVT))); 1545 else 1546 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1547 DAG.getConstant(Idx - NumElems, PtrVT))); 1548 } 1549 } 1550 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1551 break; 1552 } 1553 case TargetLowering::Promote: { 1554 // Change base type to a different vector type. 1555 MVT OVT = Node->getValueType(0); 1556 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1557 1558 // Cast the two input vectors. 1559 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1560 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1561 1562 // Convert the shuffle mask to the right # elements. 1563 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1564 assert(Tmp3.Val && "Shuffle not legal?"); 1565 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1566 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1567 break; 1568 } 1569 } 1570 break; 1571 1572 case ISD::EXTRACT_VECTOR_ELT: 1573 Tmp1 = Node->getOperand(0); 1574 Tmp2 = LegalizeOp(Node->getOperand(1)); 1575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1576 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1577 break; 1578 1579 case ISD::EXTRACT_SUBVECTOR: 1580 Tmp1 = Node->getOperand(0); 1581 Tmp2 = LegalizeOp(Node->getOperand(1)); 1582 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1583 Result = ExpandEXTRACT_SUBVECTOR(Result); 1584 break; 1585 1586 case ISD::CALLSEQ_START: { 1587 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1588 1589 // Recursively Legalize all of the inputs of the call end that do not lead 1590 // to this call start. This ensures that any libcalls that need be inserted 1591 // are inserted *before* the CALLSEQ_START. 1592 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1593 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1594 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1595 NodesLeadingTo); 1596 } 1597 1598 // Now that we legalized all of the inputs (which may have inserted 1599 // libcalls) create the new CALLSEQ_START node. 1600 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1601 1602 // Merge in the last call, to ensure that this call start after the last 1603 // call ended. 1604 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1605 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1606 Tmp1 = LegalizeOp(Tmp1); 1607 } 1608 1609 // Do not try to legalize the target-specific arguments (#1+). 1610 if (Tmp1 != Node->getOperand(0)) { 1611 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1612 Ops[0] = Tmp1; 1613 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1614 } 1615 1616 // Remember that the CALLSEQ_START is legalized. 1617 AddLegalizedOperand(Op.getValue(0), Result); 1618 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1619 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1620 1621 // Now that the callseq_start and all of the non-call nodes above this call 1622 // sequence have been legalized, legalize the call itself. During this 1623 // process, no libcalls can/will be inserted, guaranteeing that no calls 1624 // can overlap. 1625 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1626 // Note that we are selecting this call! 1627 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1628 IsLegalizingCall = true; 1629 1630 // Legalize the call, starting from the CALLSEQ_END. 1631 LegalizeOp(LastCALLSEQ_END); 1632 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1633 return Result; 1634 } 1635 case ISD::CALLSEQ_END: 1636 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1637 // will cause this node to be legalized as well as handling libcalls right. 1638 if (LastCALLSEQ_END.Val != Node) { 1639 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1640 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1641 assert(I != LegalizedNodes.end() && 1642 "Legalizing the call start should have legalized this node!"); 1643 return I->second; 1644 } 1645 1646 // Otherwise, the call start has been legalized and everything is going 1647 // according to plan. Just legalize ourselves normally here. 1648 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1649 // Do not try to legalize the target-specific arguments (#1+), except for 1650 // an optional flag input. 1651 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1652 if (Tmp1 != Node->getOperand(0)) { 1653 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1654 Ops[0] = Tmp1; 1655 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1656 } 1657 } else { 1658 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1659 if (Tmp1 != Node->getOperand(0) || 1660 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1661 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1662 Ops[0] = Tmp1; 1663 Ops.back() = Tmp2; 1664 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1665 } 1666 } 1667 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1668 // This finishes up call legalization. 1669 IsLegalizingCall = false; 1670 1671 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1672 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1673 if (Node->getNumValues() == 2) 1674 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1675 return Result.getValue(Op.ResNo); 1676 case ISD::DYNAMIC_STACKALLOC: { 1677 MVT VT = Node->getValueType(0); 1678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1680 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1681 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1682 1683 Tmp1 = Result.getValue(0); 1684 Tmp2 = Result.getValue(1); 1685 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1686 default: assert(0 && "This action is not supported yet!"); 1687 case TargetLowering::Expand: { 1688 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1689 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1690 " not tell us which reg is the stack pointer!"); 1691 SDOperand Chain = Tmp1.getOperand(0); 1692 1693 // Chain the dynamic stack allocation so that it doesn't modify the stack 1694 // pointer when other instructions are using the stack. 1695 Chain = DAG.getCALLSEQ_START(Chain, 1696 DAG.getConstant(0, TLI.getPointerTy())); 1697 1698 SDOperand Size = Tmp2.getOperand(1); 1699 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1700 Chain = SP.getValue(1); 1701 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1702 unsigned StackAlign = 1703 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1704 if (Align > StackAlign) 1705 SP = DAG.getNode(ISD::AND, VT, SP, 1706 DAG.getConstant(-(uint64_t)Align, VT)); 1707 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1708 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1709 1710 Tmp2 = 1711 DAG.getCALLSEQ_END(Chain, 1712 DAG.getConstant(0, TLI.getPointerTy()), 1713 DAG.getConstant(0, TLI.getPointerTy()), 1714 SDOperand()); 1715 1716 Tmp1 = LegalizeOp(Tmp1); 1717 Tmp2 = LegalizeOp(Tmp2); 1718 break; 1719 } 1720 case TargetLowering::Custom: 1721 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1722 if (Tmp3.Val) { 1723 Tmp1 = LegalizeOp(Tmp3); 1724 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1725 } 1726 break; 1727 case TargetLowering::Legal: 1728 break; 1729 } 1730 // Since this op produce two values, make sure to remember that we 1731 // legalized both of them. 1732 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1733 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1734 return Op.ResNo ? Tmp2 : Tmp1; 1735 } 1736 case ISD::INLINEASM: { 1737 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1738 bool Changed = false; 1739 // Legalize all of the operands of the inline asm, in case they are nodes 1740 // that need to be expanded or something. Note we skip the asm string and 1741 // all of the TargetConstant flags. 1742 SDOperand Op = LegalizeOp(Ops[0]); 1743 Changed = Op != Ops[0]; 1744 Ops[0] = Op; 1745 1746 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1747 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1748 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1749 for (++i; NumVals; ++i, --NumVals) { 1750 SDOperand Op = LegalizeOp(Ops[i]); 1751 if (Op != Ops[i]) { 1752 Changed = true; 1753 Ops[i] = Op; 1754 } 1755 } 1756 } 1757 1758 if (HasInFlag) { 1759 Op = LegalizeOp(Ops.back()); 1760 Changed |= Op != Ops.back(); 1761 Ops.back() = Op; 1762 } 1763 1764 if (Changed) 1765 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1766 1767 // INLINE asm returns a chain and flag, make sure to add both to the map. 1768 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1769 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1770 return Result.getValue(Op.ResNo); 1771 } 1772 case ISD::BR: 1773 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1774 // Ensure that libcalls are emitted before a branch. 1775 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1776 Tmp1 = LegalizeOp(Tmp1); 1777 LastCALLSEQ_END = DAG.getEntryNode(); 1778 1779 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1780 break; 1781 case ISD::BRIND: 1782 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1783 // Ensure that libcalls are emitted before a branch. 1784 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1785 Tmp1 = LegalizeOp(Tmp1); 1786 LastCALLSEQ_END = DAG.getEntryNode(); 1787 1788 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1789 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1790 case Legal: 1791 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1792 break; 1793 } 1794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1795 break; 1796 case ISD::BR_JT: 1797 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1798 // Ensure that libcalls are emitted before a branch. 1799 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1800 Tmp1 = LegalizeOp(Tmp1); 1801 LastCALLSEQ_END = DAG.getEntryNode(); 1802 1803 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1804 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1805 1806 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1807 default: assert(0 && "This action is not supported yet!"); 1808 case TargetLowering::Legal: break; 1809 case TargetLowering::Custom: 1810 Tmp1 = TLI.LowerOperation(Result, DAG); 1811 if (Tmp1.Val) Result = Tmp1; 1812 break; 1813 case TargetLowering::Expand: { 1814 SDOperand Chain = Result.getOperand(0); 1815 SDOperand Table = Result.getOperand(1); 1816 SDOperand Index = Result.getOperand(2); 1817 1818 MVT PTy = TLI.getPointerTy(); 1819 MachineFunction &MF = DAG.getMachineFunction(); 1820 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1821 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1822 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1823 1824 SDOperand LD; 1825 switch (EntrySize) { 1826 default: assert(0 && "Size of jump table not supported yet."); break; 1827 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1828 PseudoSourceValue::getJumpTable(), 0); break; 1829 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1830 PseudoSourceValue::getJumpTable(), 0); break; 1831 } 1832 1833 Addr = LD; 1834 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1835 // For PIC, the sequence is: 1836 // BRIND(load(Jumptable + index) + RelocBase) 1837 // RelocBase can be JumpTable, GOT or some sort of global base. 1838 if (PTy != MVT::i32) 1839 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1840 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1841 TLI.getPICJumpTableRelocBase(Table, DAG)); 1842 } 1843 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1844 } 1845 } 1846 break; 1847 case ISD::BRCOND: 1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1849 // Ensure that libcalls are emitted before a return. 1850 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1851 Tmp1 = LegalizeOp(Tmp1); 1852 LastCALLSEQ_END = DAG.getEntryNode(); 1853 1854 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1855 case Expand: assert(0 && "It's impossible to expand bools"); 1856 case Legal: 1857 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1858 break; 1859 case Promote: { 1860 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1861 1862 // The top bits of the promoted condition are not necessarily zero, ensure 1863 // that the value is properly zero extended. 1864 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1865 if (!DAG.MaskedValueIsZero(Tmp2, 1866 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1867 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1868 break; 1869 } 1870 } 1871 1872 // Basic block destination (Op#2) is always legal. 1873 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1874 1875 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1876 default: assert(0 && "This action is not supported yet!"); 1877 case TargetLowering::Legal: break; 1878 case TargetLowering::Custom: 1879 Tmp1 = TLI.LowerOperation(Result, DAG); 1880 if (Tmp1.Val) Result = Tmp1; 1881 break; 1882 case TargetLowering::Expand: 1883 // Expand brcond's setcc into its constituent parts and create a BR_CC 1884 // Node. 1885 if (Tmp2.getOpcode() == ISD::SETCC) { 1886 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1887 Tmp2.getOperand(0), Tmp2.getOperand(1), 1888 Node->getOperand(2)); 1889 } else { 1890 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1891 DAG.getCondCode(ISD::SETNE), Tmp2, 1892 DAG.getConstant(0, Tmp2.getValueType()), 1893 Node->getOperand(2)); 1894 } 1895 break; 1896 } 1897 break; 1898 case ISD::BR_CC: 1899 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1900 // Ensure that libcalls are emitted before a branch. 1901 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1902 Tmp1 = LegalizeOp(Tmp1); 1903 Tmp2 = Node->getOperand(2); // LHS 1904 Tmp3 = Node->getOperand(3); // RHS 1905 Tmp4 = Node->getOperand(1); // CC 1906 1907 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1908 LastCALLSEQ_END = DAG.getEntryNode(); 1909 1910 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1911 // the LHS is a legal SETCC itself. In this case, we need to compare 1912 // the result against zero to select between true and false values. 1913 if (Tmp3.Val == 0) { 1914 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1915 Tmp4 = DAG.getCondCode(ISD::SETNE); 1916 } 1917 1918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1919 Node->getOperand(4)); 1920 1921 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1922 default: assert(0 && "Unexpected action for BR_CC!"); 1923 case TargetLowering::Legal: break; 1924 case TargetLowering::Custom: 1925 Tmp4 = TLI.LowerOperation(Result, DAG); 1926 if (Tmp4.Val) Result = Tmp4; 1927 break; 1928 } 1929 break; 1930 case ISD::LOAD: { 1931 LoadSDNode *LD = cast<LoadSDNode>(Node); 1932 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1933 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1934 1935 ISD::LoadExtType ExtType = LD->getExtensionType(); 1936 if (ExtType == ISD::NON_EXTLOAD) { 1937 MVT VT = Node->getValueType(0); 1938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1939 Tmp3 = Result.getValue(0); 1940 Tmp4 = Result.getValue(1); 1941 1942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1943 default: assert(0 && "This action is not supported yet!"); 1944 case TargetLowering::Legal: 1945 // If this is an unaligned load and the target doesn't support it, 1946 // expand it. 1947 if (!TLI.allowsUnalignedMemoryAccesses()) { 1948 unsigned ABIAlignment = TLI.getTargetData()-> 1949 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1950 if (LD->getAlignment() < ABIAlignment){ 1951 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1952 TLI); 1953 Tmp3 = Result.getOperand(0); 1954 Tmp4 = Result.getOperand(1); 1955 Tmp3 = LegalizeOp(Tmp3); 1956 Tmp4 = LegalizeOp(Tmp4); 1957 } 1958 } 1959 break; 1960 case TargetLowering::Custom: 1961 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1962 if (Tmp1.Val) { 1963 Tmp3 = LegalizeOp(Tmp1); 1964 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1965 } 1966 break; 1967 case TargetLowering::Promote: { 1968 // Only promote a load of vector type to another. 1969 assert(VT.isVector() && "Cannot promote this load!"); 1970 // Change base type to a different vector type. 1971 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1972 1973 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1974 LD->getSrcValueOffset(), 1975 LD->isVolatile(), LD->getAlignment()); 1976 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1977 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1978 break; 1979 } 1980 } 1981 // Since loads produce two values, make sure to remember that we 1982 // legalized both of them. 1983 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1984 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1985 return Op.ResNo ? Tmp4 : Tmp3; 1986 } else { 1987 MVT SrcVT = LD->getMemoryVT(); 1988 unsigned SrcWidth = SrcVT.getSizeInBits(); 1989 int SVOffset = LD->getSrcValueOffset(); 1990 unsigned Alignment = LD->getAlignment(); 1991 bool isVolatile = LD->isVolatile(); 1992 1993 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1994 // Some targets pretend to have an i1 loading operation, and actually 1995 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1996 // bits are guaranteed to be zero; it helps the optimizers understand 1997 // that these bits are zero. It is also useful for EXTLOAD, since it 1998 // tells the optimizers that those bits are undefined. It would be 1999 // nice to have an effective generic way of getting these benefits... 2000 // Until such a way is found, don't insist on promoting i1 here. 2001 (SrcVT != MVT::i1 || 2002 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2003 // Promote to a byte-sized load if not loading an integral number of 2004 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2005 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 2006 MVT NVT = MVT::getIntegerVT(NewWidth); 2007 SDOperand Ch; 2008 2009 // The extra bits are guaranteed to be zero, since we stored them that 2010 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2011 2012 ISD::LoadExtType NewExtType = 2013 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2014 2015 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2016 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2017 NVT, isVolatile, Alignment); 2018 2019 Ch = Result.getValue(1); // The chain. 2020 2021 if (ExtType == ISD::SEXTLOAD) 2022 // Having the top bits zero doesn't help when sign extending. 2023 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2024 Result, DAG.getValueType(SrcVT)); 2025 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2026 // All the top bits are guaranteed to be zero - inform the optimizers. 2027 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2028 DAG.getValueType(SrcVT)); 2029 2030 Tmp1 = LegalizeOp(Result); 2031 Tmp2 = LegalizeOp(Ch); 2032 } else if (SrcWidth & (SrcWidth - 1)) { 2033 // If not loading a power-of-2 number of bits, expand as two loads. 2034 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2035 "Unsupported extload!"); 2036 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2037 assert(RoundWidth < SrcWidth); 2038 unsigned ExtraWidth = SrcWidth - RoundWidth; 2039 assert(ExtraWidth < RoundWidth); 2040 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2041 "Load size not an integral number of bytes!"); 2042 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2043 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2044 SDOperand Lo, Hi, Ch; 2045 unsigned IncrementSize; 2046 2047 if (TLI.isLittleEndian()) { 2048 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2049 // Load the bottom RoundWidth bits. 2050 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2051 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2052 Alignment); 2053 2054 // Load the remaining ExtraWidth bits. 2055 IncrementSize = RoundWidth / 8; 2056 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2057 DAG.getIntPtrConstant(IncrementSize)); 2058 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2059 LD->getSrcValue(), SVOffset + IncrementSize, 2060 ExtraVT, isVolatile, 2061 MinAlign(Alignment, IncrementSize)); 2062 2063 // Build a factor node to remember that this load is independent of the 2064 // other one. 2065 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2066 Hi.getValue(1)); 2067 2068 // Move the top bits to the right place. 2069 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2070 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2071 2072 // Join the hi and lo parts. 2073 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2074 } else { 2075 // Big endian - avoid unaligned loads. 2076 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2077 // Load the top RoundWidth bits. 2078 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2079 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2080 Alignment); 2081 2082 // Load the remaining ExtraWidth bits. 2083 IncrementSize = RoundWidth / 8; 2084 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2085 DAG.getIntPtrConstant(IncrementSize)); 2086 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2087 LD->getSrcValue(), SVOffset + IncrementSize, 2088 ExtraVT, isVolatile, 2089 MinAlign(Alignment, IncrementSize)); 2090 2091 // Build a factor node to remember that this load is independent of the 2092 // other one. 2093 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2094 Hi.getValue(1)); 2095 2096 // Move the top bits to the right place. 2097 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2098 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2099 2100 // Join the hi and lo parts. 2101 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2102 } 2103 2104 Tmp1 = LegalizeOp(Result); 2105 Tmp2 = LegalizeOp(Ch); 2106 } else { 2107 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2108 default: assert(0 && "This action is not supported yet!"); 2109 case TargetLowering::Custom: 2110 isCustom = true; 2111 // FALLTHROUGH 2112 case TargetLowering::Legal: 2113 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2114 Tmp1 = Result.getValue(0); 2115 Tmp2 = Result.getValue(1); 2116 2117 if (isCustom) { 2118 Tmp3 = TLI.LowerOperation(Result, DAG); 2119 if (Tmp3.Val) { 2120 Tmp1 = LegalizeOp(Tmp3); 2121 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2122 } 2123 } else { 2124 // If this is an unaligned load and the target doesn't support it, 2125 // expand it. 2126 if (!TLI.allowsUnalignedMemoryAccesses()) { 2127 unsigned ABIAlignment = TLI.getTargetData()-> 2128 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2129 if (LD->getAlignment() < ABIAlignment){ 2130 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2131 TLI); 2132 Tmp1 = Result.getOperand(0); 2133 Tmp2 = Result.getOperand(1); 2134 Tmp1 = LegalizeOp(Tmp1); 2135 Tmp2 = LegalizeOp(Tmp2); 2136 } 2137 } 2138 } 2139 break; 2140 case TargetLowering::Expand: 2141 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2142 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2143 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2144 LD->getSrcValueOffset(), 2145 LD->isVolatile(), LD->getAlignment()); 2146 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2147 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2148 Tmp2 = LegalizeOp(Load.getValue(1)); 2149 break; 2150 } 2151 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2152 // Turn the unsupported load into an EXTLOAD followed by an explicit 2153 // zero/sign extend inreg. 2154 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2155 Tmp1, Tmp2, LD->getSrcValue(), 2156 LD->getSrcValueOffset(), SrcVT, 2157 LD->isVolatile(), LD->getAlignment()); 2158 SDOperand ValRes; 2159 if (ExtType == ISD::SEXTLOAD) 2160 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2161 Result, DAG.getValueType(SrcVT)); 2162 else 2163 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2164 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2165 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2166 break; 2167 } 2168 } 2169 2170 // Since loads produce two values, make sure to remember that we legalized 2171 // both of them. 2172 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2173 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2174 return Op.ResNo ? Tmp2 : Tmp1; 2175 } 2176 } 2177 case ISD::EXTRACT_ELEMENT: { 2178 MVT OpTy = Node->getOperand(0).getValueType(); 2179 switch (getTypeAction(OpTy)) { 2180 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2181 case Legal: 2182 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2183 // 1 -> Hi 2184 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2185 DAG.getConstant(OpTy.getSizeInBits()/2, 2186 TLI.getShiftAmountTy())); 2187 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2188 } else { 2189 // 0 -> Lo 2190 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2191 Node->getOperand(0)); 2192 } 2193 break; 2194 case Expand: 2195 // Get both the low and high parts. 2196 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2197 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2198 Result = Tmp2; // 1 -> Hi 2199 else 2200 Result = Tmp1; // 0 -> Lo 2201 break; 2202 } 2203 break; 2204 } 2205 2206 case ISD::CopyToReg: 2207 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2208 2209 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2210 "Register type must be legal!"); 2211 // Legalize the incoming value (must be a legal type). 2212 Tmp2 = LegalizeOp(Node->getOperand(2)); 2213 if (Node->getNumValues() == 1) { 2214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2215 } else { 2216 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2217 if (Node->getNumOperands() == 4) { 2218 Tmp3 = LegalizeOp(Node->getOperand(3)); 2219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2220 Tmp3); 2221 } else { 2222 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2223 } 2224 2225 // Since this produces two values, make sure to remember that we legalized 2226 // both of them. 2227 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2228 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2229 return Result; 2230 } 2231 break; 2232 2233 case ISD::RET: 2234 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2235 2236 // Ensure that libcalls are emitted before a return. 2237 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2238 Tmp1 = LegalizeOp(Tmp1); 2239 LastCALLSEQ_END = DAG.getEntryNode(); 2240 2241 switch (Node->getNumOperands()) { 2242 case 3: // ret val 2243 Tmp2 = Node->getOperand(1); 2244 Tmp3 = Node->getOperand(2); // Signness 2245 switch (getTypeAction(Tmp2.getValueType())) { 2246 case Legal: 2247 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2248 break; 2249 case Expand: 2250 if (!Tmp2.getValueType().isVector()) { 2251 SDOperand Lo, Hi; 2252 ExpandOp(Tmp2, Lo, Hi); 2253 2254 // Big endian systems want the hi reg first. 2255 if (TLI.isBigEndian()) 2256 std::swap(Lo, Hi); 2257 2258 if (Hi.Val) 2259 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2260 else 2261 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2262 Result = LegalizeOp(Result); 2263 } else { 2264 SDNode *InVal = Tmp2.Val; 2265 int InIx = Tmp2.ResNo; 2266 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2267 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2268 2269 // Figure out if there is a simple type corresponding to this Vector 2270 // type. If so, convert to the vector type. 2271 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2272 if (TLI.isTypeLegal(TVT)) { 2273 // Turn this into a return of the vector type. 2274 Tmp2 = LegalizeOp(Tmp2); 2275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2276 } else if (NumElems == 1) { 2277 // Turn this into a return of the scalar type. 2278 Tmp2 = ScalarizeVectorOp(Tmp2); 2279 Tmp2 = LegalizeOp(Tmp2); 2280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2281 2282 // FIXME: Returns of gcc generic vectors smaller than a legal type 2283 // should be returned in integer registers! 2284 2285 // The scalarized value type may not be legal, e.g. it might require 2286 // promotion or expansion. Relegalize the return. 2287 Result = LegalizeOp(Result); 2288 } else { 2289 // FIXME: Returns of gcc generic vectors larger than a legal vector 2290 // type should be returned by reference! 2291 SDOperand Lo, Hi; 2292 SplitVectorOp(Tmp2, Lo, Hi); 2293 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2294 Result = LegalizeOp(Result); 2295 } 2296 } 2297 break; 2298 case Promote: 2299 Tmp2 = PromoteOp(Node->getOperand(1)); 2300 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2301 Result = LegalizeOp(Result); 2302 break; 2303 } 2304 break; 2305 case 1: // ret void 2306 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2307 break; 2308 default: { // ret <values> 2309 SmallVector<SDOperand, 8> NewValues; 2310 NewValues.push_back(Tmp1); 2311 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2312 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2313 case Legal: 2314 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2315 NewValues.push_back(Node->getOperand(i+1)); 2316 break; 2317 case Expand: { 2318 SDOperand Lo, Hi; 2319 assert(!Node->getOperand(i).getValueType().isExtended() && 2320 "FIXME: TODO: implement returning non-legal vector types!"); 2321 ExpandOp(Node->getOperand(i), Lo, Hi); 2322 NewValues.push_back(Lo); 2323 NewValues.push_back(Node->getOperand(i+1)); 2324 if (Hi.Val) { 2325 NewValues.push_back(Hi); 2326 NewValues.push_back(Node->getOperand(i+1)); 2327 } 2328 break; 2329 } 2330 case Promote: 2331 assert(0 && "Can't promote multiple return value yet!"); 2332 } 2333 2334 if (NewValues.size() == Node->getNumOperands()) 2335 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2336 else 2337 Result = DAG.getNode(ISD::RET, MVT::Other, 2338 &NewValues[0], NewValues.size()); 2339 break; 2340 } 2341 } 2342 2343 if (Result.getOpcode() == ISD::RET) { 2344 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2345 default: assert(0 && "This action is not supported yet!"); 2346 case TargetLowering::Legal: break; 2347 case TargetLowering::Custom: 2348 Tmp1 = TLI.LowerOperation(Result, DAG); 2349 if (Tmp1.Val) Result = Tmp1; 2350 break; 2351 } 2352 } 2353 break; 2354 case ISD::STORE: { 2355 StoreSDNode *ST = cast<StoreSDNode>(Node); 2356 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2357 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2358 int SVOffset = ST->getSrcValueOffset(); 2359 unsigned Alignment = ST->getAlignment(); 2360 bool isVolatile = ST->isVolatile(); 2361 2362 if (!ST->isTruncatingStore()) { 2363 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2364 // FIXME: We shouldn't do this for TargetConstantFP's. 2365 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2366 // to phase ordering between legalized code and the dag combiner. This 2367 // probably means that we need to integrate dag combiner and legalizer 2368 // together. 2369 // We generally can't do this one for long doubles. 2370 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2371 if (CFP->getValueType(0) == MVT::f32 && 2372 getTypeAction(MVT::i32) == Legal) { 2373 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2374 convertToAPInt().zextOrTrunc(32), 2375 MVT::i32); 2376 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2377 SVOffset, isVolatile, Alignment); 2378 break; 2379 } else if (CFP->getValueType(0) == MVT::f64) { 2380 // If this target supports 64-bit registers, do a single 64-bit store. 2381 if (getTypeAction(MVT::i64) == Legal) { 2382 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2383 zextOrTrunc(64), MVT::i64); 2384 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2385 SVOffset, isVolatile, Alignment); 2386 break; 2387 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2388 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2389 // stores. If the target supports neither 32- nor 64-bits, this 2390 // xform is certainly not worth it. 2391 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2392 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2393 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2394 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2395 2396 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2397 SVOffset, isVolatile, Alignment); 2398 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2399 DAG.getIntPtrConstant(4)); 2400 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2401 isVolatile, MinAlign(Alignment, 4U)); 2402 2403 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2404 break; 2405 } 2406 } 2407 } 2408 2409 switch (getTypeAction(ST->getMemoryVT())) { 2410 case Legal: { 2411 Tmp3 = LegalizeOp(ST->getValue()); 2412 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2413 ST->getOffset()); 2414 2415 MVT VT = Tmp3.getValueType(); 2416 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2417 default: assert(0 && "This action is not supported yet!"); 2418 case TargetLowering::Legal: 2419 // If this is an unaligned store and the target doesn't support it, 2420 // expand it. 2421 if (!TLI.allowsUnalignedMemoryAccesses()) { 2422 unsigned ABIAlignment = TLI.getTargetData()-> 2423 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2424 if (ST->getAlignment() < ABIAlignment) 2425 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2426 TLI); 2427 } 2428 break; 2429 case TargetLowering::Custom: 2430 Tmp1 = TLI.LowerOperation(Result, DAG); 2431 if (Tmp1.Val) Result = Tmp1; 2432 break; 2433 case TargetLowering::Promote: 2434 assert(VT.isVector() && "Unknown legal promote case!"); 2435 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2436 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2437 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2438 ST->getSrcValue(), SVOffset, isVolatile, 2439 Alignment); 2440 break; 2441 } 2442 break; 2443 } 2444 case Promote: 2445 // Truncate the value and store the result. 2446 Tmp3 = PromoteOp(ST->getValue()); 2447 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2448 SVOffset, ST->getMemoryVT(), 2449 isVolatile, Alignment); 2450 break; 2451 2452 case Expand: 2453 unsigned IncrementSize = 0; 2454 SDOperand Lo, Hi; 2455 2456 // If this is a vector type, then we have to calculate the increment as 2457 // the product of the element size in bytes, and the number of elements 2458 // in the high half of the vector. 2459 if (ST->getValue().getValueType().isVector()) { 2460 SDNode *InVal = ST->getValue().Val; 2461 int InIx = ST->getValue().ResNo; 2462 MVT InVT = InVal->getValueType(InIx); 2463 unsigned NumElems = InVT.getVectorNumElements(); 2464 MVT EVT = InVT.getVectorElementType(); 2465 2466 // Figure out if there is a simple type corresponding to this Vector 2467 // type. If so, convert to the vector type. 2468 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2469 if (TLI.isTypeLegal(TVT)) { 2470 // Turn this into a normal store of the vector type. 2471 Tmp3 = LegalizeOp(ST->getValue()); 2472 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2473 SVOffset, isVolatile, Alignment); 2474 Result = LegalizeOp(Result); 2475 break; 2476 } else if (NumElems == 1) { 2477 // Turn this into a normal store of the scalar type. 2478 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2479 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2480 SVOffset, isVolatile, Alignment); 2481 // The scalarized value type may not be legal, e.g. it might require 2482 // promotion or expansion. Relegalize the scalar store. 2483 Result = LegalizeOp(Result); 2484 break; 2485 } else { 2486 SplitVectorOp(ST->getValue(), Lo, Hi); 2487 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * 2488 EVT.getSizeInBits()/8; 2489 } 2490 } else { 2491 ExpandOp(ST->getValue(), Lo, Hi); 2492 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; 2493 2494 if (TLI.isBigEndian()) 2495 std::swap(Lo, Hi); 2496 } 2497 2498 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2499 SVOffset, isVolatile, Alignment); 2500 2501 if (Hi.Val == NULL) { 2502 // Must be int <-> float one-to-one expansion. 2503 Result = Lo; 2504 break; 2505 } 2506 2507 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2508 DAG.getIntPtrConstant(IncrementSize)); 2509 assert(isTypeLegal(Tmp2.getValueType()) && 2510 "Pointers must be legal!"); 2511 SVOffset += IncrementSize; 2512 Alignment = MinAlign(Alignment, IncrementSize); 2513 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2514 SVOffset, isVolatile, Alignment); 2515 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2516 break; 2517 } 2518 } else { 2519 switch (getTypeAction(ST->getValue().getValueType())) { 2520 case Legal: 2521 Tmp3 = LegalizeOp(ST->getValue()); 2522 break; 2523 case Promote: 2524 // We can promote the value, the truncstore will still take care of it. 2525 Tmp3 = PromoteOp(ST->getValue()); 2526 break; 2527 case Expand: 2528 // Just store the low part. This may become a non-trunc store, so make 2529 // sure to use getTruncStore, not UpdateNodeOperands below. 2530 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2531 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2532 SVOffset, MVT::i8, isVolatile, Alignment); 2533 } 2534 2535 MVT StVT = ST->getMemoryVT(); 2536 unsigned StWidth = StVT.getSizeInBits(); 2537 2538 if (StWidth != StVT.getStoreSizeInBits()) { 2539 // Promote to a byte-sized store with upper bits zero if not 2540 // storing an integral number of bytes. For example, promote 2541 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2542 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2543 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2544 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2545 SVOffset, NVT, isVolatile, Alignment); 2546 } else if (StWidth & (StWidth - 1)) { 2547 // If not storing a power-of-2 number of bits, expand as two stores. 2548 assert(StVT.isExtended() && !StVT.isVector() && 2549 "Unsupported truncstore!"); 2550 unsigned RoundWidth = 1 << Log2_32(StWidth); 2551 assert(RoundWidth < StWidth); 2552 unsigned ExtraWidth = StWidth - RoundWidth; 2553 assert(ExtraWidth < RoundWidth); 2554 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2555 "Store size not an integral number of bytes!"); 2556 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2557 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2558 SDOperand Lo, Hi; 2559 unsigned IncrementSize; 2560 2561 if (TLI.isLittleEndian()) { 2562 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2563 // Store the bottom RoundWidth bits. 2564 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2565 SVOffset, RoundVT, 2566 isVolatile, Alignment); 2567 2568 // Store the remaining ExtraWidth bits. 2569 IncrementSize = RoundWidth / 8; 2570 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2571 DAG.getIntPtrConstant(IncrementSize)); 2572 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2573 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2574 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2575 SVOffset + IncrementSize, ExtraVT, isVolatile, 2576 MinAlign(Alignment, IncrementSize)); 2577 } else { 2578 // Big endian - avoid unaligned stores. 2579 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2580 // Store the top RoundWidth bits. 2581 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2582 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2583 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2584 RoundVT, isVolatile, Alignment); 2585 2586 // Store the remaining ExtraWidth bits. 2587 IncrementSize = RoundWidth / 8; 2588 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2589 DAG.getIntPtrConstant(IncrementSize)); 2590 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2591 SVOffset + IncrementSize, ExtraVT, isVolatile, 2592 MinAlign(Alignment, IncrementSize)); 2593 } 2594 2595 // The order of the stores doesn't matter. 2596 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2597 } else { 2598 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2599 Tmp2 != ST->getBasePtr()) 2600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2601 ST->getOffset()); 2602 2603 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2604 default: assert(0 && "This action is not supported yet!"); 2605 case TargetLowering::Legal: 2606 // If this is an unaligned store and the target doesn't support it, 2607 // expand it. 2608 if (!TLI.allowsUnalignedMemoryAccesses()) { 2609 unsigned ABIAlignment = TLI.getTargetData()-> 2610 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2611 if (ST->getAlignment() < ABIAlignment) 2612 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2613 TLI); 2614 } 2615 break; 2616 case TargetLowering::Custom: 2617 Result = TLI.LowerOperation(Result, DAG); 2618 break; 2619 case Expand: 2620 // TRUNCSTORE:i16 i32 -> STORE i16 2621 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2622 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2623 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2624 isVolatile, Alignment); 2625 break; 2626 } 2627 } 2628 } 2629 break; 2630 } 2631 case ISD::PCMARKER: 2632 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2634 break; 2635 case ISD::STACKSAVE: 2636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2637 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2638 Tmp1 = Result.getValue(0); 2639 Tmp2 = Result.getValue(1); 2640 2641 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2642 default: assert(0 && "This action is not supported yet!"); 2643 case TargetLowering::Legal: break; 2644 case TargetLowering::Custom: 2645 Tmp3 = TLI.LowerOperation(Result, DAG); 2646 if (Tmp3.Val) { 2647 Tmp1 = LegalizeOp(Tmp3); 2648 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2649 } 2650 break; 2651 case TargetLowering::Expand: 2652 // Expand to CopyFromReg if the target set 2653 // StackPointerRegisterToSaveRestore. 2654 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2655 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2656 Node->getValueType(0)); 2657 Tmp2 = Tmp1.getValue(1); 2658 } else { 2659 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2660 Tmp2 = Node->getOperand(0); 2661 } 2662 break; 2663 } 2664 2665 // Since stacksave produce two values, make sure to remember that we 2666 // legalized both of them. 2667 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2668 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2669 return Op.ResNo ? Tmp2 : Tmp1; 2670 2671 case ISD::STACKRESTORE: 2672 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2673 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2674 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2675 2676 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2677 default: assert(0 && "This action is not supported yet!"); 2678 case TargetLowering::Legal: break; 2679 case TargetLowering::Custom: 2680 Tmp1 = TLI.LowerOperation(Result, DAG); 2681 if (Tmp1.Val) Result = Tmp1; 2682 break; 2683 case TargetLowering::Expand: 2684 // Expand to CopyToReg if the target set 2685 // StackPointerRegisterToSaveRestore. 2686 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2687 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2688 } else { 2689 Result = Tmp1; 2690 } 2691 break; 2692 } 2693 break; 2694 2695 case ISD::READCYCLECOUNTER: 2696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2697 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2698 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2699 Node->getValueType(0))) { 2700 default: assert(0 && "This action is not supported yet!"); 2701 case TargetLowering::Legal: 2702 Tmp1 = Result.getValue(0); 2703 Tmp2 = Result.getValue(1); 2704 break; 2705 case TargetLowering::Custom: 2706 Result = TLI.LowerOperation(Result, DAG); 2707 Tmp1 = LegalizeOp(Result.getValue(0)); 2708 Tmp2 = LegalizeOp(Result.getValue(1)); 2709 break; 2710 } 2711 2712 // Since rdcc produce two values, make sure to remember that we legalized 2713 // both of them. 2714 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2715 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2716 return Result; 2717 2718 case ISD::SELECT: 2719 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2720 case Expand: assert(0 && "It's impossible to expand bools"); 2721 case Legal: 2722 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2723 break; 2724 case Promote: { 2725 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2726 // Make sure the condition is either zero or one. 2727 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2728 if (!DAG.MaskedValueIsZero(Tmp1, 2729 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2730 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2731 break; 2732 } 2733 } 2734 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2735 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2736 2737 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2738 2739 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2740 default: assert(0 && "This action is not supported yet!"); 2741 case TargetLowering::Legal: break; 2742 case TargetLowering::Custom: { 2743 Tmp1 = TLI.LowerOperation(Result, DAG); 2744 if (Tmp1.Val) Result = Tmp1; 2745 break; 2746 } 2747 case TargetLowering::Expand: 2748 if (Tmp1.getOpcode() == ISD::SETCC) { 2749 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2750 Tmp2, Tmp3, 2751 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2752 } else { 2753 Result = DAG.getSelectCC(Tmp1, 2754 DAG.getConstant(0, Tmp1.getValueType()), 2755 Tmp2, Tmp3, ISD::SETNE); 2756 } 2757 break; 2758 case TargetLowering::Promote: { 2759 MVT NVT = 2760 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2761 unsigned ExtOp, TruncOp; 2762 if (Tmp2.getValueType().isVector()) { 2763 ExtOp = ISD::BIT_CONVERT; 2764 TruncOp = ISD::BIT_CONVERT; 2765 } else if (Tmp2.getValueType().isInteger()) { 2766 ExtOp = ISD::ANY_EXTEND; 2767 TruncOp = ISD::TRUNCATE; 2768 } else { 2769 ExtOp = ISD::FP_EXTEND; 2770 TruncOp = ISD::FP_ROUND; 2771 } 2772 // Promote each of the values to the new type. 2773 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2774 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2775 // Perform the larger operation, then round down. 2776 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2777 if (TruncOp != ISD::FP_ROUND) 2778 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2779 else 2780 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2781 DAG.getIntPtrConstant(0)); 2782 break; 2783 } 2784 } 2785 break; 2786 case ISD::SELECT_CC: { 2787 Tmp1 = Node->getOperand(0); // LHS 2788 Tmp2 = Node->getOperand(1); // RHS 2789 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2790 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2791 SDOperand CC = Node->getOperand(4); 2792 2793 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2794 2795 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2796 // the LHS is a legal SETCC itself. In this case, we need to compare 2797 // the result against zero to select between true and false values. 2798 if (Tmp2.Val == 0) { 2799 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2800 CC = DAG.getCondCode(ISD::SETNE); 2801 } 2802 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2803 2804 // Everything is legal, see if we should expand this op or something. 2805 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2806 default: assert(0 && "This action is not supported yet!"); 2807 case TargetLowering::Legal: break; 2808 case TargetLowering::Custom: 2809 Tmp1 = TLI.LowerOperation(Result, DAG); 2810 if (Tmp1.Val) Result = Tmp1; 2811 break; 2812 } 2813 break; 2814 } 2815 case ISD::SETCC: 2816 Tmp1 = Node->getOperand(0); 2817 Tmp2 = Node->getOperand(1); 2818 Tmp3 = Node->getOperand(2); 2819 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2820 2821 // If we had to Expand the SetCC operands into a SELECT node, then it may 2822 // not always be possible to return a true LHS & RHS. In this case, just 2823 // return the value we legalized, returned in the LHS 2824 if (Tmp2.Val == 0) { 2825 Result = Tmp1; 2826 break; 2827 } 2828 2829 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2830 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2831 case TargetLowering::Custom: 2832 isCustom = true; 2833 // FALLTHROUGH. 2834 case TargetLowering::Legal: 2835 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2836 if (isCustom) { 2837 Tmp4 = TLI.LowerOperation(Result, DAG); 2838 if (Tmp4.Val) Result = Tmp4; 2839 } 2840 break; 2841 case TargetLowering::Promote: { 2842 // First step, figure out the appropriate operation to use. 2843 // Allow SETCC to not be supported for all legal data types 2844 // Mostly this targets FP 2845 MVT NewInTy = Node->getOperand(0).getValueType(); 2846 MVT OldVT = NewInTy; OldVT = OldVT; 2847 2848 // Scan for the appropriate larger type to use. 2849 while (1) { 2850 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2851 2852 assert(NewInTy.isInteger() == OldVT.isInteger() && 2853 "Fell off of the edge of the integer world"); 2854 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 2855 "Fell off of the edge of the floating point world"); 2856 2857 // If the target supports SETCC of this type, use it. 2858 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2859 break; 2860 } 2861 if (NewInTy.isInteger()) 2862 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2863 else { 2864 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2865 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2866 } 2867 Tmp1 = LegalizeOp(Tmp1); 2868 Tmp2 = LegalizeOp(Tmp2); 2869 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2870 Result = LegalizeOp(Result); 2871 break; 2872 } 2873 case TargetLowering::Expand: 2874 // Expand a setcc node into a select_cc of the same condition, lhs, and 2875 // rhs that selects between const 1 (true) and const 0 (false). 2876 MVT VT = Node->getValueType(0); 2877 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2878 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2879 Tmp3); 2880 break; 2881 } 2882 break; 2883 case ISD::VSETCC: { 2884 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2885 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2886 SDOperand CC = Node->getOperand(2); 2887 2888 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2889 2890 // Everything is legal, see if we should expand this op or something. 2891 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2892 default: assert(0 && "This action is not supported yet!"); 2893 case TargetLowering::Legal: break; 2894 case TargetLowering::Custom: 2895 Tmp1 = TLI.LowerOperation(Result, DAG); 2896 if (Tmp1.Val) Result = Tmp1; 2897 break; 2898 } 2899 break; 2900 } 2901 2902 case ISD::SHL_PARTS: 2903 case ISD::SRA_PARTS: 2904 case ISD::SRL_PARTS: { 2905 SmallVector<SDOperand, 8> Ops; 2906 bool Changed = false; 2907 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2908 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2909 Changed |= Ops.back() != Node->getOperand(i); 2910 } 2911 if (Changed) 2912 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2913 2914 switch (TLI.getOperationAction(Node->getOpcode(), 2915 Node->getValueType(0))) { 2916 default: assert(0 && "This action is not supported yet!"); 2917 case TargetLowering::Legal: break; 2918 case TargetLowering::Custom: 2919 Tmp1 = TLI.LowerOperation(Result, DAG); 2920 if (Tmp1.Val) { 2921 SDOperand Tmp2, RetVal(0, 0); 2922 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2923 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2924 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2925 if (i == Op.ResNo) 2926 RetVal = Tmp2; 2927 } 2928 assert(RetVal.Val && "Illegal result number"); 2929 return RetVal; 2930 } 2931 break; 2932 } 2933 2934 // Since these produce multiple values, make sure to remember that we 2935 // legalized all of them. 2936 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2937 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2938 return Result.getValue(Op.ResNo); 2939 } 2940 2941 // Binary operators 2942 case ISD::ADD: 2943 case ISD::SUB: 2944 case ISD::MUL: 2945 case ISD::MULHS: 2946 case ISD::MULHU: 2947 case ISD::UDIV: 2948 case ISD::SDIV: 2949 case ISD::AND: 2950 case ISD::OR: 2951 case ISD::XOR: 2952 case ISD::SHL: 2953 case ISD::SRL: 2954 case ISD::SRA: 2955 case ISD::FADD: 2956 case ISD::FSUB: 2957 case ISD::FMUL: 2958 case ISD::FDIV: 2959 case ISD::FPOW: 2960 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2961 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2962 case Expand: assert(0 && "Not possible"); 2963 case Legal: 2964 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2965 break; 2966 case Promote: 2967 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2968 break; 2969 } 2970 2971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2972 2973 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2974 default: assert(0 && "BinOp legalize operation not supported"); 2975 case TargetLowering::Legal: break; 2976 case TargetLowering::Custom: 2977 Tmp1 = TLI.LowerOperation(Result, DAG); 2978 if (Tmp1.Val) Result = Tmp1; 2979 break; 2980 case TargetLowering::Expand: { 2981 MVT VT = Op.getValueType(); 2982 2983 // See if multiply or divide can be lowered using two-result operations. 2984 SDVTList VTs = DAG.getVTList(VT, VT); 2985 if (Node->getOpcode() == ISD::MUL) { 2986 // We just need the low half of the multiply; try both the signed 2987 // and unsigned forms. If the target supports both SMUL_LOHI and 2988 // UMUL_LOHI, form a preference by checking which forms of plain 2989 // MULH it supports. 2990 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2991 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2992 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2993 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2994 unsigned OpToUse = 0; 2995 if (HasSMUL_LOHI && !HasMULHS) { 2996 OpToUse = ISD::SMUL_LOHI; 2997 } else if (HasUMUL_LOHI && !HasMULHU) { 2998 OpToUse = ISD::UMUL_LOHI; 2999 } else if (HasSMUL_LOHI) { 3000 OpToUse = ISD::SMUL_LOHI; 3001 } else if (HasUMUL_LOHI) { 3002 OpToUse = ISD::UMUL_LOHI; 3003 } 3004 if (OpToUse) { 3005 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 3006 break; 3007 } 3008 } 3009 if (Node->getOpcode() == ISD::MULHS && 3010 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3011 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3012 break; 3013 } 3014 if (Node->getOpcode() == ISD::MULHU && 3015 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3016 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3017 break; 3018 } 3019 if (Node->getOpcode() == ISD::SDIV && 3020 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3021 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3022 break; 3023 } 3024 if (Node->getOpcode() == ISD::UDIV && 3025 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3026 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3027 break; 3028 } 3029 3030 // Check to see if we have a libcall for this operator. 3031 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3032 bool isSigned = false; 3033 switch (Node->getOpcode()) { 3034 case ISD::UDIV: 3035 case ISD::SDIV: 3036 if (VT == MVT::i32) { 3037 LC = Node->getOpcode() == ISD::UDIV 3038 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3039 isSigned = Node->getOpcode() == ISD::SDIV; 3040 } 3041 break; 3042 case ISD::FPOW: 3043 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3044 RTLIB::POW_PPCF128); 3045 break; 3046 default: break; 3047 } 3048 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3049 SDOperand Dummy; 3050 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3051 break; 3052 } 3053 3054 assert(Node->getValueType(0).isVector() && 3055 "Cannot expand this binary operator!"); 3056 // Expand the operation into a bunch of nasty scalar code. 3057 Result = LegalizeOp(UnrollVectorOp(Op)); 3058 break; 3059 } 3060 case TargetLowering::Promote: { 3061 switch (Node->getOpcode()) { 3062 default: assert(0 && "Do not know how to promote this BinOp!"); 3063 case ISD::AND: 3064 case ISD::OR: 3065 case ISD::XOR: { 3066 MVT OVT = Node->getValueType(0); 3067 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3068 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3069 // Bit convert each of the values to the new type. 3070 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3071 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3072 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3073 // Bit convert the result back the original type. 3074 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3075 break; 3076 } 3077 } 3078 } 3079 } 3080 break; 3081 3082 case ISD::SMUL_LOHI: 3083 case ISD::UMUL_LOHI: 3084 case ISD::SDIVREM: 3085 case ISD::UDIVREM: 3086 // These nodes will only be produced by target-specific lowering, so 3087 // they shouldn't be here if they aren't legal. 3088 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3089 "This must be legal!"); 3090 3091 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3092 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3093 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3094 break; 3095 3096 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3097 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3098 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3099 case Expand: assert(0 && "Not possible"); 3100 case Legal: 3101 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3102 break; 3103 case Promote: 3104 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3105 break; 3106 } 3107 3108 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3109 3110 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3111 default: assert(0 && "Operation not supported"); 3112 case TargetLowering::Custom: 3113 Tmp1 = TLI.LowerOperation(Result, DAG); 3114 if (Tmp1.Val) Result = Tmp1; 3115 break; 3116 case TargetLowering::Legal: break; 3117 case TargetLowering::Expand: { 3118 // If this target supports fabs/fneg natively and select is cheap, 3119 // do this efficiently. 3120 if (!TLI.isSelectExpensive() && 3121 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3122 TargetLowering::Legal && 3123 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3124 TargetLowering::Legal) { 3125 // Get the sign bit of the RHS. 3126 MVT IVT = 3127 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3128 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3129 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3130 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3131 // Get the absolute value of the result. 3132 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3133 // Select between the nabs and abs value based on the sign bit of 3134 // the input. 3135 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3136 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3137 AbsVal), 3138 AbsVal); 3139 Result = LegalizeOp(Result); 3140 break; 3141 } 3142 3143 // Otherwise, do bitwise ops! 3144 MVT NVT = 3145 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3146 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3147 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3148 Result = LegalizeOp(Result); 3149 break; 3150 } 3151 } 3152 break; 3153 3154 case ISD::ADDC: 3155 case ISD::SUBC: 3156 Tmp1 = LegalizeOp(Node->getOperand(0)); 3157 Tmp2 = LegalizeOp(Node->getOperand(1)); 3158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3159 // Since this produces two values, make sure to remember that we legalized 3160 // both of them. 3161 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3162 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3163 return Result; 3164 3165 case ISD::ADDE: 3166 case ISD::SUBE: 3167 Tmp1 = LegalizeOp(Node->getOperand(0)); 3168 Tmp2 = LegalizeOp(Node->getOperand(1)); 3169 Tmp3 = LegalizeOp(Node->getOperand(2)); 3170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3171 // Since this produces two values, make sure to remember that we legalized 3172 // both of them. 3173 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3174 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3175 return Result; 3176 3177 case ISD::BUILD_PAIR: { 3178 MVT PairTy = Node->getValueType(0); 3179 // TODO: handle the case where the Lo and Hi operands are not of legal type 3180 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3181 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3182 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3183 case TargetLowering::Promote: 3184 case TargetLowering::Custom: 3185 assert(0 && "Cannot promote/custom this yet!"); 3186 case TargetLowering::Legal: 3187 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3188 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3189 break; 3190 case TargetLowering::Expand: 3191 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3192 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3193 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3194 DAG.getConstant(PairTy.getSizeInBits()/2, 3195 TLI.getShiftAmountTy())); 3196 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3197 break; 3198 } 3199 break; 3200 } 3201 3202 case ISD::UREM: 3203 case ISD::SREM: 3204 case ISD::FREM: 3205 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3206 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3207 3208 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3209 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3210 case TargetLowering::Custom: 3211 isCustom = true; 3212 // FALLTHROUGH 3213 case TargetLowering::Legal: 3214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3215 if (isCustom) { 3216 Tmp1 = TLI.LowerOperation(Result, DAG); 3217 if (Tmp1.Val) Result = Tmp1; 3218 } 3219 break; 3220 case TargetLowering::Expand: { 3221 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3222 bool isSigned = DivOpc == ISD::SDIV; 3223 MVT VT = Node->getValueType(0); 3224 3225 // See if remainder can be lowered using two-result operations. 3226 SDVTList VTs = DAG.getVTList(VT, VT); 3227 if (Node->getOpcode() == ISD::SREM && 3228 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3229 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3230 break; 3231 } 3232 if (Node->getOpcode() == ISD::UREM && 3233 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3234 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3235 break; 3236 } 3237 3238 if (VT.isInteger()) { 3239 if (TLI.getOperationAction(DivOpc, VT) == 3240 TargetLowering::Legal) { 3241 // X % Y -> X-X/Y*Y 3242 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3243 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3244 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3245 } else if (VT.isVector()) { 3246 Result = LegalizeOp(UnrollVectorOp(Op)); 3247 } else { 3248 assert(VT == MVT::i32 && 3249 "Cannot expand this binary operator!"); 3250 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3251 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3252 SDOperand Dummy; 3253 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3254 } 3255 } else { 3256 assert(VT.isFloatingPoint() && 3257 "remainder op must have integer or floating-point type"); 3258 if (VT.isVector()) { 3259 Result = LegalizeOp(UnrollVectorOp(Op)); 3260 } else { 3261 // Floating point mod -> fmod libcall. 3262 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3263 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3264 SDOperand Dummy; 3265 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3266 } 3267 } 3268 break; 3269 } 3270 } 3271 break; 3272 case ISD::VAARG: { 3273 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3274 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3275 3276 MVT VT = Node->getValueType(0); 3277 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3278 default: assert(0 && "This action is not supported yet!"); 3279 case TargetLowering::Custom: 3280 isCustom = true; 3281 // FALLTHROUGH 3282 case TargetLowering::Legal: 3283 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3284 Result = Result.getValue(0); 3285 Tmp1 = Result.getValue(1); 3286 3287 if (isCustom) { 3288 Tmp2 = TLI.LowerOperation(Result, DAG); 3289 if (Tmp2.Val) { 3290 Result = LegalizeOp(Tmp2); 3291 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3292 } 3293 } 3294 break; 3295 case TargetLowering::Expand: { 3296 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3297 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3298 // Increment the pointer, VAList, to the next vaarg 3299 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3300 DAG.getConstant(VT.getSizeInBits()/8, 3301 TLI.getPointerTy())); 3302 // Store the incremented VAList to the legalized pointer 3303 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3304 // Load the actual argument out of the pointer VAList 3305 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3306 Tmp1 = LegalizeOp(Result.getValue(1)); 3307 Result = LegalizeOp(Result); 3308 break; 3309 } 3310 } 3311 // Since VAARG produces two values, make sure to remember that we 3312 // legalized both of them. 3313 AddLegalizedOperand(SDOperand(Node, 0), Result); 3314 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3315 return Op.ResNo ? Tmp1 : Result; 3316 } 3317 3318 case ISD::VACOPY: 3319 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3320 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3321 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3322 3323 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3324 default: assert(0 && "This action is not supported yet!"); 3325 case TargetLowering::Custom: 3326 isCustom = true; 3327 // FALLTHROUGH 3328 case TargetLowering::Legal: 3329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3330 Node->getOperand(3), Node->getOperand(4)); 3331 if (isCustom) { 3332 Tmp1 = TLI.LowerOperation(Result, DAG); 3333 if (Tmp1.Val) Result = Tmp1; 3334 } 3335 break; 3336 case TargetLowering::Expand: 3337 // This defaults to loading a pointer from the input and storing it to the 3338 // output, returning the chain. 3339 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3340 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3341 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3342 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3343 break; 3344 } 3345 break; 3346 3347 case ISD::VAEND: 3348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3349 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3350 3351 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3352 default: assert(0 && "This action is not supported yet!"); 3353 case TargetLowering::Custom: 3354 isCustom = true; 3355 // FALLTHROUGH 3356 case TargetLowering::Legal: 3357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3358 if (isCustom) { 3359 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3360 if (Tmp1.Val) Result = Tmp1; 3361 } 3362 break; 3363 case TargetLowering::Expand: 3364 Result = Tmp1; // Default to a no-op, return the chain 3365 break; 3366 } 3367 break; 3368 3369 case ISD::VASTART: 3370 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3371 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3372 3373 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3374 3375 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3376 default: assert(0 && "This action is not supported yet!"); 3377 case TargetLowering::Legal: break; 3378 case TargetLowering::Custom: 3379 Tmp1 = TLI.LowerOperation(Result, DAG); 3380 if (Tmp1.Val) Result = Tmp1; 3381 break; 3382 } 3383 break; 3384 3385 case ISD::ROTL: 3386 case ISD::ROTR: 3387 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3388 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3390 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3391 default: 3392 assert(0 && "ROTL/ROTR legalize operation not supported"); 3393 break; 3394 case TargetLowering::Legal: 3395 break; 3396 case TargetLowering::Custom: 3397 Tmp1 = TLI.LowerOperation(Result, DAG); 3398 if (Tmp1.Val) Result = Tmp1; 3399 break; 3400 case TargetLowering::Promote: 3401 assert(0 && "Do not know how to promote ROTL/ROTR"); 3402 break; 3403 case TargetLowering::Expand: 3404 assert(0 && "Do not know how to expand ROTL/ROTR"); 3405 break; 3406 } 3407 break; 3408 3409 case ISD::BSWAP: 3410 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3411 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3412 case TargetLowering::Custom: 3413 assert(0 && "Cannot custom legalize this yet!"); 3414 case TargetLowering::Legal: 3415 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3416 break; 3417 case TargetLowering::Promote: { 3418 MVT OVT = Tmp1.getValueType(); 3419 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3420 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3421 3422 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3423 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3424 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3425 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3426 break; 3427 } 3428 case TargetLowering::Expand: 3429 Result = ExpandBSWAP(Tmp1); 3430 break; 3431 } 3432 break; 3433 3434 case ISD::CTPOP: 3435 case ISD::CTTZ: 3436 case ISD::CTLZ: 3437 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3438 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3439 case TargetLowering::Custom: 3440 case TargetLowering::Legal: 3441 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3442 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3443 TargetLowering::Custom) { 3444 Tmp1 = TLI.LowerOperation(Result, DAG); 3445 if (Tmp1.Val) { 3446 Result = Tmp1; 3447 } 3448 } 3449 break; 3450 case TargetLowering::Promote: { 3451 MVT OVT = Tmp1.getValueType(); 3452 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3453 3454 // Zero extend the argument. 3455 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3456 // Perform the larger operation, then subtract if needed. 3457 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3458 switch (Node->getOpcode()) { 3459 case ISD::CTPOP: 3460 Result = Tmp1; 3461 break; 3462 case ISD::CTTZ: 3463 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3464 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3465 DAG.getConstant(NVT.getSizeInBits(), NVT), 3466 ISD::SETEQ); 3467 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3468 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3469 break; 3470 case ISD::CTLZ: 3471 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3472 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3473 DAG.getConstant(NVT.getSizeInBits() - 3474 OVT.getSizeInBits(), NVT)); 3475 break; 3476 } 3477 break; 3478 } 3479 case TargetLowering::Expand: 3480 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3481 break; 3482 } 3483 break; 3484 3485 // Unary operators 3486 case ISD::FABS: 3487 case ISD::FNEG: 3488 case ISD::FSQRT: 3489 case ISD::FSIN: 3490 case ISD::FCOS: 3491 Tmp1 = LegalizeOp(Node->getOperand(0)); 3492 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3493 case TargetLowering::Promote: 3494 case TargetLowering::Custom: 3495 isCustom = true; 3496 // FALLTHROUGH 3497 case TargetLowering::Legal: 3498 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3499 if (isCustom) { 3500 Tmp1 = TLI.LowerOperation(Result, DAG); 3501 if (Tmp1.Val) Result = Tmp1; 3502 } 3503 break; 3504 case TargetLowering::Expand: 3505 switch (Node->getOpcode()) { 3506 default: assert(0 && "Unreachable!"); 3507 case ISD::FNEG: 3508 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3509 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3510 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3511 break; 3512 case ISD::FABS: { 3513 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3514 MVT VT = Node->getValueType(0); 3515 Tmp2 = DAG.getConstantFP(0.0, VT); 3516 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3517 ISD::SETUGT); 3518 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3519 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3520 break; 3521 } 3522 case ISD::FSQRT: 3523 case ISD::FSIN: 3524 case ISD::FCOS: { 3525 MVT VT = Node->getValueType(0); 3526 3527 // Expand unsupported unary vector operators by unrolling them. 3528 if (VT.isVector()) { 3529 Result = LegalizeOp(UnrollVectorOp(Op)); 3530 break; 3531 } 3532 3533 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3534 switch(Node->getOpcode()) { 3535 case ISD::FSQRT: 3536 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3537 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3538 break; 3539 case ISD::FSIN: 3540 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3541 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3542 break; 3543 case ISD::FCOS: 3544 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3545 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3546 break; 3547 default: assert(0 && "Unreachable!"); 3548 } 3549 SDOperand Dummy; 3550 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3551 break; 3552 } 3553 } 3554 break; 3555 } 3556 break; 3557 case ISD::FPOWI: { 3558 MVT VT = Node->getValueType(0); 3559 3560 // Expand unsupported unary vector operators by unrolling them. 3561 if (VT.isVector()) { 3562 Result = LegalizeOp(UnrollVectorOp(Op)); 3563 break; 3564 } 3565 3566 // We always lower FPOWI into a libcall. No target support for it yet. 3567 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3568 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3569 SDOperand Dummy; 3570 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3571 break; 3572 } 3573 case ISD::BIT_CONVERT: 3574 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3575 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3576 Node->getValueType(0)); 3577 } else if (Op.getOperand(0).getValueType().isVector()) { 3578 // The input has to be a vector type, we have to either scalarize it, pack 3579 // it, or convert it based on whether the input vector type is legal. 3580 SDNode *InVal = Node->getOperand(0).Val; 3581 int InIx = Node->getOperand(0).ResNo; 3582 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3583 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3584 3585 // Figure out if there is a simple type corresponding to this Vector 3586 // type. If so, convert to the vector type. 3587 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3588 if (TLI.isTypeLegal(TVT)) { 3589 // Turn this into a bit convert of the vector input. 3590 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3591 LegalizeOp(Node->getOperand(0))); 3592 break; 3593 } else if (NumElems == 1) { 3594 // Turn this into a bit convert of the scalar input. 3595 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3596 ScalarizeVectorOp(Node->getOperand(0))); 3597 break; 3598 } else { 3599 // FIXME: UNIMP! Store then reload 3600 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3601 } 3602 } else { 3603 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3604 Node->getOperand(0).getValueType())) { 3605 default: assert(0 && "Unknown operation action!"); 3606 case TargetLowering::Expand: 3607 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3608 Node->getValueType(0)); 3609 break; 3610 case TargetLowering::Legal: 3611 Tmp1 = LegalizeOp(Node->getOperand(0)); 3612 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3613 break; 3614 } 3615 } 3616 break; 3617 3618 // Conversion operators. The source and destination have different types. 3619 case ISD::SINT_TO_FP: 3620 case ISD::UINT_TO_FP: { 3621 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3622 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3623 case Legal: 3624 switch (TLI.getOperationAction(Node->getOpcode(), 3625 Node->getOperand(0).getValueType())) { 3626 default: assert(0 && "Unknown operation action!"); 3627 case TargetLowering::Custom: 3628 isCustom = true; 3629 // FALLTHROUGH 3630 case TargetLowering::Legal: 3631 Tmp1 = LegalizeOp(Node->getOperand(0)); 3632 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3633 if (isCustom) { 3634 Tmp1 = TLI.LowerOperation(Result, DAG); 3635 if (Tmp1.Val) Result = Tmp1; 3636 } 3637 break; 3638 case TargetLowering::Expand: 3639 Result = ExpandLegalINT_TO_FP(isSigned, 3640 LegalizeOp(Node->getOperand(0)), 3641 Node->getValueType(0)); 3642 break; 3643 case TargetLowering::Promote: 3644 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3645 Node->getValueType(0), 3646 isSigned); 3647 break; 3648 } 3649 break; 3650 case Expand: 3651 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3652 Node->getValueType(0), Node->getOperand(0)); 3653 break; 3654 case Promote: 3655 Tmp1 = PromoteOp(Node->getOperand(0)); 3656 if (isSigned) { 3657 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3658 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3659 } else { 3660 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3661 Node->getOperand(0).getValueType()); 3662 } 3663 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3664 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3665 break; 3666 } 3667 break; 3668 } 3669 case ISD::TRUNCATE: 3670 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3671 case Legal: 3672 Tmp1 = LegalizeOp(Node->getOperand(0)); 3673 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3674 break; 3675 case Expand: 3676 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3677 3678 // Since the result is legal, we should just be able to truncate the low 3679 // part of the source. 3680 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3681 break; 3682 case Promote: 3683 Result = PromoteOp(Node->getOperand(0)); 3684 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3685 break; 3686 } 3687 break; 3688 3689 case ISD::FP_TO_SINT: 3690 case ISD::FP_TO_UINT: 3691 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3692 case Legal: 3693 Tmp1 = LegalizeOp(Node->getOperand(0)); 3694 3695 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3696 default: assert(0 && "Unknown operation action!"); 3697 case TargetLowering::Custom: 3698 isCustom = true; 3699 // FALLTHROUGH 3700 case TargetLowering::Legal: 3701 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3702 if (isCustom) { 3703 Tmp1 = TLI.LowerOperation(Result, DAG); 3704 if (Tmp1.Val) Result = Tmp1; 3705 } 3706 break; 3707 case TargetLowering::Promote: 3708 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3709 Node->getOpcode() == ISD::FP_TO_SINT); 3710 break; 3711 case TargetLowering::Expand: 3712 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3713 SDOperand True, False; 3714 MVT VT = Node->getOperand(0).getValueType(); 3715 MVT NVT = Node->getValueType(0); 3716 const uint64_t zero[] = {0, 0}; 3717 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3718 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3719 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3720 Tmp2 = DAG.getConstantFP(apf, VT); 3721 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3722 Node->getOperand(0), Tmp2, ISD::SETLT); 3723 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3724 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3725 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3726 Tmp2)); 3727 False = DAG.getNode(ISD::XOR, NVT, False, 3728 DAG.getConstant(x, NVT)); 3729 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3730 break; 3731 } else { 3732 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3733 } 3734 break; 3735 } 3736 break; 3737 case Expand: { 3738 MVT VT = Op.getValueType(); 3739 MVT OVT = Node->getOperand(0).getValueType(); 3740 // Convert ppcf128 to i32 3741 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3742 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3743 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3744 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3745 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3746 DAG.getIntPtrConstant(1)); 3747 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3748 } else { 3749 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3750 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3751 Tmp2 = DAG.getConstantFP(apf, OVT); 3752 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3753 // FIXME: generated code sucks. 3754 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3755 DAG.getNode(ISD::ADD, MVT::i32, 3756 DAG.getNode(ISD::FP_TO_SINT, VT, 3757 DAG.getNode(ISD::FSUB, OVT, 3758 Node->getOperand(0), Tmp2)), 3759 DAG.getConstant(0x80000000, MVT::i32)), 3760 DAG.getNode(ISD::FP_TO_SINT, VT, 3761 Node->getOperand(0)), 3762 DAG.getCondCode(ISD::SETGE)); 3763 } 3764 break; 3765 } 3766 // Convert f32 / f64 to i32 / i64 / i128. 3767 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3768 switch (Node->getOpcode()) { 3769 case ISD::FP_TO_SINT: { 3770 if (VT == MVT::i32) { 3771 if (OVT == MVT::f32) 3772 LC = RTLIB::FPTOSINT_F32_I32; 3773 else if (OVT == MVT::f64) 3774 LC = RTLIB::FPTOSINT_F64_I32; 3775 else 3776 assert(0 && "Unexpected i32-to-fp conversion!"); 3777 } else if (VT == MVT::i64) { 3778 if (OVT == MVT::f32) 3779 LC = RTLIB::FPTOSINT_F32_I64; 3780 else if (OVT == MVT::f64) 3781 LC = RTLIB::FPTOSINT_F64_I64; 3782 else if (OVT == MVT::f80) 3783 LC = RTLIB::FPTOSINT_F80_I64; 3784 else if (OVT == MVT::ppcf128) 3785 LC = RTLIB::FPTOSINT_PPCF128_I64; 3786 else 3787 assert(0 && "Unexpected i64-to-fp conversion!"); 3788 } else if (VT == MVT::i128) { 3789 if (OVT == MVT::f32) 3790 LC = RTLIB::FPTOSINT_F32_I128; 3791 else if (OVT == MVT::f64) 3792 LC = RTLIB::FPTOSINT_F64_I128; 3793 else if (OVT == MVT::f80) 3794 LC = RTLIB::FPTOSINT_F80_I128; 3795 else if (OVT == MVT::ppcf128) 3796 LC = RTLIB::FPTOSINT_PPCF128_I128; 3797 else 3798 assert(0 && "Unexpected i128-to-fp conversion!"); 3799 } else { 3800 assert(0 && "Unexpectd int-to-fp conversion!"); 3801 } 3802 break; 3803 } 3804 case ISD::FP_TO_UINT: { 3805 if (VT == MVT::i32) { 3806 if (OVT == MVT::f32) 3807 LC = RTLIB::FPTOUINT_F32_I32; 3808 else if (OVT == MVT::f64) 3809 LC = RTLIB::FPTOUINT_F64_I32; 3810 else if (OVT == MVT::f80) 3811 LC = RTLIB::FPTOUINT_F80_I32; 3812 else 3813 assert(0 && "Unexpected i32-to-fp conversion!"); 3814 } else if (VT == MVT::i64) { 3815 if (OVT == MVT::f32) 3816 LC = RTLIB::FPTOUINT_F32_I64; 3817 else if (OVT == MVT::f64) 3818 LC = RTLIB::FPTOUINT_F64_I64; 3819 else if (OVT == MVT::f80) 3820 LC = RTLIB::FPTOUINT_F80_I64; 3821 else if (OVT == MVT::ppcf128) 3822 LC = RTLIB::FPTOUINT_PPCF128_I64; 3823 else 3824 assert(0 && "Unexpected i64-to-fp conversion!"); 3825 } else if (VT == MVT::i128) { 3826 if (OVT == MVT::f32) 3827 LC = RTLIB::FPTOUINT_F32_I128; 3828 else if (OVT == MVT::f64) 3829 LC = RTLIB::FPTOUINT_F64_I128; 3830 else if (OVT == MVT::f80) 3831 LC = RTLIB::FPTOUINT_F80_I128; 3832 else if (OVT == MVT::ppcf128) 3833 LC = RTLIB::FPTOUINT_PPCF128_I128; 3834 else 3835 assert(0 && "Unexpected i128-to-fp conversion!"); 3836 } else { 3837 assert(0 && "Unexpectd int-to-fp conversion!"); 3838 } 3839 break; 3840 } 3841 default: assert(0 && "Unreachable!"); 3842 } 3843 SDOperand Dummy; 3844 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3845 break; 3846 } 3847 case Promote: 3848 Tmp1 = PromoteOp(Node->getOperand(0)); 3849 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3850 Result = LegalizeOp(Result); 3851 break; 3852 } 3853 break; 3854 3855 case ISD::FP_EXTEND: { 3856 MVT DstVT = Op.getValueType(); 3857 MVT SrcVT = Op.getOperand(0).getValueType(); 3858 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3859 // The only other way we can lower this is to turn it into a STORE, 3860 // LOAD pair, targetting a temporary location (a stack slot). 3861 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3862 break; 3863 } 3864 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3865 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3866 case Legal: 3867 Tmp1 = LegalizeOp(Node->getOperand(0)); 3868 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3869 break; 3870 case Promote: 3871 Tmp1 = PromoteOp(Node->getOperand(0)); 3872 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3873 break; 3874 } 3875 break; 3876 } 3877 case ISD::FP_ROUND: { 3878 MVT DstVT = Op.getValueType(); 3879 MVT SrcVT = Op.getOperand(0).getValueType(); 3880 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3881 if (SrcVT == MVT::ppcf128) { 3882 SDOperand Lo; 3883 ExpandOp(Node->getOperand(0), Lo, Result); 3884 // Round it the rest of the way (e.g. to f32) if needed. 3885 if (DstVT!=MVT::f64) 3886 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3887 break; 3888 } 3889 // The only other way we can lower this is to turn it into a STORE, 3890 // LOAD pair, targetting a temporary location (a stack slot). 3891 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3892 break; 3893 } 3894 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3895 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3896 case Legal: 3897 Tmp1 = LegalizeOp(Node->getOperand(0)); 3898 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3899 break; 3900 case Promote: 3901 Tmp1 = PromoteOp(Node->getOperand(0)); 3902 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3903 Node->getOperand(1)); 3904 break; 3905 } 3906 break; 3907 } 3908 case ISD::ANY_EXTEND: 3909 case ISD::ZERO_EXTEND: 3910 case ISD::SIGN_EXTEND: 3911 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3912 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3913 case Legal: 3914 Tmp1 = LegalizeOp(Node->getOperand(0)); 3915 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3916 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3917 TargetLowering::Custom) { 3918 Tmp1 = TLI.LowerOperation(Result, DAG); 3919 if (Tmp1.Val) Result = Tmp1; 3920 } 3921 break; 3922 case Promote: 3923 switch (Node->getOpcode()) { 3924 case ISD::ANY_EXTEND: 3925 Tmp1 = PromoteOp(Node->getOperand(0)); 3926 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3927 break; 3928 case ISD::ZERO_EXTEND: 3929 Result = PromoteOp(Node->getOperand(0)); 3930 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3931 Result = DAG.getZeroExtendInReg(Result, 3932 Node->getOperand(0).getValueType()); 3933 break; 3934 case ISD::SIGN_EXTEND: 3935 Result = PromoteOp(Node->getOperand(0)); 3936 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3937 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3938 Result, 3939 DAG.getValueType(Node->getOperand(0).getValueType())); 3940 break; 3941 } 3942 } 3943 break; 3944 case ISD::FP_ROUND_INREG: 3945 case ISD::SIGN_EXTEND_INREG: { 3946 Tmp1 = LegalizeOp(Node->getOperand(0)); 3947 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3948 3949 // If this operation is not supported, convert it to a shl/shr or load/store 3950 // pair. 3951 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3952 default: assert(0 && "This action not supported for this op yet!"); 3953 case TargetLowering::Legal: 3954 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3955 break; 3956 case TargetLowering::Expand: 3957 // If this is an integer extend and shifts are supported, do that. 3958 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3959 // NOTE: we could fall back on load/store here too for targets without 3960 // SAR. However, it is doubtful that any exist. 3961 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3962 ExtraVT.getSizeInBits(); 3963 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3964 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3965 Node->getOperand(0), ShiftCst); 3966 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3967 Result, ShiftCst); 3968 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3969 // The only way we can lower this is to turn it into a TRUNCSTORE, 3970 // EXTLOAD pair, targetting a temporary location (a stack slot). 3971 3972 // NOTE: there is a choice here between constantly creating new stack 3973 // slots and always reusing the same one. We currently always create 3974 // new ones, as reuse may inhibit scheduling. 3975 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3976 Node->getValueType(0)); 3977 } else { 3978 assert(0 && "Unknown op"); 3979 } 3980 break; 3981 } 3982 break; 3983 } 3984 case ISD::TRAMPOLINE: { 3985 SDOperand Ops[6]; 3986 for (unsigned i = 0; i != 6; ++i) 3987 Ops[i] = LegalizeOp(Node->getOperand(i)); 3988 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3989 // The only option for this node is to custom lower it. 3990 Result = TLI.LowerOperation(Result, DAG); 3991 assert(Result.Val && "Should always custom lower!"); 3992 3993 // Since trampoline produces two values, make sure to remember that we 3994 // legalized both of them. 3995 Tmp1 = LegalizeOp(Result.getValue(1)); 3996 Result = LegalizeOp(Result); 3997 AddLegalizedOperand(SDOperand(Node, 0), Result); 3998 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3999 return Op.ResNo ? Tmp1 : Result; 4000 } 4001 case ISD::FLT_ROUNDS_: { 4002 MVT VT = Node->getValueType(0); 4003 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4004 default: assert(0 && "This action not supported for this op yet!"); 4005 case TargetLowering::Custom: 4006 Result = TLI.LowerOperation(Op, DAG); 4007 if (Result.Val) break; 4008 // Fall Thru 4009 case TargetLowering::Legal: 4010 // If this operation is not supported, lower it to constant 1 4011 Result = DAG.getConstant(1, VT); 4012 break; 4013 } 4014 break; 4015 } 4016 case ISD::TRAP: { 4017 MVT VT = Node->getValueType(0); 4018 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4019 default: assert(0 && "This action not supported for this op yet!"); 4020 case TargetLowering::Legal: 4021 Tmp1 = LegalizeOp(Node->getOperand(0)); 4022 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4023 break; 4024 case TargetLowering::Custom: 4025 Result = TLI.LowerOperation(Op, DAG); 4026 if (Result.Val) break; 4027 // Fall Thru 4028 case TargetLowering::Expand: 4029 // If this operation is not supported, lower it to 'abort()' call 4030 Tmp1 = LegalizeOp(Node->getOperand(0)); 4031 TargetLowering::ArgListTy Args; 4032 std::pair<SDOperand,SDOperand> CallResult = 4033 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4034 false, false, false, CallingConv::C, false, 4035 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4036 Args, DAG); 4037 Result = CallResult.second; 4038 break; 4039 } 4040 break; 4041 } 4042 } 4043 4044 assert(Result.getValueType() == Op.getValueType() && 4045 "Bad legalization!"); 4046 4047 // Make sure that the generated code is itself legal. 4048 if (Result != Op) 4049 Result = LegalizeOp(Result); 4050 4051 // Note that LegalizeOp may be reentered even from single-use nodes, which 4052 // means that we always must cache transformed nodes. 4053 AddLegalizedOperand(Op, Result); 4054 return Result; 4055} 4056 4057/// PromoteOp - Given an operation that produces a value in an invalid type, 4058/// promote it to compute the value into a larger type. The produced value will 4059/// have the correct bits for the low portion of the register, but no guarantee 4060/// is made about the top bits: it may be zero, sign-extended, or garbage. 4061SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 4062 MVT VT = Op.getValueType(); 4063 MVT NVT = TLI.getTypeToTransformTo(VT); 4064 assert(getTypeAction(VT) == Promote && 4065 "Caller should expand or legalize operands that are not promotable!"); 4066 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4067 "Cannot promote to smaller type!"); 4068 4069 SDOperand Tmp1, Tmp2, Tmp3; 4070 SDOperand Result; 4071 SDNode *Node = Op.Val; 4072 4073 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 4074 if (I != PromotedNodes.end()) return I->second; 4075 4076 switch (Node->getOpcode()) { 4077 case ISD::CopyFromReg: 4078 assert(0 && "CopyFromReg must be legal!"); 4079 default: 4080#ifndef NDEBUG 4081 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4082#endif 4083 assert(0 && "Do not know how to promote this operator!"); 4084 abort(); 4085 case ISD::UNDEF: 4086 Result = DAG.getNode(ISD::UNDEF, NVT); 4087 break; 4088 case ISD::Constant: 4089 if (VT != MVT::i1) 4090 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4091 else 4092 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4093 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4094 break; 4095 case ISD::ConstantFP: 4096 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4097 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4098 break; 4099 4100 case ISD::SETCC: 4101 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4102 && "SetCC type is not legal??"); 4103 Result = DAG.getNode(ISD::SETCC, 4104 TLI.getSetCCResultType(Node->getOperand(0)), 4105 Node->getOperand(0), Node->getOperand(1), 4106 Node->getOperand(2)); 4107 break; 4108 4109 case ISD::TRUNCATE: 4110 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4111 case Legal: 4112 Result = LegalizeOp(Node->getOperand(0)); 4113 assert(Result.getValueType().bitsGE(NVT) && 4114 "This truncation doesn't make sense!"); 4115 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4116 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4117 break; 4118 case Promote: 4119 // The truncation is not required, because we don't guarantee anything 4120 // about high bits anyway. 4121 Result = PromoteOp(Node->getOperand(0)); 4122 break; 4123 case Expand: 4124 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4125 // Truncate the low part of the expanded value to the result type 4126 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4127 } 4128 break; 4129 case ISD::SIGN_EXTEND: 4130 case ISD::ZERO_EXTEND: 4131 case ISD::ANY_EXTEND: 4132 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4133 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4134 case Legal: 4135 // Input is legal? Just do extend all the way to the larger type. 4136 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4137 break; 4138 case Promote: 4139 // Promote the reg if it's smaller. 4140 Result = PromoteOp(Node->getOperand(0)); 4141 // The high bits are not guaranteed to be anything. Insert an extend. 4142 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4143 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4144 DAG.getValueType(Node->getOperand(0).getValueType())); 4145 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4146 Result = DAG.getZeroExtendInReg(Result, 4147 Node->getOperand(0).getValueType()); 4148 break; 4149 } 4150 break; 4151 case ISD::BIT_CONVERT: 4152 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4153 Node->getValueType(0)); 4154 Result = PromoteOp(Result); 4155 break; 4156 4157 case ISD::FP_EXTEND: 4158 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4159 case ISD::FP_ROUND: 4160 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4161 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4162 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4163 case Legal: 4164 if (Node->getConstantOperandVal(1) == 0) { 4165 // Input is legal? Do an FP_ROUND_INREG. 4166 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4167 DAG.getValueType(VT)); 4168 } else { 4169 // Just remove the truncate, it isn't affecting the value. 4170 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4171 Node->getOperand(1)); 4172 } 4173 break; 4174 } 4175 break; 4176 case ISD::SINT_TO_FP: 4177 case ISD::UINT_TO_FP: 4178 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4179 case Legal: 4180 // No extra round required here. 4181 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4182 break; 4183 4184 case Promote: 4185 Result = PromoteOp(Node->getOperand(0)); 4186 if (Node->getOpcode() == ISD::SINT_TO_FP) 4187 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4188 Result, 4189 DAG.getValueType(Node->getOperand(0).getValueType())); 4190 else 4191 Result = DAG.getZeroExtendInReg(Result, 4192 Node->getOperand(0).getValueType()); 4193 // No extra round required here. 4194 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4195 break; 4196 case Expand: 4197 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4198 Node->getOperand(0)); 4199 // Round if we cannot tolerate excess precision. 4200 if (NoExcessFPPrecision) 4201 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4202 DAG.getValueType(VT)); 4203 break; 4204 } 4205 break; 4206 4207 case ISD::SIGN_EXTEND_INREG: 4208 Result = PromoteOp(Node->getOperand(0)); 4209 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4210 Node->getOperand(1)); 4211 break; 4212 case ISD::FP_TO_SINT: 4213 case ISD::FP_TO_UINT: 4214 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4215 case Legal: 4216 case Expand: 4217 Tmp1 = Node->getOperand(0); 4218 break; 4219 case Promote: 4220 // The input result is prerounded, so we don't have to do anything 4221 // special. 4222 Tmp1 = PromoteOp(Node->getOperand(0)); 4223 break; 4224 } 4225 // If we're promoting a UINT to a larger size, check to see if the new node 4226 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4227 // we can use that instead. This allows us to generate better code for 4228 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4229 // legal, such as PowerPC. 4230 if (Node->getOpcode() == ISD::FP_TO_UINT && 4231 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4232 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4233 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4234 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4235 } else { 4236 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4237 } 4238 break; 4239 4240 case ISD::FABS: 4241 case ISD::FNEG: 4242 Tmp1 = PromoteOp(Node->getOperand(0)); 4243 assert(Tmp1.getValueType() == NVT); 4244 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4245 // NOTE: we do not have to do any extra rounding here for 4246 // NoExcessFPPrecision, because we know the input will have the appropriate 4247 // precision, and these operations don't modify precision at all. 4248 break; 4249 4250 case ISD::FSQRT: 4251 case ISD::FSIN: 4252 case ISD::FCOS: 4253 Tmp1 = PromoteOp(Node->getOperand(0)); 4254 assert(Tmp1.getValueType() == NVT); 4255 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4256 if (NoExcessFPPrecision) 4257 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4258 DAG.getValueType(VT)); 4259 break; 4260 4261 case ISD::FPOWI: { 4262 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4263 // directly as well, which may be better. 4264 Tmp1 = PromoteOp(Node->getOperand(0)); 4265 assert(Tmp1.getValueType() == NVT); 4266 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4267 if (NoExcessFPPrecision) 4268 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4269 DAG.getValueType(VT)); 4270 break; 4271 } 4272 4273 case ISD::ATOMIC_LCS: { 4274 Tmp2 = PromoteOp(Node->getOperand(2)); 4275 Tmp3 = PromoteOp(Node->getOperand(3)); 4276 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4277 Node->getOperand(1), Tmp2, Tmp3, 4278 cast<AtomicSDNode>(Node)->getVT()); 4279 // Remember that we legalized the chain. 4280 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4281 break; 4282 } 4283 case ISD::ATOMIC_LAS: 4284 case ISD::ATOMIC_LSS: 4285 case ISD::ATOMIC_LOAD_AND: 4286 case ISD::ATOMIC_LOAD_OR: 4287 case ISD::ATOMIC_LOAD_XOR: 4288 case ISD::ATOMIC_LOAD_NAND: 4289 case ISD::ATOMIC_LOAD_MIN: 4290 case ISD::ATOMIC_LOAD_MAX: 4291 case ISD::ATOMIC_LOAD_UMIN: 4292 case ISD::ATOMIC_LOAD_UMAX: 4293 case ISD::ATOMIC_SWAP: { 4294 Tmp2 = PromoteOp(Node->getOperand(2)); 4295 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4296 Node->getOperand(1), Tmp2, 4297 cast<AtomicSDNode>(Node)->getVT()); 4298 // Remember that we legalized the chain. 4299 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4300 break; 4301 } 4302 4303 case ISD::AND: 4304 case ISD::OR: 4305 case ISD::XOR: 4306 case ISD::ADD: 4307 case ISD::SUB: 4308 case ISD::MUL: 4309 // The input may have strange things in the top bits of the registers, but 4310 // these operations don't care. They may have weird bits going out, but 4311 // that too is okay if they are integer operations. 4312 Tmp1 = PromoteOp(Node->getOperand(0)); 4313 Tmp2 = PromoteOp(Node->getOperand(1)); 4314 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4315 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4316 break; 4317 case ISD::FADD: 4318 case ISD::FSUB: 4319 case ISD::FMUL: 4320 Tmp1 = PromoteOp(Node->getOperand(0)); 4321 Tmp2 = PromoteOp(Node->getOperand(1)); 4322 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4323 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4324 4325 // Floating point operations will give excess precision that we may not be 4326 // able to tolerate. If we DO allow excess precision, just leave it, 4327 // otherwise excise it. 4328 // FIXME: Why would we need to round FP ops more than integer ones? 4329 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4330 if (NoExcessFPPrecision) 4331 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4332 DAG.getValueType(VT)); 4333 break; 4334 4335 case ISD::SDIV: 4336 case ISD::SREM: 4337 // These operators require that their input be sign extended. 4338 Tmp1 = PromoteOp(Node->getOperand(0)); 4339 Tmp2 = PromoteOp(Node->getOperand(1)); 4340 if (NVT.isInteger()) { 4341 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4342 DAG.getValueType(VT)); 4343 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4344 DAG.getValueType(VT)); 4345 } 4346 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4347 4348 // Perform FP_ROUND: this is probably overly pessimistic. 4349 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4350 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4351 DAG.getValueType(VT)); 4352 break; 4353 case ISD::FDIV: 4354 case ISD::FREM: 4355 case ISD::FCOPYSIGN: 4356 // These operators require that their input be fp extended. 4357 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4358 case Expand: assert(0 && "not implemented"); 4359 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4360 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4361 } 4362 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4363 case Expand: assert(0 && "not implemented"); 4364 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4365 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4366 } 4367 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4368 4369 // Perform FP_ROUND: this is probably overly pessimistic. 4370 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4371 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4372 DAG.getValueType(VT)); 4373 break; 4374 4375 case ISD::UDIV: 4376 case ISD::UREM: 4377 // These operators require that their input be zero extended. 4378 Tmp1 = PromoteOp(Node->getOperand(0)); 4379 Tmp2 = PromoteOp(Node->getOperand(1)); 4380 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4381 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4382 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4383 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4384 break; 4385 4386 case ISD::SHL: 4387 Tmp1 = PromoteOp(Node->getOperand(0)); 4388 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4389 break; 4390 case ISD::SRA: 4391 // The input value must be properly sign extended. 4392 Tmp1 = PromoteOp(Node->getOperand(0)); 4393 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4394 DAG.getValueType(VT)); 4395 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4396 break; 4397 case ISD::SRL: 4398 // The input value must be properly zero extended. 4399 Tmp1 = PromoteOp(Node->getOperand(0)); 4400 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4401 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4402 break; 4403 4404 case ISD::VAARG: 4405 Tmp1 = Node->getOperand(0); // Get the chain. 4406 Tmp2 = Node->getOperand(1); // Get the pointer. 4407 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4408 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4409 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4410 } else { 4411 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4412 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4413 // Increment the pointer, VAList, to the next vaarg 4414 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4415 DAG.getConstant(VT.getSizeInBits()/8, 4416 TLI.getPointerTy())); 4417 // Store the incremented VAList to the legalized pointer 4418 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4419 // Load the actual argument out of the pointer VAList 4420 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4421 } 4422 // Remember that we legalized the chain. 4423 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4424 break; 4425 4426 case ISD::LOAD: { 4427 LoadSDNode *LD = cast<LoadSDNode>(Node); 4428 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4429 ? ISD::EXTLOAD : LD->getExtensionType(); 4430 Result = DAG.getExtLoad(ExtType, NVT, 4431 LD->getChain(), LD->getBasePtr(), 4432 LD->getSrcValue(), LD->getSrcValueOffset(), 4433 LD->getMemoryVT(), 4434 LD->isVolatile(), 4435 LD->getAlignment()); 4436 // Remember that we legalized the chain. 4437 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4438 break; 4439 } 4440 case ISD::SELECT: { 4441 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4442 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4443 4444 MVT VT2 = Tmp2.getValueType(); 4445 assert(VT2 == Tmp3.getValueType() 4446 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4447 // Ensure that the resulting node is at least the same size as the operands' 4448 // value types, because we cannot assume that TLI.getSetCCValueType() is 4449 // constant. 4450 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4451 break; 4452 } 4453 case ISD::SELECT_CC: 4454 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4455 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4456 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4457 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4458 break; 4459 case ISD::BSWAP: 4460 Tmp1 = Node->getOperand(0); 4461 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4462 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4463 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4464 DAG.getConstant(NVT.getSizeInBits() - 4465 VT.getSizeInBits(), 4466 TLI.getShiftAmountTy())); 4467 break; 4468 case ISD::CTPOP: 4469 case ISD::CTTZ: 4470 case ISD::CTLZ: 4471 // Zero extend the argument 4472 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4473 // Perform the larger operation, then subtract if needed. 4474 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4475 switch(Node->getOpcode()) { 4476 case ISD::CTPOP: 4477 Result = Tmp1; 4478 break; 4479 case ISD::CTTZ: 4480 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4481 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4482 DAG.getConstant(NVT.getSizeInBits(), NVT), 4483 ISD::SETEQ); 4484 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4485 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4486 break; 4487 case ISD::CTLZ: 4488 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4489 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4490 DAG.getConstant(NVT.getSizeInBits() - 4491 VT.getSizeInBits(), NVT)); 4492 break; 4493 } 4494 break; 4495 case ISD::EXTRACT_SUBVECTOR: 4496 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4497 break; 4498 case ISD::EXTRACT_VECTOR_ELT: 4499 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4500 break; 4501 } 4502 4503 assert(Result.Val && "Didn't set a result!"); 4504 4505 // Make sure the result is itself legal. 4506 Result = LegalizeOp(Result); 4507 4508 // Remember that we promoted this! 4509 AddPromotedOperand(Op, Result); 4510 return Result; 4511} 4512 4513/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4514/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4515/// based on the vector type. The return type of this matches the element type 4516/// of the vector, which may not be legal for the target. 4517SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4518 // We know that operand #0 is the Vec vector. If the index is a constant 4519 // or if the invec is a supported hardware type, we can use it. Otherwise, 4520 // lower to a store then an indexed load. 4521 SDOperand Vec = Op.getOperand(0); 4522 SDOperand Idx = Op.getOperand(1); 4523 4524 MVT TVT = Vec.getValueType(); 4525 unsigned NumElems = TVT.getVectorNumElements(); 4526 4527 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4528 default: assert(0 && "This action is not supported yet!"); 4529 case TargetLowering::Custom: { 4530 Vec = LegalizeOp(Vec); 4531 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4532 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4533 if (Tmp3.Val) 4534 return Tmp3; 4535 break; 4536 } 4537 case TargetLowering::Legal: 4538 if (isTypeLegal(TVT)) { 4539 Vec = LegalizeOp(Vec); 4540 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4541 return Op; 4542 } 4543 break; 4544 case TargetLowering::Expand: 4545 break; 4546 } 4547 4548 if (NumElems == 1) { 4549 // This must be an access of the only element. Return it. 4550 Op = ScalarizeVectorOp(Vec); 4551 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4552 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4553 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4554 SDOperand Lo, Hi; 4555 SplitVectorOp(Vec, Lo, Hi); 4556 if (CIdx->getValue() < NumLoElts) { 4557 Vec = Lo; 4558 } else { 4559 Vec = Hi; 4560 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4561 Idx.getValueType()); 4562 } 4563 4564 // It's now an extract from the appropriate high or low part. Recurse. 4565 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4566 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4567 } else { 4568 // Store the value to a temporary stack slot, then LOAD the scalar 4569 // element back out. 4570 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4571 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4572 4573 // Add the offset to the index. 4574 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4575 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4576 DAG.getConstant(EltSize, Idx.getValueType())); 4577 4578 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 4579 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4580 else 4581 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4582 4583 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4584 4585 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4586 } 4587 return Op; 4588} 4589 4590/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4591/// we assume the operation can be split if it is not already legal. 4592SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4593 // We know that operand #0 is the Vec vector. For now we assume the index 4594 // is a constant and that the extracted result is a supported hardware type. 4595 SDOperand Vec = Op.getOperand(0); 4596 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4597 4598 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 4599 4600 if (NumElems == Op.getValueType().getVectorNumElements()) { 4601 // This must be an access of the desired vector length. Return it. 4602 return Vec; 4603 } 4604 4605 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4606 SDOperand Lo, Hi; 4607 SplitVectorOp(Vec, Lo, Hi); 4608 if (CIdx->getValue() < NumElems/2) { 4609 Vec = Lo; 4610 } else { 4611 Vec = Hi; 4612 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4613 } 4614 4615 // It's now an extract from the appropriate high or low part. Recurse. 4616 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4617 return ExpandEXTRACT_SUBVECTOR(Op); 4618} 4619 4620/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4621/// with condition CC on the current target. This usually involves legalizing 4622/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4623/// there may be no choice but to create a new SetCC node to represent the 4624/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4625/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4626void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4627 SDOperand &RHS, 4628 SDOperand &CC) { 4629 SDOperand Tmp1, Tmp2, Tmp3, Result; 4630 4631 switch (getTypeAction(LHS.getValueType())) { 4632 case Legal: 4633 Tmp1 = LegalizeOp(LHS); // LHS 4634 Tmp2 = LegalizeOp(RHS); // RHS 4635 break; 4636 case Promote: 4637 Tmp1 = PromoteOp(LHS); // LHS 4638 Tmp2 = PromoteOp(RHS); // RHS 4639 4640 // If this is an FP compare, the operands have already been extended. 4641 if (LHS.getValueType().isInteger()) { 4642 MVT VT = LHS.getValueType(); 4643 MVT NVT = TLI.getTypeToTransformTo(VT); 4644 4645 // Otherwise, we have to insert explicit sign or zero extends. Note 4646 // that we could insert sign extends for ALL conditions, but zero extend 4647 // is cheaper on many machines (an AND instead of two shifts), so prefer 4648 // it. 4649 switch (cast<CondCodeSDNode>(CC)->get()) { 4650 default: assert(0 && "Unknown integer comparison!"); 4651 case ISD::SETEQ: 4652 case ISD::SETNE: 4653 case ISD::SETUGE: 4654 case ISD::SETUGT: 4655 case ISD::SETULE: 4656 case ISD::SETULT: 4657 // ALL of these operations will work if we either sign or zero extend 4658 // the operands (including the unsigned comparisons!). Zero extend is 4659 // usually a simpler/cheaper operation, so prefer it. 4660 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4661 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4662 break; 4663 case ISD::SETGE: 4664 case ISD::SETGT: 4665 case ISD::SETLT: 4666 case ISD::SETLE: 4667 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4668 DAG.getValueType(VT)); 4669 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4670 DAG.getValueType(VT)); 4671 break; 4672 } 4673 } 4674 break; 4675 case Expand: { 4676 MVT VT = LHS.getValueType(); 4677 if (VT == MVT::f32 || VT == MVT::f64) { 4678 // Expand into one or more soft-fp libcall(s). 4679 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4680 switch (cast<CondCodeSDNode>(CC)->get()) { 4681 case ISD::SETEQ: 4682 case ISD::SETOEQ: 4683 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4684 break; 4685 case ISD::SETNE: 4686 case ISD::SETUNE: 4687 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4688 break; 4689 case ISD::SETGE: 4690 case ISD::SETOGE: 4691 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4692 break; 4693 case ISD::SETLT: 4694 case ISD::SETOLT: 4695 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4696 break; 4697 case ISD::SETLE: 4698 case ISD::SETOLE: 4699 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4700 break; 4701 case ISD::SETGT: 4702 case ISD::SETOGT: 4703 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4704 break; 4705 case ISD::SETUO: 4706 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4707 break; 4708 case ISD::SETO: 4709 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4710 break; 4711 default: 4712 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4713 switch (cast<CondCodeSDNode>(CC)->get()) { 4714 case ISD::SETONE: 4715 // SETONE = SETOLT | SETOGT 4716 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4717 // Fallthrough 4718 case ISD::SETUGT: 4719 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4720 break; 4721 case ISD::SETUGE: 4722 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4723 break; 4724 case ISD::SETULT: 4725 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4726 break; 4727 case ISD::SETULE: 4728 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4729 break; 4730 case ISD::SETUEQ: 4731 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4732 break; 4733 default: assert(0 && "Unsupported FP setcc!"); 4734 } 4735 } 4736 4737 SDOperand Dummy; 4738 Tmp1 = ExpandLibCall(LC1, 4739 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4740 false /*sign irrelevant*/, Dummy); 4741 Tmp2 = DAG.getConstant(0, MVT::i32); 4742 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4743 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4744 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4745 CC); 4746 LHS = ExpandLibCall(LC2, 4747 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4748 false /*sign irrelevant*/, Dummy); 4749 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4750 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4751 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4752 Tmp2 = SDOperand(); 4753 } 4754 LHS = Tmp1; 4755 RHS = Tmp2; 4756 return; 4757 } 4758 4759 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4760 ExpandOp(LHS, LHSLo, LHSHi); 4761 ExpandOp(RHS, RHSLo, RHSHi); 4762 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4763 4764 if (VT==MVT::ppcf128) { 4765 // FIXME: This generated code sucks. We want to generate 4766 // FCMP crN, hi1, hi2 4767 // BNE crN, L: 4768 // FCMP crN, lo1, lo2 4769 // The following can be improved, but not that much. 4770 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4771 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4772 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4773 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4774 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4775 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4776 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4777 Tmp2 = SDOperand(); 4778 break; 4779 } 4780 4781 switch (CCCode) { 4782 case ISD::SETEQ: 4783 case ISD::SETNE: 4784 if (RHSLo == RHSHi) 4785 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4786 if (RHSCST->isAllOnesValue()) { 4787 // Comparison to -1. 4788 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4789 Tmp2 = RHSLo; 4790 break; 4791 } 4792 4793 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4794 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4795 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4796 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4797 break; 4798 default: 4799 // If this is a comparison of the sign bit, just look at the top part. 4800 // X > -1, x < 0 4801 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4802 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4803 CST->isNullValue()) || // X < 0 4804 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4805 CST->isAllOnesValue())) { // X > -1 4806 Tmp1 = LHSHi; 4807 Tmp2 = RHSHi; 4808 break; 4809 } 4810 4811 // FIXME: This generated code sucks. 4812 ISD::CondCode LowCC; 4813 switch (CCCode) { 4814 default: assert(0 && "Unknown integer setcc!"); 4815 case ISD::SETLT: 4816 case ISD::SETULT: LowCC = ISD::SETULT; break; 4817 case ISD::SETGT: 4818 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4819 case ISD::SETLE: 4820 case ISD::SETULE: LowCC = ISD::SETULE; break; 4821 case ISD::SETGE: 4822 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4823 } 4824 4825 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4826 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4827 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4828 4829 // NOTE: on targets without efficient SELECT of bools, we can always use 4830 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4831 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4832 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4833 LowCC, false, DagCombineInfo); 4834 if (!Tmp1.Val) 4835 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4836 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4837 CCCode, false, DagCombineInfo); 4838 if (!Tmp2.Val) 4839 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4840 RHSHi,CC); 4841 4842 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4843 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4844 if ((Tmp1C && Tmp1C->isNullValue()) || 4845 (Tmp2C && Tmp2C->isNullValue() && 4846 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4847 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4848 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4849 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4850 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4851 // low part is known false, returns high part. 4852 // For LE / GE, if high part is known false, ignore the low part. 4853 // For LT / GT, if high part is known true, ignore the low part. 4854 Tmp1 = Tmp2; 4855 Tmp2 = SDOperand(); 4856 } else { 4857 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4858 ISD::SETEQ, false, DagCombineInfo); 4859 if (!Result.Val) 4860 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4861 ISD::SETEQ); 4862 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4863 Result, Tmp1, Tmp2)); 4864 Tmp1 = Result; 4865 Tmp2 = SDOperand(); 4866 } 4867 } 4868 } 4869 } 4870 LHS = Tmp1; 4871 RHS = Tmp2; 4872} 4873 4874/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4875/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4876/// a load from the stack slot to DestVT, extending it if needed. 4877/// The resultant code need not be legal. 4878SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4879 MVT SlotVT, 4880 MVT DestVT) { 4881 // Create the stack frame object. 4882 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4883 4884 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4885 int SPFI = StackPtrFI->getIndex(); 4886 4887 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 4888 unsigned SlotSize = SlotVT.getSizeInBits(); 4889 unsigned DestSize = DestVT.getSizeInBits(); 4890 4891 // Emit a store to the stack slot. Use a truncstore if the input value is 4892 // later than DestVT. 4893 SDOperand Store; 4894 if (SrcSize > SlotSize) 4895 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4896 PseudoSourceValue::getFixedStack(), 4897 SPFI, SlotVT); 4898 else { 4899 assert(SrcSize == SlotSize && "Invalid store"); 4900 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4901 PseudoSourceValue::getFixedStack(), 4902 SPFI); 4903 } 4904 4905 // Result is a load from the stack slot. 4906 if (SlotSize == DestSize) 4907 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4908 4909 assert(SlotSize < DestSize && "Unknown extension!"); 4910 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4911} 4912 4913SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4914 // Create a vector sized/aligned stack slot, store the value to element #0, 4915 // then load the whole vector back out. 4916 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4917 4918 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4919 int SPFI = StackPtrFI->getIndex(); 4920 4921 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4922 PseudoSourceValue::getFixedStack(), SPFI); 4923 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4924 PseudoSourceValue::getFixedStack(), SPFI); 4925} 4926 4927 4928/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4929/// support the operation, but do support the resultant vector type. 4930SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4931 4932 // If the only non-undef value is the low element, turn this into a 4933 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4934 unsigned NumElems = Node->getNumOperands(); 4935 bool isOnlyLowElement = true; 4936 SDOperand SplatValue = Node->getOperand(0); 4937 4938 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t> 4939 // and use a bitmask instead of a list of elements. 4940 std::map<SDOperand, std::vector<unsigned> > Values; 4941 Values[SplatValue].push_back(0); 4942 bool isConstant = true; 4943 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4944 SplatValue.getOpcode() != ISD::UNDEF) 4945 isConstant = false; 4946 4947 for (unsigned i = 1; i < NumElems; ++i) { 4948 SDOperand V = Node->getOperand(i); 4949 Values[V].push_back(i); 4950 if (V.getOpcode() != ISD::UNDEF) 4951 isOnlyLowElement = false; 4952 if (SplatValue != V) 4953 SplatValue = SDOperand(0,0); 4954 4955 // If this isn't a constant element or an undef, we can't use a constant 4956 // pool load. 4957 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4958 V.getOpcode() != ISD::UNDEF) 4959 isConstant = false; 4960 } 4961 4962 if (isOnlyLowElement) { 4963 // If the low element is an undef too, then this whole things is an undef. 4964 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4965 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4966 // Otherwise, turn this into a scalar_to_vector node. 4967 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4968 Node->getOperand(0)); 4969 } 4970 4971 // If all elements are constants, create a load from the constant pool. 4972 if (isConstant) { 4973 MVT VT = Node->getValueType(0); 4974 std::vector<Constant*> CV; 4975 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4976 if (ConstantFPSDNode *V = 4977 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4978 CV.push_back(ConstantFP::get(V->getValueAPF())); 4979 } else if (ConstantSDNode *V = 4980 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4981 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4982 } else { 4983 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4984 const Type *OpNTy = 4985 Node->getOperand(0).getValueType().getTypeForMVT(); 4986 CV.push_back(UndefValue::get(OpNTy)); 4987 } 4988 } 4989 Constant *CP = ConstantVector::get(CV); 4990 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4991 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4992 PseudoSourceValue::getConstantPool(), 0); 4993 } 4994 4995 if (SplatValue.Val) { // Splat of one value? 4996 // Build the shuffle constant vector: <0, 0, 0, 0> 4997 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 4998 SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 4999 std::vector<SDOperand> ZeroVec(NumElems, Zero); 5000 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5001 &ZeroVec[0], ZeroVec.size()); 5002 5003 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5004 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5005 // Get the splatted value into the low element of a vector register. 5006 SDOperand LowValVec = 5007 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5008 5009 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5010 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5011 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5012 SplatMask); 5013 } 5014 } 5015 5016 // If there are only two unique elements, we may be able to turn this into a 5017 // vector shuffle. 5018 if (Values.size() == 2) { 5019 // Get the two values in deterministic order. 5020 SDOperand Val1 = Node->getOperand(1); 5021 SDOperand Val2; 5022 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin(); 5023 if (MI->first != Val1) 5024 Val2 = MI->first; 5025 else 5026 Val2 = (++MI)->first; 5027 5028 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5029 // vector shuffle has the undef vector on the RHS. 5030 if (Val1.getOpcode() == ISD::UNDEF) 5031 std::swap(Val1, Val2); 5032 5033 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5034 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5035 MVT MaskEltVT = MaskVT.getVectorElementType(); 5036 std::vector<SDOperand> MaskVec(NumElems); 5037 5038 // Set elements of the shuffle mask for Val1. 5039 std::vector<unsigned> &Val1Elts = Values[Val1]; 5040 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5041 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5042 5043 // Set elements of the shuffle mask for Val2. 5044 std::vector<unsigned> &Val2Elts = Values[Val2]; 5045 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5046 if (Val2.getOpcode() != ISD::UNDEF) 5047 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5048 else 5049 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5050 5051 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5052 &MaskVec[0], MaskVec.size()); 5053 5054 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5055 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5056 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5057 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5058 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5059 SDOperand Ops[] = { Val1, Val2, ShuffleMask }; 5060 5061 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5062 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5063 } 5064 } 5065 5066 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5067 // aligned object on the stack, store each element into it, then load 5068 // the result as a vector. 5069 MVT VT = Node->getValueType(0); 5070 // Create the stack frame object. 5071 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 5072 5073 // Emit a store of each element to the stack slot. 5074 SmallVector<SDOperand, 8> Stores; 5075 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5076 // Store (in the right endianness) the elements to memory. 5077 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5078 // Ignore undef elements. 5079 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5080 5081 unsigned Offset = TypeByteSize*i; 5082 5083 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5084 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5085 5086 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5087 NULL, 0)); 5088 } 5089 5090 SDOperand StoreChain; 5091 if (!Stores.empty()) // Not all undef elements? 5092 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5093 &Stores[0], Stores.size()); 5094 else 5095 StoreChain = DAG.getEntryNode(); 5096 5097 // Result is a load from the stack slot. 5098 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5099} 5100 5101void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5102 SDOperand Op, SDOperand Amt, 5103 SDOperand &Lo, SDOperand &Hi) { 5104 // Expand the subcomponents. 5105 SDOperand LHSL, LHSH; 5106 ExpandOp(Op, LHSL, LHSH); 5107 5108 SDOperand Ops[] = { LHSL, LHSH, Amt }; 5109 MVT VT = LHSL.getValueType(); 5110 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5111 Hi = Lo.getValue(1); 5112} 5113 5114 5115/// ExpandShift - Try to find a clever way to expand this shift operation out to 5116/// smaller elements. If we can't find a way that is more efficient than a 5117/// libcall on this target, return false. Otherwise, return true with the 5118/// low-parts expanded into Lo and Hi. 5119bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 5120 SDOperand &Lo, SDOperand &Hi) { 5121 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5122 "This is not a shift!"); 5123 5124 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5125 SDOperand ShAmt = LegalizeOp(Amt); 5126 MVT ShTy = ShAmt.getValueType(); 5127 unsigned ShBits = ShTy.getSizeInBits(); 5128 unsigned VTBits = Op.getValueType().getSizeInBits(); 5129 unsigned NVTBits = NVT.getSizeInBits(); 5130 5131 // Handle the case when Amt is an immediate. 5132 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5133 unsigned Cst = CN->getValue(); 5134 // Expand the incoming operand to be shifted, so that we have its parts 5135 SDOperand InL, InH; 5136 ExpandOp(Op, InL, InH); 5137 switch(Opc) { 5138 case ISD::SHL: 5139 if (Cst > VTBits) { 5140 Lo = DAG.getConstant(0, NVT); 5141 Hi = DAG.getConstant(0, NVT); 5142 } else if (Cst > NVTBits) { 5143 Lo = DAG.getConstant(0, NVT); 5144 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5145 } else if (Cst == NVTBits) { 5146 Lo = DAG.getConstant(0, NVT); 5147 Hi = InL; 5148 } else { 5149 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5150 Hi = DAG.getNode(ISD::OR, NVT, 5151 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5152 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5153 } 5154 return true; 5155 case ISD::SRL: 5156 if (Cst > VTBits) { 5157 Lo = DAG.getConstant(0, NVT); 5158 Hi = DAG.getConstant(0, NVT); 5159 } else if (Cst > NVTBits) { 5160 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5161 Hi = DAG.getConstant(0, NVT); 5162 } else if (Cst == NVTBits) { 5163 Lo = InH; 5164 Hi = DAG.getConstant(0, NVT); 5165 } else { 5166 Lo = DAG.getNode(ISD::OR, NVT, 5167 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5168 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5169 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5170 } 5171 return true; 5172 case ISD::SRA: 5173 if (Cst > VTBits) { 5174 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5175 DAG.getConstant(NVTBits-1, ShTy)); 5176 } else if (Cst > NVTBits) { 5177 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5178 DAG.getConstant(Cst-NVTBits, ShTy)); 5179 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5180 DAG.getConstant(NVTBits-1, ShTy)); 5181 } else if (Cst == NVTBits) { 5182 Lo = InH; 5183 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5184 DAG.getConstant(NVTBits-1, ShTy)); 5185 } else { 5186 Lo = DAG.getNode(ISD::OR, NVT, 5187 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5188 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5189 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5190 } 5191 return true; 5192 } 5193 } 5194 5195 // Okay, the shift amount isn't constant. However, if we can tell that it is 5196 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5197 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5198 APInt KnownZero, KnownOne; 5199 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5200 5201 // If we know that if any of the high bits of the shift amount are one, then 5202 // we can do this as a couple of simple shifts. 5203 if (KnownOne.intersects(Mask)) { 5204 // Mask out the high bit, which we know is set. 5205 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5206 DAG.getConstant(~Mask, Amt.getValueType())); 5207 5208 // Expand the incoming operand to be shifted, so that we have its parts 5209 SDOperand InL, InH; 5210 ExpandOp(Op, InL, InH); 5211 switch(Opc) { 5212 case ISD::SHL: 5213 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5214 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5215 return true; 5216 case ISD::SRL: 5217 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5218 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5219 return true; 5220 case ISD::SRA: 5221 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5222 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5223 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5224 return true; 5225 } 5226 } 5227 5228 // If we know that the high bits of the shift amount are all zero, then we can 5229 // do this as a couple of simple shifts. 5230 if ((KnownZero & Mask) == Mask) { 5231 // Compute 32-amt. 5232 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5233 DAG.getConstant(NVTBits, Amt.getValueType()), 5234 Amt); 5235 5236 // Expand the incoming operand to be shifted, so that we have its parts 5237 SDOperand InL, InH; 5238 ExpandOp(Op, InL, InH); 5239 switch(Opc) { 5240 case ISD::SHL: 5241 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5242 Hi = DAG.getNode(ISD::OR, NVT, 5243 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5244 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5245 return true; 5246 case ISD::SRL: 5247 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5248 Lo = DAG.getNode(ISD::OR, NVT, 5249 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5250 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5251 return true; 5252 case ISD::SRA: 5253 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5254 Lo = DAG.getNode(ISD::OR, NVT, 5255 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5256 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5257 return true; 5258 } 5259 } 5260 5261 return false; 5262} 5263 5264 5265// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5266// does not fit into a register, return the lo part and set the hi part to the 5267// by-reg argument. If it does fit into a single register, return the result 5268// and leave the Hi part unset. 5269SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5270 bool isSigned, SDOperand &Hi) { 5271 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5272 // The input chain to this libcall is the entry node of the function. 5273 // Legalizing the call will automatically add the previous call to the 5274 // dependence. 5275 SDOperand InChain = DAG.getEntryNode(); 5276 5277 TargetLowering::ArgListTy Args; 5278 TargetLowering::ArgListEntry Entry; 5279 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5280 MVT ArgVT = Node->getOperand(i).getValueType(); 5281 const Type *ArgTy = ArgVT.getTypeForMVT(); 5282 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5283 Entry.isSExt = isSigned; 5284 Entry.isZExt = !isSigned; 5285 Args.push_back(Entry); 5286 } 5287 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5288 TLI.getPointerTy()); 5289 5290 // Splice the libcall in wherever FindInputOutputChains tells us to. 5291 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5292 std::pair<SDOperand,SDOperand> CallInfo = 5293 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5294 false, Callee, Args, DAG); 5295 5296 // Legalize the call sequence, starting with the chain. This will advance 5297 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5298 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5299 LegalizeOp(CallInfo.second); 5300 SDOperand Result; 5301 switch (getTypeAction(CallInfo.first.getValueType())) { 5302 default: assert(0 && "Unknown thing"); 5303 case Legal: 5304 Result = CallInfo.first; 5305 break; 5306 case Expand: 5307 ExpandOp(CallInfo.first, Result, Hi); 5308 break; 5309 } 5310 return Result; 5311} 5312 5313 5314/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5315/// 5316SDOperand SelectionDAGLegalize:: 5317ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) { 5318 MVT SourceVT = Source.getValueType(); 5319 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5320 5321 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5322 if (!isSigned && SourceVT != MVT::i32) { 5323 // The integer value loaded will be incorrectly if the 'sign bit' of the 5324 // incoming integer is set. To handle this, we dynamically test to see if 5325 // it is set, and, if so, add a fudge factor. 5326 SDOperand Hi; 5327 if (ExpandSource) { 5328 SDOperand Lo; 5329 ExpandOp(Source, Lo, Hi); 5330 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5331 } else { 5332 // The comparison for the sign bit will use the entire operand. 5333 Hi = Source; 5334 } 5335 5336 // If this is unsigned, and not supported, first perform the conversion to 5337 // signed, then adjust the result if the sign bit is set. 5338 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); 5339 5340 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5341 DAG.getConstant(0, Hi.getValueType()), 5342 ISD::SETLT); 5343 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5344 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5345 SignSet, Four, Zero); 5346 uint64_t FF = 0x5f800000ULL; 5347 if (TLI.isLittleEndian()) FF <<= 32; 5348 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5349 5350 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5351 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5352 SDOperand FudgeInReg; 5353 if (DestTy == MVT::f32) 5354 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5355 PseudoSourceValue::getConstantPool(), 0); 5356 else if (DestTy.bitsGT(MVT::f32)) 5357 // FIXME: Avoid the extend by construction the right constantpool? 5358 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5359 CPIdx, 5360 PseudoSourceValue::getConstantPool(), 0, 5361 MVT::f32); 5362 else 5363 assert(0 && "Unexpected conversion"); 5364 5365 MVT SCVT = SignedConv.getValueType(); 5366 if (SCVT != DestTy) { 5367 // Destination type needs to be expanded as well. The FADD now we are 5368 // constructing will be expanded into a libcall. 5369 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5370 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5371 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5372 SignedConv, SignedConv.getValue(1)); 5373 } 5374 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5375 } 5376 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5377 } 5378 5379 // Check to see if the target has a custom way to lower this. If so, use it. 5380 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5381 default: assert(0 && "This action not implemented for this operation!"); 5382 case TargetLowering::Legal: 5383 case TargetLowering::Expand: 5384 break; // This case is handled below. 5385 case TargetLowering::Custom: { 5386 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5387 Source), DAG); 5388 if (NV.Val) 5389 return LegalizeOp(NV); 5390 break; // The target decided this was legal after all 5391 } 5392 } 5393 5394 // Expand the source, then glue it back together for the call. We must expand 5395 // the source in case it is shared (this pass of legalize must traverse it). 5396 if (ExpandSource) { 5397 SDOperand SrcLo, SrcHi; 5398 ExpandOp(Source, SrcLo, SrcHi); 5399 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5400 } 5401 5402 RTLIB::Libcall LC; 5403 if (SourceVT == MVT::i32) { 5404 if (DestTy == MVT::f32) 5405 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5406 else { 5407 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5408 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5409 } 5410 } else if (SourceVT == MVT::i64) { 5411 if (DestTy == MVT::f32) 5412 LC = RTLIB::SINTTOFP_I64_F32; 5413 else if (DestTy == MVT::f64) 5414 LC = RTLIB::SINTTOFP_I64_F64; 5415 else if (DestTy == MVT::f80) 5416 LC = RTLIB::SINTTOFP_I64_F80; 5417 else { 5418 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5419 LC = RTLIB::SINTTOFP_I64_PPCF128; 5420 } 5421 } else if (SourceVT == MVT::i128) { 5422 if (DestTy == MVT::f32) 5423 LC = RTLIB::SINTTOFP_I128_F32; 5424 else if (DestTy == MVT::f64) 5425 LC = RTLIB::SINTTOFP_I128_F64; 5426 else if (DestTy == MVT::f80) 5427 LC = RTLIB::SINTTOFP_I128_F80; 5428 else { 5429 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5430 LC = RTLIB::SINTTOFP_I128_PPCF128; 5431 } 5432 } else { 5433 assert(0 && "Unknown int value type"); 5434 } 5435 5436 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5437 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5438 SDOperand HiPart; 5439 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart); 5440 if (Result.getValueType() != DestTy && HiPart.Val) 5441 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5442 return Result; 5443} 5444 5445/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5446/// INT_TO_FP operation of the specified operand when the target requests that 5447/// we expand it. At this point, we know that the result and operand types are 5448/// legal for the target. 5449SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5450 SDOperand Op0, 5451 MVT DestVT) { 5452 if (Op0.getValueType() == MVT::i32) { 5453 // simple 32-bit [signed|unsigned] integer to float/double expansion 5454 5455 // Get the stack frame index of a 8 byte buffer. 5456 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5457 5458 // word offset constant for Hi/Lo address computation 5459 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5460 // set up Hi and Lo (into buffer) address based on endian 5461 SDOperand Hi = StackSlot; 5462 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5463 if (TLI.isLittleEndian()) 5464 std::swap(Hi, Lo); 5465 5466 // if signed map to unsigned space 5467 SDOperand Op0Mapped; 5468 if (isSigned) { 5469 // constant used to invert sign bit (signed to unsigned mapping) 5470 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5471 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5472 } else { 5473 Op0Mapped = Op0; 5474 } 5475 // store the lo of the constructed double - based on integer input 5476 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5477 Op0Mapped, Lo, NULL, 0); 5478 // initial hi portion of constructed double 5479 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5480 // store the hi of the constructed double - biased exponent 5481 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5482 // load the constructed double 5483 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5484 // FP constant to bias correct the final result 5485 SDOperand Bias = DAG.getConstantFP(isSigned ? 5486 BitsToDouble(0x4330000080000000ULL) 5487 : BitsToDouble(0x4330000000000000ULL), 5488 MVT::f64); 5489 // subtract the bias 5490 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5491 // final result 5492 SDOperand Result; 5493 // handle final rounding 5494 if (DestVT == MVT::f64) { 5495 // do nothing 5496 Result = Sub; 5497 } else if (DestVT.bitsLT(MVT::f64)) { 5498 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5499 DAG.getIntPtrConstant(0)); 5500 } else if (DestVT.bitsGT(MVT::f64)) { 5501 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5502 } 5503 return Result; 5504 } 5505 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5506 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5507 5508 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5509 DAG.getConstant(0, Op0.getValueType()), 5510 ISD::SETLT); 5511 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5512 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5513 SignSet, Four, Zero); 5514 5515 // If the sign bit of the integer is set, the large number will be treated 5516 // as a negative number. To counteract this, the dynamic code adds an 5517 // offset depending on the data type. 5518 uint64_t FF; 5519 switch (Op0.getValueType().getSimpleVT()) { 5520 default: assert(0 && "Unsupported integer type!"); 5521 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5522 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5523 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5524 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5525 } 5526 if (TLI.isLittleEndian()) FF <<= 32; 5527 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5528 5529 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5530 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5531 SDOperand FudgeInReg; 5532 if (DestVT == MVT::f32) 5533 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5534 PseudoSourceValue::getConstantPool(), 0); 5535 else { 5536 FudgeInReg = 5537 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5538 DAG.getEntryNode(), CPIdx, 5539 PseudoSourceValue::getConstantPool(), 0, 5540 MVT::f32)); 5541 } 5542 5543 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5544} 5545 5546/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5547/// *INT_TO_FP operation of the specified operand when the target requests that 5548/// we promote it. At this point, we know that the result and operand types are 5549/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5550/// operation that takes a larger input. 5551SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5552 MVT DestVT, 5553 bool isSigned) { 5554 // First step, figure out the appropriate *INT_TO_FP operation to use. 5555 MVT NewInTy = LegalOp.getValueType(); 5556 5557 unsigned OpToUse = 0; 5558 5559 // Scan for the appropriate larger type to use. 5560 while (1) { 5561 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 5562 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 5563 5564 // If the target supports SINT_TO_FP of this type, use it. 5565 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5566 default: break; 5567 case TargetLowering::Legal: 5568 if (!TLI.isTypeLegal(NewInTy)) 5569 break; // Can't use this datatype. 5570 // FALL THROUGH. 5571 case TargetLowering::Custom: 5572 OpToUse = ISD::SINT_TO_FP; 5573 break; 5574 } 5575 if (OpToUse) break; 5576 if (isSigned) continue; 5577 5578 // If the target supports UINT_TO_FP of this type, use it. 5579 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5580 default: break; 5581 case TargetLowering::Legal: 5582 if (!TLI.isTypeLegal(NewInTy)) 5583 break; // Can't use this datatype. 5584 // FALL THROUGH. 5585 case TargetLowering::Custom: 5586 OpToUse = ISD::UINT_TO_FP; 5587 break; 5588 } 5589 if (OpToUse) break; 5590 5591 // Otherwise, try a larger type. 5592 } 5593 5594 // Okay, we found the operation and type to use. Zero extend our input to the 5595 // desired type then run the operation on it. 5596 return DAG.getNode(OpToUse, DestVT, 5597 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5598 NewInTy, LegalOp)); 5599} 5600 5601/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5602/// FP_TO_*INT operation of the specified operand when the target requests that 5603/// we promote it. At this point, we know that the result and operand types are 5604/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5605/// operation that returns a larger result. 5606SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5607 MVT DestVT, 5608 bool isSigned) { 5609 // First step, figure out the appropriate FP_TO*INT operation to use. 5610 MVT NewOutTy = DestVT; 5611 5612 unsigned OpToUse = 0; 5613 5614 // Scan for the appropriate larger type to use. 5615 while (1) { 5616 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 5617 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 5618 5619 // If the target supports FP_TO_SINT returning this type, use it. 5620 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5621 default: break; 5622 case TargetLowering::Legal: 5623 if (!TLI.isTypeLegal(NewOutTy)) 5624 break; // Can't use this datatype. 5625 // FALL THROUGH. 5626 case TargetLowering::Custom: 5627 OpToUse = ISD::FP_TO_SINT; 5628 break; 5629 } 5630 if (OpToUse) break; 5631 5632 // If the target supports FP_TO_UINT of this type, use it. 5633 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5634 default: break; 5635 case TargetLowering::Legal: 5636 if (!TLI.isTypeLegal(NewOutTy)) 5637 break; // Can't use this datatype. 5638 // FALL THROUGH. 5639 case TargetLowering::Custom: 5640 OpToUse = ISD::FP_TO_UINT; 5641 break; 5642 } 5643 if (OpToUse) break; 5644 5645 // Otherwise, try a larger type. 5646 } 5647 5648 5649 // Okay, we found the operation and type to use. 5650 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5651 5652 // If the operation produces an invalid type, it must be custom lowered. Use 5653 // the target lowering hooks to expand it. Just keep the low part of the 5654 // expanded operation, we know that we're truncating anyway. 5655 if (getTypeAction(NewOutTy) == Expand) { 5656 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5657 assert(Operation.Val && "Didn't return anything"); 5658 } 5659 5660 // Truncate the result of the extended FP_TO_*INT operation to the desired 5661 // size. 5662 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5663} 5664 5665/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5666/// 5667SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5668 MVT VT = Op.getValueType(); 5669 MVT SHVT = TLI.getShiftAmountTy(); 5670 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5671 switch (VT.getSimpleVT()) { 5672 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5673 case MVT::i16: 5674 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5675 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5676 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5677 case MVT::i32: 5678 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5679 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5680 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5681 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5682 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5683 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5684 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5685 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5686 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5687 case MVT::i64: 5688 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5689 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5690 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5691 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5692 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5693 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5694 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5695 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5696 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5697 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5698 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5699 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5700 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5701 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5702 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5703 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5704 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5705 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5706 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5707 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5708 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5709 } 5710} 5711 5712/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5713/// 5714SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5715 switch (Opc) { 5716 default: assert(0 && "Cannot expand this yet!"); 5717 case ISD::CTPOP: { 5718 static const uint64_t mask[6] = { 5719 0x5555555555555555ULL, 0x3333333333333333ULL, 5720 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5721 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5722 }; 5723 MVT VT = Op.getValueType(); 5724 MVT ShVT = TLI.getShiftAmountTy(); 5725 unsigned len = VT.getSizeInBits(); 5726 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5727 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5728 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5729 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5730 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5731 DAG.getNode(ISD::AND, VT, 5732 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5733 } 5734 return Op; 5735 } 5736 case ISD::CTLZ: { 5737 // for now, we do this: 5738 // x = x | (x >> 1); 5739 // x = x | (x >> 2); 5740 // ... 5741 // x = x | (x >>16); 5742 // x = x | (x >>32); // for 64-bit input 5743 // return popcount(~x); 5744 // 5745 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5746 MVT VT = Op.getValueType(); 5747 MVT ShVT = TLI.getShiftAmountTy(); 5748 unsigned len = VT.getSizeInBits(); 5749 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5750 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5751 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5752 } 5753 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5754 return DAG.getNode(ISD::CTPOP, VT, Op); 5755 } 5756 case ISD::CTTZ: { 5757 // for now, we use: { return popcount(~x & (x - 1)); } 5758 // unless the target has ctlz but not ctpop, in which case we use: 5759 // { return 32 - nlz(~x & (x-1)); } 5760 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5761 MVT VT = Op.getValueType(); 5762 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5763 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5764 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5765 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5766 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5767 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5768 TLI.isOperationLegal(ISD::CTLZ, VT)) 5769 return DAG.getNode(ISD::SUB, VT, 5770 DAG.getConstant(VT.getSizeInBits(), VT), 5771 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5772 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5773 } 5774 } 5775} 5776 5777/// ExpandOp - Expand the specified SDOperand into its two component pieces 5778/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5779/// LegalizeNodes map is filled in for any results that are not expanded, the 5780/// ExpandedNodes map is filled in for any results that are expanded, and the 5781/// Lo/Hi values are returned. 5782void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5783 MVT VT = Op.getValueType(); 5784 MVT NVT = TLI.getTypeToTransformTo(VT); 5785 SDNode *Node = Op.Val; 5786 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5787 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 5788 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 5789 5790 // See if we already expanded it. 5791 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5792 = ExpandedNodes.find(Op); 5793 if (I != ExpandedNodes.end()) { 5794 Lo = I->second.first; 5795 Hi = I->second.second; 5796 return; 5797 } 5798 5799 switch (Node->getOpcode()) { 5800 case ISD::CopyFromReg: 5801 assert(0 && "CopyFromReg must be legal!"); 5802 case ISD::FP_ROUND_INREG: 5803 if (VT == MVT::ppcf128 && 5804 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5805 TargetLowering::Custom) { 5806 SDOperand SrcLo, SrcHi, Src; 5807 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5808 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5809 SDOperand Result = TLI.LowerOperation( 5810 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5811 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5812 Lo = Result.Val->getOperand(0); 5813 Hi = Result.Val->getOperand(1); 5814 break; 5815 } 5816 // fall through 5817 default: 5818#ifndef NDEBUG 5819 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5820#endif 5821 assert(0 && "Do not know how to expand this operator!"); 5822 abort(); 5823 case ISD::EXTRACT_ELEMENT: 5824 ExpandOp(Node->getOperand(0), Lo, Hi); 5825 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5826 return ExpandOp(Hi, Lo, Hi); 5827 return ExpandOp(Lo, Lo, Hi); 5828 case ISD::EXTRACT_VECTOR_ELT: 5829 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5830 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5831 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5832 return ExpandOp(Lo, Lo, Hi); 5833 case ISD::UNDEF: 5834 Lo = DAG.getNode(ISD::UNDEF, NVT); 5835 Hi = DAG.getNode(ISD::UNDEF, NVT); 5836 break; 5837 case ISD::Constant: { 5838 unsigned NVTBits = NVT.getSizeInBits(); 5839 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5840 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5841 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5842 break; 5843 } 5844 case ISD::ConstantFP: { 5845 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5846 if (CFP->getValueType(0) == MVT::ppcf128) { 5847 APInt api = CFP->getValueAPF().convertToAPInt(); 5848 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5849 MVT::f64); 5850 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5851 MVT::f64); 5852 break; 5853 } 5854 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5855 if (getTypeAction(Lo.getValueType()) == Expand) 5856 ExpandOp(Lo, Lo, Hi); 5857 break; 5858 } 5859 case ISD::BUILD_PAIR: 5860 // Return the operands. 5861 Lo = Node->getOperand(0); 5862 Hi = Node->getOperand(1); 5863 break; 5864 5865 case ISD::MERGE_VALUES: 5866 if (Node->getNumValues() == 1) { 5867 ExpandOp(Op.getOperand(0), Lo, Hi); 5868 break; 5869 } 5870 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5871 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5872 Op.getValue(1).getValueType() == MVT::Other && 5873 "unhandled MERGE_VALUES"); 5874 ExpandOp(Op.getOperand(0), Lo, Hi); 5875 // Remember that we legalized the chain. 5876 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5877 break; 5878 5879 case ISD::SIGN_EXTEND_INREG: 5880 ExpandOp(Node->getOperand(0), Lo, Hi); 5881 // sext_inreg the low part if needed. 5882 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5883 5884 // The high part gets the sign extension from the lo-part. This handles 5885 // things like sextinreg V:i64 from i8. 5886 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5887 DAG.getConstant(NVT.getSizeInBits()-1, 5888 TLI.getShiftAmountTy())); 5889 break; 5890 5891 case ISD::BSWAP: { 5892 ExpandOp(Node->getOperand(0), Lo, Hi); 5893 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5894 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5895 Lo = TempLo; 5896 break; 5897 } 5898 5899 case ISD::CTPOP: 5900 ExpandOp(Node->getOperand(0), Lo, Hi); 5901 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5902 DAG.getNode(ISD::CTPOP, NVT, Lo), 5903 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5904 Hi = DAG.getConstant(0, NVT); 5905 break; 5906 5907 case ISD::CTLZ: { 5908 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5909 ExpandOp(Node->getOperand(0), Lo, Hi); 5910 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5911 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5912 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5913 ISD::SETNE); 5914 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5915 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5916 5917 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5918 Hi = DAG.getConstant(0, NVT); 5919 break; 5920 } 5921 5922 case ISD::CTTZ: { 5923 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5924 ExpandOp(Node->getOperand(0), Lo, Hi); 5925 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5926 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5927 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5928 ISD::SETNE); 5929 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5930 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5931 5932 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5933 Hi = DAG.getConstant(0, NVT); 5934 break; 5935 } 5936 5937 case ISD::VAARG: { 5938 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5939 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5940 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5941 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5942 5943 // Remember that we legalized the chain. 5944 Hi = LegalizeOp(Hi); 5945 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5946 if (TLI.isBigEndian()) 5947 std::swap(Lo, Hi); 5948 break; 5949 } 5950 5951 case ISD::LOAD: { 5952 LoadSDNode *LD = cast<LoadSDNode>(Node); 5953 SDOperand Ch = LD->getChain(); // Legalize the chain. 5954 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5955 ISD::LoadExtType ExtType = LD->getExtensionType(); 5956 int SVOffset = LD->getSrcValueOffset(); 5957 unsigned Alignment = LD->getAlignment(); 5958 bool isVolatile = LD->isVolatile(); 5959 5960 if (ExtType == ISD::NON_EXTLOAD) { 5961 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5962 isVolatile, Alignment); 5963 if (VT == MVT::f32 || VT == MVT::f64) { 5964 // f32->i32 or f64->i64 one to one expansion. 5965 // Remember that we legalized the chain. 5966 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5967 // Recursively expand the new load. 5968 if (getTypeAction(NVT) == Expand) 5969 ExpandOp(Lo, Lo, Hi); 5970 break; 5971 } 5972 5973 // Increment the pointer to the other half. 5974 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 5975 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5976 DAG.getIntPtrConstant(IncrementSize)); 5977 SVOffset += IncrementSize; 5978 Alignment = MinAlign(Alignment, IncrementSize); 5979 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5980 isVolatile, Alignment); 5981 5982 // Build a factor node to remember that this load is independent of the 5983 // other one. 5984 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5985 Hi.getValue(1)); 5986 5987 // Remember that we legalized the chain. 5988 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5989 if (TLI.isBigEndian()) 5990 std::swap(Lo, Hi); 5991 } else { 5992 MVT EVT = LD->getMemoryVT(); 5993 5994 if ((VT == MVT::f64 && EVT == MVT::f32) || 5995 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5996 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5997 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5998 SVOffset, isVolatile, Alignment); 5999 // Remember that we legalized the chain. 6000 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 6001 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6002 break; 6003 } 6004 6005 if (EVT == NVT) 6006 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 6007 SVOffset, isVolatile, Alignment); 6008 else 6009 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 6010 SVOffset, EVT, isVolatile, 6011 Alignment); 6012 6013 // Remember that we legalized the chain. 6014 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 6015 6016 if (ExtType == ISD::SEXTLOAD) { 6017 // The high part is obtained by SRA'ing all but one of the bits of the 6018 // lo part. 6019 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6020 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6021 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6022 } else if (ExtType == ISD::ZEXTLOAD) { 6023 // The high part is just a zero. 6024 Hi = DAG.getConstant(0, NVT); 6025 } else /* if (ExtType == ISD::EXTLOAD) */ { 6026 // The high part is undefined. 6027 Hi = DAG.getNode(ISD::UNDEF, NVT); 6028 } 6029 } 6030 break; 6031 } 6032 case ISD::AND: 6033 case ISD::OR: 6034 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6035 SDOperand LL, LH, RL, RH; 6036 ExpandOp(Node->getOperand(0), LL, LH); 6037 ExpandOp(Node->getOperand(1), RL, RH); 6038 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6039 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6040 break; 6041 } 6042 case ISD::SELECT: { 6043 SDOperand LL, LH, RL, RH; 6044 ExpandOp(Node->getOperand(1), LL, LH); 6045 ExpandOp(Node->getOperand(2), RL, RH); 6046 if (getTypeAction(NVT) == Expand) 6047 NVT = TLI.getTypeToExpandTo(NVT); 6048 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6049 if (VT != MVT::f32) 6050 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6051 break; 6052 } 6053 case ISD::SELECT_CC: { 6054 SDOperand TL, TH, FL, FH; 6055 ExpandOp(Node->getOperand(2), TL, TH); 6056 ExpandOp(Node->getOperand(3), FL, FH); 6057 if (getTypeAction(NVT) == Expand) 6058 NVT = TLI.getTypeToExpandTo(NVT); 6059 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6060 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6061 if (VT != MVT::f32) 6062 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6063 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6064 break; 6065 } 6066 case ISD::ANY_EXTEND: 6067 // The low part is any extension of the input (which degenerates to a copy). 6068 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6069 // The high part is undefined. 6070 Hi = DAG.getNode(ISD::UNDEF, NVT); 6071 break; 6072 case ISD::SIGN_EXTEND: { 6073 // The low part is just a sign extension of the input (which degenerates to 6074 // a copy). 6075 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6076 6077 // The high part is obtained by SRA'ing all but one of the bits of the lo 6078 // part. 6079 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6080 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6081 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6082 break; 6083 } 6084 case ISD::ZERO_EXTEND: 6085 // The low part is just a zero extension of the input (which degenerates to 6086 // a copy). 6087 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6088 6089 // The high part is just a zero. 6090 Hi = DAG.getConstant(0, NVT); 6091 break; 6092 6093 case ISD::TRUNCATE: { 6094 // The input value must be larger than this value. Expand *it*. 6095 SDOperand NewLo; 6096 ExpandOp(Node->getOperand(0), NewLo, Hi); 6097 6098 // The low part is now either the right size, or it is closer. If not the 6099 // right size, make an illegal truncate so we recursively expand it. 6100 if (NewLo.getValueType() != Node->getValueType(0)) 6101 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6102 ExpandOp(NewLo, Lo, Hi); 6103 break; 6104 } 6105 6106 case ISD::BIT_CONVERT: { 6107 SDOperand Tmp; 6108 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6109 // If the target wants to, allow it to lower this itself. 6110 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6111 case Expand: assert(0 && "cannot expand FP!"); 6112 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6113 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6114 } 6115 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6116 } 6117 6118 // f32 / f64 must be expanded to i32 / i64. 6119 if (VT == MVT::f32 || VT == MVT::f64) { 6120 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6121 if (getTypeAction(NVT) == Expand) 6122 ExpandOp(Lo, Lo, Hi); 6123 break; 6124 } 6125 6126 // If source operand will be expanded to the same type as VT, i.e. 6127 // i64 <- f64, i32 <- f32, expand the source operand instead. 6128 MVT VT0 = Node->getOperand(0).getValueType(); 6129 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6130 ExpandOp(Node->getOperand(0), Lo, Hi); 6131 break; 6132 } 6133 6134 // Turn this into a load/store pair by default. 6135 if (Tmp.Val == 0) 6136 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6137 6138 ExpandOp(Tmp, Lo, Hi); 6139 break; 6140 } 6141 6142 case ISD::READCYCLECOUNTER: { 6143 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6144 TargetLowering::Custom && 6145 "Must custom expand ReadCycleCounter"); 6146 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6147 assert(Tmp.Val && "Node must be custom expanded!"); 6148 ExpandOp(Tmp.getValue(0), Lo, Hi); 6149 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6150 LegalizeOp(Tmp.getValue(1))); 6151 break; 6152 } 6153 6154 case ISD::ATOMIC_LCS: { 6155 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6156 assert(Tmp.Val && "Node must be custom expanded!"); 6157 ExpandOp(Tmp.getValue(0), Lo, Hi); 6158 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6159 LegalizeOp(Tmp.getValue(1))); 6160 break; 6161 } 6162 6163 6164 6165 // These operators cannot be expanded directly, emit them as calls to 6166 // library functions. 6167 case ISD::FP_TO_SINT: { 6168 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6169 SDOperand Op; 6170 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6171 case Expand: assert(0 && "cannot expand FP!"); 6172 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6173 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6174 } 6175 6176 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6177 6178 // Now that the custom expander is done, expand the result, which is still 6179 // VT. 6180 if (Op.Val) { 6181 ExpandOp(Op, Lo, Hi); 6182 break; 6183 } 6184 } 6185 6186 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6187 if (VT == MVT::i64) { 6188 if (Node->getOperand(0).getValueType() == MVT::f32) 6189 LC = RTLIB::FPTOSINT_F32_I64; 6190 else if (Node->getOperand(0).getValueType() == MVT::f64) 6191 LC = RTLIB::FPTOSINT_F64_I64; 6192 else if (Node->getOperand(0).getValueType() == MVT::f80) 6193 LC = RTLIB::FPTOSINT_F80_I64; 6194 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6195 LC = RTLIB::FPTOSINT_PPCF128_I64; 6196 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6197 } else if (VT == MVT::i128) { 6198 if (Node->getOperand(0).getValueType() == MVT::f32) 6199 LC = RTLIB::FPTOSINT_F32_I128; 6200 else if (Node->getOperand(0).getValueType() == MVT::f64) 6201 LC = RTLIB::FPTOSINT_F64_I128; 6202 else if (Node->getOperand(0).getValueType() == MVT::f80) 6203 LC = RTLIB::FPTOSINT_F80_I128; 6204 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6205 LC = RTLIB::FPTOSINT_PPCF128_I128; 6206 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6207 } else { 6208 assert(0 && "Unexpected uint-to-fp conversion!"); 6209 } 6210 break; 6211 } 6212 6213 case ISD::FP_TO_UINT: { 6214 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6215 SDOperand Op; 6216 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6217 case Expand: assert(0 && "cannot expand FP!"); 6218 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6219 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6220 } 6221 6222 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6223 6224 // Now that the custom expander is done, expand the result. 6225 if (Op.Val) { 6226 ExpandOp(Op, Lo, Hi); 6227 break; 6228 } 6229 } 6230 6231 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6232 if (VT == MVT::i64) { 6233 if (Node->getOperand(0).getValueType() == MVT::f32) 6234 LC = RTLIB::FPTOUINT_F32_I64; 6235 else if (Node->getOperand(0).getValueType() == MVT::f64) 6236 LC = RTLIB::FPTOUINT_F64_I64; 6237 else if (Node->getOperand(0).getValueType() == MVT::f80) 6238 LC = RTLIB::FPTOUINT_F80_I64; 6239 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6240 LC = RTLIB::FPTOUINT_PPCF128_I64; 6241 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6242 } else if (VT == MVT::i128) { 6243 if (Node->getOperand(0).getValueType() == MVT::f32) 6244 LC = RTLIB::FPTOUINT_F32_I128; 6245 else if (Node->getOperand(0).getValueType() == MVT::f64) 6246 LC = RTLIB::FPTOUINT_F64_I128; 6247 else if (Node->getOperand(0).getValueType() == MVT::f80) 6248 LC = RTLIB::FPTOUINT_F80_I128; 6249 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6250 LC = RTLIB::FPTOUINT_PPCF128_I128; 6251 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6252 } else { 6253 assert(0 && "Unexpected uint-to-fp conversion!"); 6254 } 6255 break; 6256 } 6257 6258 case ISD::SHL: { 6259 // If the target wants custom lowering, do so. 6260 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6261 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6262 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6263 Op = TLI.LowerOperation(Op, DAG); 6264 if (Op.Val) { 6265 // Now that the custom expander is done, expand the result, which is 6266 // still VT. 6267 ExpandOp(Op, Lo, Hi); 6268 break; 6269 } 6270 } 6271 6272 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6273 // this X << 1 as X+X. 6274 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6275 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6276 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6277 SDOperand LoOps[2], HiOps[3]; 6278 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6279 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6280 LoOps[1] = LoOps[0]; 6281 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6282 6283 HiOps[1] = HiOps[0]; 6284 HiOps[2] = Lo.getValue(1); 6285 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6286 break; 6287 } 6288 } 6289 6290 // If we can emit an efficient shift operation, do so now. 6291 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6292 break; 6293 6294 // If this target supports SHL_PARTS, use it. 6295 TargetLowering::LegalizeAction Action = 6296 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6297 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6298 Action == TargetLowering::Custom) { 6299 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6300 break; 6301 } 6302 6303 // Otherwise, emit a libcall. 6304 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6305 break; 6306 } 6307 6308 case ISD::SRA: { 6309 // If the target wants custom lowering, do so. 6310 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6311 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6312 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6313 Op = TLI.LowerOperation(Op, DAG); 6314 if (Op.Val) { 6315 // Now that the custom expander is done, expand the result, which is 6316 // still VT. 6317 ExpandOp(Op, Lo, Hi); 6318 break; 6319 } 6320 } 6321 6322 // If we can emit an efficient shift operation, do so now. 6323 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6324 break; 6325 6326 // If this target supports SRA_PARTS, use it. 6327 TargetLowering::LegalizeAction Action = 6328 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6329 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6330 Action == TargetLowering::Custom) { 6331 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6332 break; 6333 } 6334 6335 // Otherwise, emit a libcall. 6336 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6337 break; 6338 } 6339 6340 case ISD::SRL: { 6341 // If the target wants custom lowering, do so. 6342 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6343 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6344 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6345 Op = TLI.LowerOperation(Op, DAG); 6346 if (Op.Val) { 6347 // Now that the custom expander is done, expand the result, which is 6348 // still VT. 6349 ExpandOp(Op, Lo, Hi); 6350 break; 6351 } 6352 } 6353 6354 // If we can emit an efficient shift operation, do so now. 6355 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6356 break; 6357 6358 // If this target supports SRL_PARTS, use it. 6359 TargetLowering::LegalizeAction Action = 6360 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6361 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6362 Action == TargetLowering::Custom) { 6363 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6364 break; 6365 } 6366 6367 // Otherwise, emit a libcall. 6368 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6369 break; 6370 } 6371 6372 case ISD::ADD: 6373 case ISD::SUB: { 6374 // If the target wants to custom expand this, let them. 6375 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6376 TargetLowering::Custom) { 6377 Op = TLI.LowerOperation(Op, DAG); 6378 if (Op.Val) { 6379 ExpandOp(Op, Lo, Hi); 6380 break; 6381 } 6382 } 6383 6384 // Expand the subcomponents. 6385 SDOperand LHSL, LHSH, RHSL, RHSH; 6386 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6387 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6388 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6389 SDOperand LoOps[2], HiOps[3]; 6390 LoOps[0] = LHSL; 6391 LoOps[1] = RHSL; 6392 HiOps[0] = LHSH; 6393 HiOps[1] = RHSH; 6394 if (Node->getOpcode() == ISD::ADD) { 6395 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6396 HiOps[2] = Lo.getValue(1); 6397 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6398 } else { 6399 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6400 HiOps[2] = Lo.getValue(1); 6401 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6402 } 6403 break; 6404 } 6405 6406 case ISD::ADDC: 6407 case ISD::SUBC: { 6408 // Expand the subcomponents. 6409 SDOperand LHSL, LHSH, RHSL, RHSH; 6410 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6411 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6412 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6413 SDOperand LoOps[2] = { LHSL, RHSL }; 6414 SDOperand HiOps[3] = { LHSH, RHSH }; 6415 6416 if (Node->getOpcode() == ISD::ADDC) { 6417 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6418 HiOps[2] = Lo.getValue(1); 6419 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6420 } else { 6421 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6422 HiOps[2] = Lo.getValue(1); 6423 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6424 } 6425 // Remember that we legalized the flag. 6426 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6427 break; 6428 } 6429 case ISD::ADDE: 6430 case ISD::SUBE: { 6431 // Expand the subcomponents. 6432 SDOperand LHSL, LHSH, RHSL, RHSH; 6433 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6434 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6435 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6436 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6437 SDOperand HiOps[3] = { LHSH, RHSH }; 6438 6439 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6440 HiOps[2] = Lo.getValue(1); 6441 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6442 6443 // Remember that we legalized the flag. 6444 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6445 break; 6446 } 6447 case ISD::MUL: { 6448 // If the target wants to custom expand this, let them. 6449 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6450 SDOperand New = TLI.LowerOperation(Op, DAG); 6451 if (New.Val) { 6452 ExpandOp(New, Lo, Hi); 6453 break; 6454 } 6455 } 6456 6457 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6458 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6459 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6460 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6461 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6462 SDOperand LL, LH, RL, RH; 6463 ExpandOp(Node->getOperand(0), LL, LH); 6464 ExpandOp(Node->getOperand(1), RL, RH); 6465 unsigned OuterBitSize = Op.getValueSizeInBits(); 6466 unsigned InnerBitSize = RH.getValueSizeInBits(); 6467 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6468 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6469 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6470 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6471 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6472 // The inputs are both zero-extended. 6473 if (HasUMUL_LOHI) { 6474 // We can emit a umul_lohi. 6475 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6476 Hi = SDOperand(Lo.Val, 1); 6477 break; 6478 } 6479 if (HasMULHU) { 6480 // We can emit a mulhu+mul. 6481 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6482 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6483 break; 6484 } 6485 } 6486 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6487 // The input values are both sign-extended. 6488 if (HasSMUL_LOHI) { 6489 // We can emit a smul_lohi. 6490 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6491 Hi = SDOperand(Lo.Val, 1); 6492 break; 6493 } 6494 if (HasMULHS) { 6495 // We can emit a mulhs+mul. 6496 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6497 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6498 break; 6499 } 6500 } 6501 if (HasUMUL_LOHI) { 6502 // Lo,Hi = umul LHS, RHS. 6503 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6504 DAG.getVTList(NVT, NVT), LL, RL); 6505 Lo = UMulLOHI; 6506 Hi = UMulLOHI.getValue(1); 6507 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6508 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6509 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6510 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6511 break; 6512 } 6513 if (HasMULHU) { 6514 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6515 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6516 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6517 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6518 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6519 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6520 break; 6521 } 6522 } 6523 6524 // If nothing else, we can make a libcall. 6525 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6526 break; 6527 } 6528 case ISD::SDIV: 6529 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6530 break; 6531 case ISD::UDIV: 6532 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6533 break; 6534 case ISD::SREM: 6535 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6536 break; 6537 case ISD::UREM: 6538 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6539 break; 6540 6541 case ISD::FADD: 6542 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6543 RTLIB::ADD_F64, 6544 RTLIB::ADD_F80, 6545 RTLIB::ADD_PPCF128), 6546 Node, false, Hi); 6547 break; 6548 case ISD::FSUB: 6549 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6550 RTLIB::SUB_F64, 6551 RTLIB::SUB_F80, 6552 RTLIB::SUB_PPCF128), 6553 Node, false, Hi); 6554 break; 6555 case ISD::FMUL: 6556 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6557 RTLIB::MUL_F64, 6558 RTLIB::MUL_F80, 6559 RTLIB::MUL_PPCF128), 6560 Node, false, Hi); 6561 break; 6562 case ISD::FDIV: 6563 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6564 RTLIB::DIV_F64, 6565 RTLIB::DIV_F80, 6566 RTLIB::DIV_PPCF128), 6567 Node, false, Hi); 6568 break; 6569 case ISD::FP_EXTEND: 6570 if (VT == MVT::ppcf128) { 6571 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6572 Node->getOperand(0).getValueType()==MVT::f64); 6573 const uint64_t zero = 0; 6574 if (Node->getOperand(0).getValueType()==MVT::f32) 6575 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6576 else 6577 Hi = Node->getOperand(0); 6578 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6579 break; 6580 } 6581 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi); 6582 break; 6583 case ISD::FP_ROUND: 6584 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi); 6585 break; 6586 case ISD::FPOWI: 6587 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32, 6588 RTLIB::POWI_F64, 6589 RTLIB::POWI_F80, 6590 RTLIB::POWI_PPCF128), 6591 Node, false, Hi); 6592 break; 6593 case ISD::FSQRT: 6594 case ISD::FSIN: 6595 case ISD::FCOS: { 6596 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6597 switch(Node->getOpcode()) { 6598 case ISD::FSQRT: 6599 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6600 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6601 break; 6602 case ISD::FSIN: 6603 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6604 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6605 break; 6606 case ISD::FCOS: 6607 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6608 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6609 break; 6610 default: assert(0 && "Unreachable!"); 6611 } 6612 Lo = ExpandLibCall(LC, Node, false, Hi); 6613 break; 6614 } 6615 case ISD::FABS: { 6616 if (VT == MVT::ppcf128) { 6617 SDOperand Tmp; 6618 ExpandOp(Node->getOperand(0), Lo, Tmp); 6619 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6620 // lo = hi==fabs(hi) ? lo : -lo; 6621 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6622 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6623 DAG.getCondCode(ISD::SETEQ)); 6624 break; 6625 } 6626 SDOperand Mask = (VT == MVT::f64) 6627 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6628 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6629 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6630 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6631 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6632 if (getTypeAction(NVT) == Expand) 6633 ExpandOp(Lo, Lo, Hi); 6634 break; 6635 } 6636 case ISD::FNEG: { 6637 if (VT == MVT::ppcf128) { 6638 ExpandOp(Node->getOperand(0), Lo, Hi); 6639 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6640 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6641 break; 6642 } 6643 SDOperand Mask = (VT == MVT::f64) 6644 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6645 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6646 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6647 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6648 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6649 if (getTypeAction(NVT) == Expand) 6650 ExpandOp(Lo, Lo, Hi); 6651 break; 6652 } 6653 case ISD::FCOPYSIGN: { 6654 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6655 if (getTypeAction(NVT) == Expand) 6656 ExpandOp(Lo, Lo, Hi); 6657 break; 6658 } 6659 case ISD::SINT_TO_FP: 6660 case ISD::UINT_TO_FP: { 6661 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6662 MVT SrcVT = Node->getOperand(0).getValueType(); 6663 6664 // Promote the operand if needed. Do this before checking for 6665 // ppcf128 so conversions of i16 and i8 work. 6666 if (getTypeAction(SrcVT) == Promote) { 6667 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6668 Tmp = isSigned 6669 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6670 DAG.getValueType(SrcVT)) 6671 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6672 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6673 SrcVT = Node->getOperand(0).getValueType(); 6674 } 6675 6676 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6677 static const uint64_t zero = 0; 6678 if (isSigned) { 6679 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6680 Node->getOperand(0))); 6681 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6682 } else { 6683 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6684 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6685 Node->getOperand(0))); 6686 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6687 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6688 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6689 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6690 DAG.getConstant(0, MVT::i32), 6691 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6692 DAG.getConstantFP( 6693 APFloat(APInt(128, 2, TwoE32)), 6694 MVT::ppcf128)), 6695 Hi, 6696 DAG.getCondCode(ISD::SETLT)), 6697 Lo, Hi); 6698 } 6699 break; 6700 } 6701 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6702 // si64->ppcf128 done by libcall, below 6703 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6704 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6705 Lo, Hi); 6706 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6707 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6708 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6709 DAG.getConstant(0, MVT::i64), 6710 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6711 DAG.getConstantFP( 6712 APFloat(APInt(128, 2, TwoE64)), 6713 MVT::ppcf128)), 6714 Hi, 6715 DAG.getCondCode(ISD::SETLT)), 6716 Lo, Hi); 6717 break; 6718 } 6719 6720 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6721 Node->getOperand(0)); 6722 if (getTypeAction(Lo.getValueType()) == Expand) 6723 // float to i32 etc. can be 'expanded' to a single node. 6724 ExpandOp(Lo, Lo, Hi); 6725 break; 6726 } 6727 } 6728 6729 // Make sure the resultant values have been legalized themselves, unless this 6730 // is a type that requires multi-step expansion. 6731 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6732 Lo = LegalizeOp(Lo); 6733 if (Hi.Val) 6734 // Don't legalize the high part if it is expanded to a single node. 6735 Hi = LegalizeOp(Hi); 6736 } 6737 6738 // Remember in a map if the values will be reused later. 6739 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6740 assert(isNew && "Value already expanded?!?"); 6741} 6742 6743/// SplitVectorOp - Given an operand of vector type, break it down into 6744/// two smaller values, still of vector type. 6745void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6746 SDOperand &Hi) { 6747 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 6748 SDNode *Node = Op.Val; 6749 unsigned NumElements = Op.getValueType().getVectorNumElements(); 6750 assert(NumElements > 1 && "Cannot split a single element vector!"); 6751 6752 MVT NewEltVT = Op.getValueType().getVectorElementType(); 6753 6754 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6755 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6756 6757 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 6758 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 6759 6760 // See if we already split it. 6761 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6762 = SplitNodes.find(Op); 6763 if (I != SplitNodes.end()) { 6764 Lo = I->second.first; 6765 Hi = I->second.second; 6766 return; 6767 } 6768 6769 switch (Node->getOpcode()) { 6770 default: 6771#ifndef NDEBUG 6772 Node->dump(&DAG); 6773#endif 6774 assert(0 && "Unhandled operation in SplitVectorOp!"); 6775 case ISD::UNDEF: 6776 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6777 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6778 break; 6779 case ISD::BUILD_PAIR: 6780 Lo = Node->getOperand(0); 6781 Hi = Node->getOperand(1); 6782 break; 6783 case ISD::INSERT_VECTOR_ELT: { 6784 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6785 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6786 unsigned Index = Idx->getValue(); 6787 SDOperand ScalarOp = Node->getOperand(1); 6788 if (Index < NewNumElts_Lo) 6789 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6790 DAG.getIntPtrConstant(Index)); 6791 else 6792 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6793 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6794 break; 6795 } 6796 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6797 Node->getOperand(1), 6798 Node->getOperand(2)); 6799 SplitVectorOp(Tmp, Lo, Hi); 6800 break; 6801 } 6802 case ISD::VECTOR_SHUFFLE: { 6803 // Build the low part. 6804 SDOperand Mask = Node->getOperand(2); 6805 SmallVector<SDOperand, 8> Ops; 6806 MVT PtrVT = TLI.getPointerTy(); 6807 6808 // Insert all of the elements from the input that are needed. We use 6809 // buildvector of extractelement here because the input vectors will have 6810 // to be legalized, so this makes the code simpler. 6811 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6812 SDOperand IdxNode = Mask.getOperand(i); 6813 if (IdxNode.getOpcode() == ISD::UNDEF) { 6814 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6815 continue; 6816 } 6817 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6818 SDOperand InVec = Node->getOperand(0); 6819 if (Idx >= NumElements) { 6820 InVec = Node->getOperand(1); 6821 Idx -= NumElements; 6822 } 6823 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6824 DAG.getConstant(Idx, PtrVT))); 6825 } 6826 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6827 Ops.clear(); 6828 6829 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6830 SDOperand IdxNode = Mask.getOperand(i); 6831 if (IdxNode.getOpcode() == ISD::UNDEF) { 6832 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6833 continue; 6834 } 6835 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6836 SDOperand InVec = Node->getOperand(0); 6837 if (Idx >= NumElements) { 6838 InVec = Node->getOperand(1); 6839 Idx -= NumElements; 6840 } 6841 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6842 DAG.getConstant(Idx, PtrVT))); 6843 } 6844 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6845 break; 6846 } 6847 case ISD::BUILD_VECTOR: { 6848 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6849 Node->op_begin()+NewNumElts_Lo); 6850 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6851 6852 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6853 Node->op_end()); 6854 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6855 break; 6856 } 6857 case ISD::CONCAT_VECTORS: { 6858 // FIXME: Handle non-power-of-two vectors? 6859 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6860 if (NewNumSubvectors == 1) { 6861 Lo = Node->getOperand(0); 6862 Hi = Node->getOperand(1); 6863 } else { 6864 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6865 Node->op_begin()+NewNumSubvectors); 6866 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6867 6868 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6869 Node->op_end()); 6870 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6871 } 6872 break; 6873 } 6874 case ISD::SELECT: { 6875 SDOperand Cond = Node->getOperand(0); 6876 6877 SDOperand LL, LH, RL, RH; 6878 SplitVectorOp(Node->getOperand(1), LL, LH); 6879 SplitVectorOp(Node->getOperand(2), RL, RH); 6880 6881 if (Cond.getValueType().isVector()) { 6882 // Handle a vector merge. 6883 SDOperand CL, CH; 6884 SplitVectorOp(Cond, CL, CH); 6885 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6886 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6887 } else { 6888 // Handle a simple select with vector operands. 6889 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6890 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6891 } 6892 break; 6893 } 6894 case ISD::VSETCC: { 6895 SDOperand LL, LH, RL, RH; 6896 SplitVectorOp(Node->getOperand(0), LL, LH); 6897 SplitVectorOp(Node->getOperand(1), RL, RH); 6898 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 6899 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 6900 break; 6901 } 6902 case ISD::ADD: 6903 case ISD::SUB: 6904 case ISD::MUL: 6905 case ISD::FADD: 6906 case ISD::FSUB: 6907 case ISD::FMUL: 6908 case ISD::SDIV: 6909 case ISD::UDIV: 6910 case ISD::FDIV: 6911 case ISD::FPOW: 6912 case ISD::AND: 6913 case ISD::OR: 6914 case ISD::XOR: 6915 case ISD::UREM: 6916 case ISD::SREM: 6917 case ISD::FREM: { 6918 SDOperand LL, LH, RL, RH; 6919 SplitVectorOp(Node->getOperand(0), LL, LH); 6920 SplitVectorOp(Node->getOperand(1), RL, RH); 6921 6922 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6923 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6924 break; 6925 } 6926 case ISD::FPOWI: { 6927 SDOperand L, H; 6928 SplitVectorOp(Node->getOperand(0), L, H); 6929 6930 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6931 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6932 break; 6933 } 6934 case ISD::CTTZ: 6935 case ISD::CTLZ: 6936 case ISD::CTPOP: 6937 case ISD::FNEG: 6938 case ISD::FABS: 6939 case ISD::FSQRT: 6940 case ISD::FSIN: 6941 case ISD::FCOS: 6942 case ISD::FP_TO_SINT: 6943 case ISD::FP_TO_UINT: 6944 case ISD::SINT_TO_FP: 6945 case ISD::UINT_TO_FP: { 6946 SDOperand L, H; 6947 SplitVectorOp(Node->getOperand(0), L, H); 6948 6949 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6950 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6951 break; 6952 } 6953 case ISD::LOAD: { 6954 LoadSDNode *LD = cast<LoadSDNode>(Node); 6955 SDOperand Ch = LD->getChain(); 6956 SDOperand Ptr = LD->getBasePtr(); 6957 const Value *SV = LD->getSrcValue(); 6958 int SVOffset = LD->getSrcValueOffset(); 6959 unsigned Alignment = LD->getAlignment(); 6960 bool isVolatile = LD->isVolatile(); 6961 6962 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6963 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8; 6964 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6965 DAG.getIntPtrConstant(IncrementSize)); 6966 SVOffset += IncrementSize; 6967 Alignment = MinAlign(Alignment, IncrementSize); 6968 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6969 6970 // Build a factor node to remember that this load is independent of the 6971 // other one. 6972 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6973 Hi.getValue(1)); 6974 6975 // Remember that we legalized the chain. 6976 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6977 break; 6978 } 6979 case ISD::BIT_CONVERT: { 6980 // We know the result is a vector. The input may be either a vector or a 6981 // scalar value. 6982 SDOperand InOp = Node->getOperand(0); 6983 if (!InOp.getValueType().isVector() || 6984 InOp.getValueType().getVectorNumElements() == 1) { 6985 // The input is a scalar or single-element vector. 6986 // Lower to a store/load so that it can be split. 6987 // FIXME: this could be improved probably. 6988 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6989 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val); 6990 6991 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6992 InOp, Ptr, 6993 PseudoSourceValue::getFixedStack(), 6994 FI->getIndex()); 6995 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 6996 PseudoSourceValue::getFixedStack(), 6997 FI->getIndex()); 6998 } 6999 // Split the vector and convert each of the pieces now. 7000 SplitVectorOp(InOp, Lo, Hi); 7001 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7002 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7003 break; 7004 } 7005 } 7006 7007 // Remember in a map if the values will be reused later. 7008 bool isNew = 7009 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7010 assert(isNew && "Value already split?!?"); 7011} 7012 7013 7014/// ScalarizeVectorOp - Given an operand of single-element vector type 7015/// (e.g. v1f32), convert it into the equivalent operation that returns a 7016/// scalar (e.g. f32) value. 7017SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 7018 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7019 SDNode *Node = Op.Val; 7020 MVT NewVT = Op.getValueType().getVectorElementType(); 7021 assert(Op.getValueType().getVectorNumElements() == 1); 7022 7023 // See if we already scalarized it. 7024 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 7025 if (I != ScalarizedNodes.end()) return I->second; 7026 7027 SDOperand Result; 7028 switch (Node->getOpcode()) { 7029 default: 7030#ifndef NDEBUG 7031 Node->dump(&DAG); cerr << "\n"; 7032#endif 7033 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7034 case ISD::ADD: 7035 case ISD::FADD: 7036 case ISD::SUB: 7037 case ISD::FSUB: 7038 case ISD::MUL: 7039 case ISD::FMUL: 7040 case ISD::SDIV: 7041 case ISD::UDIV: 7042 case ISD::FDIV: 7043 case ISD::SREM: 7044 case ISD::UREM: 7045 case ISD::FREM: 7046 case ISD::FPOW: 7047 case ISD::AND: 7048 case ISD::OR: 7049 case ISD::XOR: 7050 Result = DAG.getNode(Node->getOpcode(), 7051 NewVT, 7052 ScalarizeVectorOp(Node->getOperand(0)), 7053 ScalarizeVectorOp(Node->getOperand(1))); 7054 break; 7055 case ISD::FNEG: 7056 case ISD::FABS: 7057 case ISD::FSQRT: 7058 case ISD::FSIN: 7059 case ISD::FCOS: 7060 Result = DAG.getNode(Node->getOpcode(), 7061 NewVT, 7062 ScalarizeVectorOp(Node->getOperand(0))); 7063 break; 7064 case ISD::FPOWI: 7065 Result = DAG.getNode(Node->getOpcode(), 7066 NewVT, 7067 ScalarizeVectorOp(Node->getOperand(0)), 7068 Node->getOperand(1)); 7069 break; 7070 case ISD::LOAD: { 7071 LoadSDNode *LD = cast<LoadSDNode>(Node); 7072 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7073 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7074 7075 const Value *SV = LD->getSrcValue(); 7076 int SVOffset = LD->getSrcValueOffset(); 7077 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 7078 LD->isVolatile(), LD->getAlignment()); 7079 7080 // Remember that we legalized the chain. 7081 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7082 break; 7083 } 7084 case ISD::BUILD_VECTOR: 7085 Result = Node->getOperand(0); 7086 break; 7087 case ISD::INSERT_VECTOR_ELT: 7088 // Returning the inserted scalar element. 7089 Result = Node->getOperand(1); 7090 break; 7091 case ISD::CONCAT_VECTORS: 7092 assert(Node->getOperand(0).getValueType() == NewVT && 7093 "Concat of non-legal vectors not yet supported!"); 7094 Result = Node->getOperand(0); 7095 break; 7096 case ISD::VECTOR_SHUFFLE: { 7097 // Figure out if the scalar is the LHS or RHS and return it. 7098 SDOperand EltNum = Node->getOperand(2).getOperand(0); 7099 if (cast<ConstantSDNode>(EltNum)->getValue()) 7100 Result = ScalarizeVectorOp(Node->getOperand(1)); 7101 else 7102 Result = ScalarizeVectorOp(Node->getOperand(0)); 7103 break; 7104 } 7105 case ISD::EXTRACT_SUBVECTOR: 7106 Result = Node->getOperand(0); 7107 assert(Result.getValueType() == NewVT); 7108 break; 7109 case ISD::BIT_CONVERT: { 7110 SDOperand Op0 = Op.getOperand(0); 7111 if (Op0.getValueType().getVectorNumElements() == 1) 7112 Op0 = ScalarizeVectorOp(Op0); 7113 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7114 break; 7115 } 7116 case ISD::SELECT: 7117 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7118 ScalarizeVectorOp(Op.getOperand(1)), 7119 ScalarizeVectorOp(Op.getOperand(2))); 7120 break; 7121 case ISD::VSETCC: { 7122 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7123 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7124 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7125 Op.getOperand(2)); 7126 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7127 DAG.getConstant(-1ULL, NewVT), 7128 DAG.getConstant(0ULL, NewVT)); 7129 break; 7130 } 7131 } 7132 7133 if (TLI.isTypeLegal(NewVT)) 7134 Result = LegalizeOp(Result); 7135 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7136 assert(isNew && "Value already scalarized?"); 7137 return Result; 7138} 7139 7140 7141// SelectionDAG::Legalize - This is the entry point for the file. 7142// 7143void SelectionDAG::Legalize() { 7144 if (ViewLegalizeDAGs) viewGraph(); 7145 7146 /// run - This is the main entry point to this class. 7147 /// 7148 SelectionDAGLegalize(*this).LegalizeDAG(); 7149} 7150 7151