LegalizeDAG.cpp revision 61bbbabe3da27479cc9a3a36e49091a1141ba7a3
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetFrameInfo.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetMachine.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Support/MathExtras.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallVector.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include <map> 33using namespace llvm; 34 35#ifndef NDEBUG 36static cl::opt<bool> 37ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 38 cl::desc("Pop up a window to show dags before legalize")); 39#else 40static const bool ViewLegalizeDAGs = 0; 41#endif 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class VISIBILITY_HIDDEN SelectionDAGLegalize { 57 TargetLowering &TLI; 58 SelectionDAG &DAG; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDOperand LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDOperand, SDOperand> LegalizedNodes; 87 88 /// PromotedNodes - For nodes that are below legal width, and that have more 89 /// than one use, this map indicates what promoted value to use. This allows 90 /// us to avoid promoting the same thing more than once. 91 DenseMap<SDOperand, SDOperand> PromotedNodes; 92 93 /// ExpandedNodes - For nodes that need to be expanded this map indicates 94 /// which which operands are the expanded version of the input. This allows 95 /// us to avoid expanding the same node more than once. 96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 97 98 /// SplitNodes - For vector nodes that need to be split, this map indicates 99 /// which which operands are the split version of the input. This allows us 100 /// to avoid splitting the same node more than once. 101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 102 103 /// ScalarizedNodes - For nodes that need to be converted from vector types to 104 /// scalar types, this contains the mapping of ones we have already 105 /// processed to the result. 106 std::map<SDOperand, SDOperand> ScalarizedNodes; 107 108 void AddLegalizedOperand(SDOperand From, SDOperand To) { 109 LegalizedNodes.insert(std::make_pair(From, To)); 110 // If someone requests legalization of the new node, return itself. 111 if (From != To) 112 LegalizedNodes.insert(std::make_pair(To, To)); 113 } 114 void AddPromotedOperand(SDOperand From, SDOperand To) { 115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 116 assert(isNew && "Got into the map somehow?"); 117 // If someone requests legalization of the new node, return itself. 118 LegalizedNodes.insert(std::make_pair(To, To)); 119 } 120 121public: 122 123 SelectionDAGLegalize(SelectionDAG &DAG); 124 125 /// getTypeAction - Return how we should legalize values of this type, either 126 /// it is already legal or we need to expand it into multiple registers of 127 /// smaller integer type, or we need to promote it to a larger type. 128 LegalizeAction getTypeAction(MVT::ValueType VT) const { 129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 130 } 131 132 /// isTypeLegal - Return true if this type is legal on this target. 133 /// 134 bool isTypeLegal(MVT::ValueType VT) const { 135 return getTypeAction(VT) == Legal; 136 } 137 138 void LegalizeDAG(); 139 140private: 141 /// HandleOp - Legalize, Promote, or Expand the specified operand as 142 /// appropriate for its type. 143 void HandleOp(SDOperand Op); 144 145 /// LegalizeOp - We know that the specified value has a legal type. 146 /// Recursively ensure that the operands have legal types, then return the 147 /// result. 148 SDOperand LegalizeOp(SDOperand O); 149 150 /// PromoteOp - Given an operation that produces a value in an invalid type, 151 /// promote it to compute the value into a larger type. The produced value 152 /// will have the correct bits for the low portion of the register, but no 153 /// guarantee is made about the top bits: it may be zero, sign-extended, or 154 /// garbage. 155 SDOperand PromoteOp(SDOperand O); 156 157 /// ExpandOp - Expand the specified SDOperand into its two component pieces 158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 159 /// the LegalizeNodes map is filled in for any results that are not expanded, 160 /// the ExpandedNodes map is filled in for any results that are expanded, and 161 /// the Lo/Hi values are returned. This applies to integer types and Vector 162 /// types. 163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 164 165 /// SplitVectorOp - Given an operand of vector type, break it down into 166 /// two smaller values. 167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 168 169 /// ScalarizeVectorOp - Given an operand of single-element vector type 170 /// (e.g. v1f32), convert it into the equivalent operation that returns a 171 /// scalar (e.g. f32) value. 172 SDOperand ScalarizeVectorOp(SDOperand O); 173 174 /// isShuffleLegal - Return true if a vector shuffle is legal with the 175 /// specified mask and type. Targets can specify exactly which masks they 176 /// support and the code generator is tasked with not creating illegal masks. 177 /// 178 /// Note that this will also return true for shuffles that are promoted to a 179 /// different type. 180 /// 181 /// If this is a legal shuffle, this method returns the (possibly promoted) 182 /// build_vector Mask. If it's not a legal shuffle, it returns null. 183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 184 185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 187 188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 189 190 SDOperand CreateStackTemporary(MVT::ValueType VT); 191 192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 193 SDOperand &Hi); 194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 195 SDOperand Source); 196 197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 198 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 200 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 201 SDOperand LegalOp, 202 MVT::ValueType DestVT); 203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 204 bool isSigned); 205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 206 bool isSigned); 207 208 SDOperand ExpandBSWAP(SDOperand Op); 209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 211 SDOperand &Lo, SDOperand &Hi); 212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 213 SDOperand &Lo, SDOperand &Hi); 214 215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 217 218 SDOperand getIntPtrConstant(uint64_t Val) { 219 return DAG.getConstant(Val, TLI.getPointerTy()); 220 } 221}; 222} 223 224/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 225/// specified mask and type. Targets can specify exactly which masks they 226/// support and the code generator is tasked with not creating illegal masks. 227/// 228/// Note that this will also return true for shuffles that are promoted to a 229/// different type. 230SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 231 SDOperand Mask) const { 232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 233 default: return 0; 234 case TargetLowering::Legal: 235 case TargetLowering::Custom: 236 break; 237 case TargetLowering::Promote: { 238 // If this is promoted to a different type, convert the shuffle mask and 239 // ask if it is legal in the promoted type! 240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 241 242 // If we changed # elements, change the shuffle mask. 243 unsigned NumEltsGrowth = 244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 246 if (NumEltsGrowth > 1) { 247 // Renumber the elements. 248 SmallVector<SDOperand, 8> Ops; 249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 250 SDOperand InOp = Mask.getOperand(i); 251 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 252 if (InOp.getOpcode() == ISD::UNDEF) 253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 254 else { 255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 257 } 258 } 259 } 260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 261 } 262 VT = NVT; 263 break; 264 } 265 } 266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 267} 268 269SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 270 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 271 ValueTypeActions(TLI.getValueTypeActions()) { 272 assert(MVT::LAST_VALUETYPE <= 32 && 273 "Too many value types for ValueTypeActions to hold!"); 274} 275 276/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 277/// contains all of a nodes operands before it contains the node. 278static void ComputeTopDownOrdering(SelectionDAG &DAG, 279 SmallVector<SDNode*, 64> &Order) { 280 281 DenseMap<SDNode*, unsigned> Visited; 282 std::vector<SDNode*> Worklist; 283 Worklist.reserve(128); 284 285 // Compute ordering from all of the leaves in the graphs, those (like the 286 // entry node) that have no operands. 287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 288 E = DAG.allnodes_end(); I != E; ++I) { 289 if (I->getNumOperands() == 0) { 290 Visited[I] = 0 - 1U; 291 Worklist.push_back(I); 292 } 293 } 294 295 while (!Worklist.empty()) { 296 SDNode *N = Worklist.back(); 297 Worklist.pop_back(); 298 299 if (++Visited[N] != N->getNumOperands()) 300 continue; // Haven't visited all operands yet 301 302 Order.push_back(N); 303 304 // Now that we have N in, add anything that uses it if all of their operands 305 // are now done. 306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 307 UI != E; ++UI) 308 Worklist.push_back(*UI); 309 } 310 311 assert(Order.size() == Visited.size() && 312 Order.size() == 313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 314 "Error: DAG is cyclic!"); 315} 316 317 318void SelectionDAGLegalize::LegalizeDAG() { 319 LastCALLSEQ_END = DAG.getEntryNode(); 320 IsLegalizingCall = false; 321 322 // The legalize process is inherently a bottom-up recursive process (users 323 // legalize their uses before themselves). Given infinite stack space, we 324 // could just start legalizing on the root and traverse the whole graph. In 325 // practice however, this causes us to run out of stack space on large basic 326 // blocks. To avoid this problem, compute an ordering of the nodes where each 327 // node is only legalized after all of its operands are legalized. 328 SmallVector<SDNode*, 64> Order; 329 ComputeTopDownOrdering(DAG, Order); 330 331 for (unsigned i = 0, e = Order.size(); i != e; ++i) 332 HandleOp(SDOperand(Order[i], 0)); 333 334 // Finally, it's possible the root changed. Get the new root. 335 SDOperand OldRoot = DAG.getRoot(); 336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 337 DAG.setRoot(LegalizedNodes[OldRoot]); 338 339 ExpandedNodes.clear(); 340 LegalizedNodes.clear(); 341 PromotedNodes.clear(); 342 SplitNodes.clear(); 343 ScalarizedNodes.clear(); 344 345 // Remove dead nodes now. 346 DAG.RemoveDeadNodes(); 347} 348 349 350/// FindCallEndFromCallStart - Given a chained node that is part of a call 351/// sequence, find the CALLSEQ_END node that terminates the call sequence. 352static SDNode *FindCallEndFromCallStart(SDNode *Node) { 353 if (Node->getOpcode() == ISD::CALLSEQ_END) 354 return Node; 355 if (Node->use_empty()) 356 return 0; // No CallSeqEnd 357 358 // The chain is usually at the end. 359 SDOperand TheChain(Node, Node->getNumValues()-1); 360 if (TheChain.getValueType() != MVT::Other) { 361 // Sometimes it's at the beginning. 362 TheChain = SDOperand(Node, 0); 363 if (TheChain.getValueType() != MVT::Other) { 364 // Otherwise, hunt for it. 365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 366 if (Node->getValueType(i) == MVT::Other) { 367 TheChain = SDOperand(Node, i); 368 break; 369 } 370 371 // Otherwise, we walked into a node without a chain. 372 if (TheChain.getValueType() != MVT::Other) 373 return 0; 374 } 375 } 376 377 for (SDNode::use_iterator UI = Node->use_begin(), 378 E = Node->use_end(); UI != E; ++UI) { 379 380 // Make sure to only follow users of our token chain. 381 SDNode *User = *UI; 382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 383 if (User->getOperand(i) == TheChain) 384 if (SDNode *Result = FindCallEndFromCallStart(User)) 385 return Result; 386 } 387 return 0; 388} 389 390/// FindCallStartFromCallEnd - Given a chained node that is part of a call 391/// sequence, find the CALLSEQ_START node that initiates the call sequence. 392static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 393 assert(Node && "Didn't find callseq_start for a call??"); 394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 395 396 assert(Node->getOperand(0).getValueType() == MVT::Other && 397 "Node doesn't have a token chain argument!"); 398 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 399} 400 401/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 402/// see if any uses can reach Dest. If no dest operands can get to dest, 403/// legalize them, legalize ourself, and return false, otherwise, return true. 404/// 405/// Keep track of the nodes we fine that actually do lead to Dest in 406/// NodesLeadingTo. This avoids retraversing them exponential number of times. 407/// 408bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 410 if (N == Dest) return true; // N certainly leads to Dest :) 411 412 // If we've already processed this node and it does lead to Dest, there is no 413 // need to reprocess it. 414 if (NodesLeadingTo.count(N)) return true; 415 416 // If the first result of this node has been already legalized, then it cannot 417 // reach N. 418 switch (getTypeAction(N->getValueType(0))) { 419 case Legal: 420 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 421 break; 422 case Promote: 423 if (PromotedNodes.count(SDOperand(N, 0))) return false; 424 break; 425 case Expand: 426 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 } 429 430 // Okay, this node has not already been legalized. Check and legalize all 431 // operands. If none lead to Dest, then we can legalize this node. 432 bool OperandsLeadToDest = false; 433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 434 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 436 437 if (OperandsLeadToDest) { 438 NodesLeadingTo.insert(N); 439 return true; 440 } 441 442 // Okay, this node looks safe, legalize it and return false. 443 HandleOp(SDOperand(N, 0)); 444 return false; 445} 446 447/// HandleOp - Legalize, Promote, or Expand the specified operand as 448/// appropriate for its type. 449void SelectionDAGLegalize::HandleOp(SDOperand Op) { 450 MVT::ValueType VT = Op.getValueType(); 451 switch (getTypeAction(VT)) { 452 default: assert(0 && "Bad type action!"); 453 case Legal: (void)LegalizeOp(Op); break; 454 case Promote: (void)PromoteOp(Op); break; 455 case Expand: 456 if (!MVT::isVector(VT)) { 457 // If this is an illegal scalar, expand it into its two component 458 // pieces. 459 SDOperand X, Y; 460 ExpandOp(Op, X, Y); 461 } else if (MVT::getVectorNumElements(VT) == 1) { 462 // If this is an illegal single element vector, convert it to a 463 // scalar operation. 464 (void)ScalarizeVectorOp(Op); 465 } else { 466 // Otherwise, this is an illegal multiple element vector. 467 // Split it in half and legalize both parts. 468 SDOperand X, Y; 469 SplitVectorOp(Op, X, Y); 470 } 471 break; 472 } 473} 474 475/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 476/// a load from the constant pool. 477static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 478 SelectionDAG &DAG, TargetLowering &TLI) { 479 bool Extend = false; 480 481 // If a FP immediate is precise when represented as a float and if the 482 // target can do an extending load from float to double, we put it into 483 // the constant pool as a float, even if it's is statically typed as a 484 // double. 485 MVT::ValueType VT = CFP->getValueType(0); 486 bool isDouble = VT == MVT::f64; 487 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 488 Type::FloatTy, CFP->getValue()); 489 if (!UseCP) { 490 double Val = LLVMC->getValue(); 491 return isDouble 492 ? DAG.getConstant(DoubleToBits(Val), MVT::i64) 493 : DAG.getConstant(FloatToBits(Val), MVT::i32); 494 } 495 496 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 497 // Only do this if the target has a native EXTLOAD instruction from f32. 498 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 499 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 500 VT = MVT::f32; 501 Extend = true; 502 } 503 504 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 505 if (Extend) { 506 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 507 CPIdx, NULL, 0, MVT::f32); 508 } else { 509 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 510 } 511} 512 513 514/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 515/// operations. 516static 517SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 518 SelectionDAG &DAG, TargetLowering &TLI) { 519 MVT::ValueType VT = Node->getValueType(0); 520 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 521 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 522 "fcopysign expansion only supported for f32 and f64"); 523 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 524 525 // First get the sign bit of second operand. 526 SDOperand Mask1 = (SrcVT == MVT::f64) 527 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 528 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 529 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 530 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 531 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 532 // Shift right or sign-extend it if the two operands have different types. 533 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 534 if (SizeDiff > 0) { 535 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 536 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 537 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 538 } else if (SizeDiff < 0) 539 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 540 541 // Clear the sign bit of first operand. 542 SDOperand Mask2 = (VT == MVT::f64) 543 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 544 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 545 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 546 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 547 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 548 549 // Or the value with the sign bit. 550 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 551 return Result; 552} 553 554/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 555static 556SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 557 TargetLowering &TLI) { 558 assert(MVT::isInteger(ST->getStoredVT()) && 559 "Non integer unaligned stores not implemented."); 560 int SVOffset = ST->getSrcValueOffset(); 561 SDOperand Chain = ST->getChain(); 562 SDOperand Ptr = ST->getBasePtr(); 563 SDOperand Val = ST->getValue(); 564 MVT::ValueType VT = Val.getValueType(); 565 // Get the half-size VT 566 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 567 int NumBits = MVT::getSizeInBits(NewStoredVT); 568 int Alignment = ST->getAlignment(); 569 int IncrementSize = NumBits / 8; 570 571 // Divide the stored value in two parts. 572 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 573 SDOperand Lo = Val; 574 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 575 576 // Store the two parts 577 SDOperand Store1, Store2; 578 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 579 ST->getSrcValue(), SVOffset, NewStoredVT, 580 ST->isVolatile(), Alignment); 581 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 582 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 583 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 584 ST->getSrcValue(), SVOffset + IncrementSize, 585 NewStoredVT, ST->isVolatile(), Alignment); 586 587 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 588} 589 590/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 591static 592SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 593 TargetLowering &TLI) { 594 assert(MVT::isInteger(LD->getLoadedVT()) && 595 "Non integer unaligned loads not implemented."); 596 int SVOffset = LD->getSrcValueOffset(); 597 SDOperand Chain = LD->getChain(); 598 SDOperand Ptr = LD->getBasePtr(); 599 MVT::ValueType VT = LD->getValueType(0); 600 MVT::ValueType NewLoadedVT = LD->getLoadedVT() - 1; 601 int NumBits = MVT::getSizeInBits(NewLoadedVT); 602 int Alignment = LD->getAlignment(); 603 int IncrementSize = NumBits / 8; 604 ISD::LoadExtType HiExtType = LD->getExtensionType(); 605 606 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 607 if (HiExtType == ISD::NON_EXTLOAD) 608 HiExtType = ISD::ZEXTLOAD; 609 610 // Load the value in two parts 611 SDOperand Lo, Hi; 612 if (TLI.isLittleEndian()) { 613 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 614 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 615 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 616 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 617 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 618 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 619 Alignment); 620 } else { 621 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 622 NewLoadedVT,LD->isVolatile(), Alignment); 623 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 624 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 625 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 626 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 627 Alignment); 628 } 629 630 // aggregate the two parts 631 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 632 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 633 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 634 635 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 636 Hi.getValue(1)); 637 638 SDOperand Ops[] = { Result, TF }; 639 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 640} 641 642/// LegalizeOp - We know that the specified value has a legal type, and 643/// that its operands are legal. Now ensure that the operation itself 644/// is legal, recursively ensuring that the operands' operations remain 645/// legal. 646SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 647 assert(isTypeLegal(Op.getValueType()) && 648 "Caller should expand or promote operands that are not legal!"); 649 SDNode *Node = Op.Val; 650 651 // If this operation defines any values that cannot be represented in a 652 // register on this target, make sure to expand or promote them. 653 if (Node->getNumValues() > 1) { 654 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 655 if (getTypeAction(Node->getValueType(i)) != Legal) { 656 HandleOp(Op.getValue(i)); 657 assert(LegalizedNodes.count(Op) && 658 "Handling didn't add legal operands!"); 659 return LegalizedNodes[Op]; 660 } 661 } 662 663 // Note that LegalizeOp may be reentered even from single-use nodes, which 664 // means that we always must cache transformed nodes. 665 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 666 if (I != LegalizedNodes.end()) return I->second; 667 668 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 669 SDOperand Result = Op; 670 bool isCustom = false; 671 672 switch (Node->getOpcode()) { 673 case ISD::FrameIndex: 674 case ISD::EntryToken: 675 case ISD::Register: 676 case ISD::BasicBlock: 677 case ISD::TargetFrameIndex: 678 case ISD::TargetJumpTable: 679 case ISD::TargetConstant: 680 case ISD::TargetConstantFP: 681 case ISD::TargetConstantPool: 682 case ISD::TargetGlobalAddress: 683 case ISD::TargetGlobalTLSAddress: 684 case ISD::TargetExternalSymbol: 685 case ISD::VALUETYPE: 686 case ISD::SRCVALUE: 687 case ISD::STRING: 688 case ISD::CONDCODE: 689 // Primitives must all be legal. 690 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 691 "This must be legal!"); 692 break; 693 default: 694 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 695 // If this is a target node, legalize it by legalizing the operands then 696 // passing it through. 697 SmallVector<SDOperand, 8> Ops; 698 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 699 Ops.push_back(LegalizeOp(Node->getOperand(i))); 700 701 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 702 703 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 704 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 705 return Result.getValue(Op.ResNo); 706 } 707 // Otherwise this is an unhandled builtin node. splat. 708#ifndef NDEBUG 709 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 710#endif 711 assert(0 && "Do not know how to legalize this operator!"); 712 abort(); 713 case ISD::GLOBAL_OFFSET_TABLE: 714 case ISD::GlobalAddress: 715 case ISD::GlobalTLSAddress: 716 case ISD::ExternalSymbol: 717 case ISD::ConstantPool: 718 case ISD::JumpTable: // Nothing to do. 719 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 720 default: assert(0 && "This action is not supported yet!"); 721 case TargetLowering::Custom: 722 Tmp1 = TLI.LowerOperation(Op, DAG); 723 if (Tmp1.Val) Result = Tmp1; 724 // FALLTHROUGH if the target doesn't want to lower this op after all. 725 case TargetLowering::Legal: 726 break; 727 } 728 break; 729 case ISD::FRAMEADDR: 730 case ISD::RETURNADDR: 731 case ISD::FRAME_TO_ARGS_OFFSET: 732 // The only option for these nodes is to custom lower them. If the target 733 // does not custom lower them, then return zero. 734 Tmp1 = TLI.LowerOperation(Op, DAG); 735 if (Tmp1.Val) 736 Result = Tmp1; 737 else 738 Result = DAG.getConstant(0, TLI.getPointerTy()); 739 break; 740 case ISD::EXCEPTIONADDR: { 741 Tmp1 = LegalizeOp(Node->getOperand(0)); 742 MVT::ValueType VT = Node->getValueType(0); 743 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 744 default: assert(0 && "This action is not supported yet!"); 745 case TargetLowering::Expand: { 746 unsigned Reg = TLI.getExceptionAddressRegister(); 747 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); 748 } 749 break; 750 case TargetLowering::Custom: 751 Result = TLI.LowerOperation(Op, DAG); 752 if (Result.Val) break; 753 // Fall Thru 754 case TargetLowering::Legal: { 755 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 756 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 757 Ops, 2).getValue(Op.ResNo); 758 break; 759 } 760 } 761 } 762 break; 763 case ISD::EHSELECTION: { 764 Tmp1 = LegalizeOp(Node->getOperand(0)); 765 Tmp2 = LegalizeOp(Node->getOperand(1)); 766 MVT::ValueType VT = Node->getValueType(0); 767 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 768 default: assert(0 && "This action is not supported yet!"); 769 case TargetLowering::Expand: { 770 unsigned Reg = TLI.getExceptionSelectorRegister(); 771 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); 772 } 773 break; 774 case TargetLowering::Custom: 775 Result = TLI.LowerOperation(Op, DAG); 776 if (Result.Val) break; 777 // Fall Thru 778 case TargetLowering::Legal: { 779 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 780 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 781 Ops, 2).getValue(Op.ResNo); 782 break; 783 } 784 } 785 } 786 break; 787 case ISD::EH_RETURN: { 788 MVT::ValueType VT = Node->getValueType(0); 789 // The only "good" option for this node is to custom lower it. 790 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 791 default: assert(0 && "This action is not supported at all!"); 792 case TargetLowering::Custom: 793 Result = TLI.LowerOperation(Op, DAG); 794 if (Result.Val) break; 795 // Fall Thru 796 case TargetLowering::Legal: 797 // Target does not know, how to lower this, lower to noop 798 Result = LegalizeOp(Node->getOperand(0)); 799 break; 800 } 801 } 802 break; 803 case ISD::AssertSext: 804 case ISD::AssertZext: 805 Tmp1 = LegalizeOp(Node->getOperand(0)); 806 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 807 break; 808 case ISD::MERGE_VALUES: 809 // Legalize eliminates MERGE_VALUES nodes. 810 Result = Node->getOperand(Op.ResNo); 811 break; 812 case ISD::CopyFromReg: 813 Tmp1 = LegalizeOp(Node->getOperand(0)); 814 Result = Op.getValue(0); 815 if (Node->getNumValues() == 2) { 816 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 817 } else { 818 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 819 if (Node->getNumOperands() == 3) { 820 Tmp2 = LegalizeOp(Node->getOperand(2)); 821 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 822 } else { 823 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 824 } 825 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 826 } 827 // Since CopyFromReg produces two values, make sure to remember that we 828 // legalized both of them. 829 AddLegalizedOperand(Op.getValue(0), Result); 830 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 831 return Result.getValue(Op.ResNo); 832 case ISD::UNDEF: { 833 MVT::ValueType VT = Op.getValueType(); 834 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 835 default: assert(0 && "This action is not supported yet!"); 836 case TargetLowering::Expand: 837 if (MVT::isInteger(VT)) 838 Result = DAG.getConstant(0, VT); 839 else if (MVT::isFloatingPoint(VT)) 840 Result = DAG.getConstantFP(0, VT); 841 else 842 assert(0 && "Unknown value type!"); 843 break; 844 case TargetLowering::Legal: 845 break; 846 } 847 break; 848 } 849 850 case ISD::INTRINSIC_W_CHAIN: 851 case ISD::INTRINSIC_WO_CHAIN: 852 case ISD::INTRINSIC_VOID: { 853 SmallVector<SDOperand, 8> Ops; 854 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 855 Ops.push_back(LegalizeOp(Node->getOperand(i))); 856 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 857 858 // Allow the target to custom lower its intrinsics if it wants to. 859 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 860 TargetLowering::Custom) { 861 Tmp3 = TLI.LowerOperation(Result, DAG); 862 if (Tmp3.Val) Result = Tmp3; 863 } 864 865 if (Result.Val->getNumValues() == 1) break; 866 867 // Must have return value and chain result. 868 assert(Result.Val->getNumValues() == 2 && 869 "Cannot return more than two values!"); 870 871 // Since loads produce two values, make sure to remember that we 872 // legalized both of them. 873 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 874 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 875 return Result.getValue(Op.ResNo); 876 } 877 878 case ISD::LOCATION: 879 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 881 882 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 883 case TargetLowering::Promote: 884 default: assert(0 && "This action is not supported yet!"); 885 case TargetLowering::Expand: { 886 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 887 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 888 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 889 890 if (MMI && (useDEBUG_LOC || useLABEL)) { 891 const std::string &FName = 892 cast<StringSDNode>(Node->getOperand(3))->getValue(); 893 const std::string &DirName = 894 cast<StringSDNode>(Node->getOperand(4))->getValue(); 895 unsigned SrcFile = MMI->RecordSource(DirName, FName); 896 897 SmallVector<SDOperand, 8> Ops; 898 Ops.push_back(Tmp1); // chain 899 SDOperand LineOp = Node->getOperand(1); 900 SDOperand ColOp = Node->getOperand(2); 901 902 if (useDEBUG_LOC) { 903 Ops.push_back(LineOp); // line # 904 Ops.push_back(ColOp); // col # 905 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 906 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 907 } else { 908 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 909 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 910 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 911 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 912 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 913 } 914 } else { 915 Result = Tmp1; // chain 916 } 917 break; 918 } 919 case TargetLowering::Legal: 920 if (Tmp1 != Node->getOperand(0) || 921 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 922 SmallVector<SDOperand, 8> Ops; 923 Ops.push_back(Tmp1); 924 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 925 Ops.push_back(Node->getOperand(1)); // line # must be legal. 926 Ops.push_back(Node->getOperand(2)); // col # must be legal. 927 } else { 928 // Otherwise promote them. 929 Ops.push_back(PromoteOp(Node->getOperand(1))); 930 Ops.push_back(PromoteOp(Node->getOperand(2))); 931 } 932 Ops.push_back(Node->getOperand(3)); // filename must be legal. 933 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 934 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 935 } 936 break; 937 } 938 break; 939 940 case ISD::DEBUG_LOC: 941 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 942 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 943 default: assert(0 && "This action is not supported yet!"); 944 case TargetLowering::Legal: 945 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 946 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 947 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 948 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 949 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 950 break; 951 } 952 break; 953 954 case ISD::LABEL: 955 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 956 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 957 default: assert(0 && "This action is not supported yet!"); 958 case TargetLowering::Legal: 959 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 960 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 961 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 962 break; 963 case TargetLowering::Expand: 964 Result = LegalizeOp(Node->getOperand(0)); 965 break; 966 } 967 break; 968 969 case ISD::Constant: { 970 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 971 unsigned opAction = 972 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 973 974 // We know we don't need to expand constants here, constants only have one 975 // value and we check that it is fine above. 976 977 if (opAction == TargetLowering::Custom) { 978 Tmp1 = TLI.LowerOperation(Result, DAG); 979 if (Tmp1.Val) 980 Result = Tmp1; 981 } 982 break; 983 } 984 case ISD::ConstantFP: { 985 // Spill FP immediates to the constant pool if the target cannot directly 986 // codegen them. Targets often have some immediate values that can be 987 // efficiently generated into an FP register without a load. We explicitly 988 // leave these constants as ConstantFP nodes for the target to deal with. 989 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 990 991 // Check to see if this FP immediate is already legal. 992 bool isLegal = false; 993 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 994 E = TLI.legal_fpimm_end(); I != E; ++I) 995 if (CFP->isExactlyValue(*I)) { 996 isLegal = true; 997 break; 998 } 999 1000 // If this is a legal constant, turn it into a TargetConstantFP node. 1001 if (isLegal) { 1002 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 1003 break; 1004 } 1005 1006 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1007 default: assert(0 && "This action is not supported yet!"); 1008 case TargetLowering::Custom: 1009 Tmp3 = TLI.LowerOperation(Result, DAG); 1010 if (Tmp3.Val) { 1011 Result = Tmp3; 1012 break; 1013 } 1014 // FALLTHROUGH 1015 case TargetLowering::Expand: 1016 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1017 } 1018 break; 1019 } 1020 case ISD::TokenFactor: 1021 if (Node->getNumOperands() == 2) { 1022 Tmp1 = LegalizeOp(Node->getOperand(0)); 1023 Tmp2 = LegalizeOp(Node->getOperand(1)); 1024 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1025 } else if (Node->getNumOperands() == 3) { 1026 Tmp1 = LegalizeOp(Node->getOperand(0)); 1027 Tmp2 = LegalizeOp(Node->getOperand(1)); 1028 Tmp3 = LegalizeOp(Node->getOperand(2)); 1029 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1030 } else { 1031 SmallVector<SDOperand, 8> Ops; 1032 // Legalize the operands. 1033 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1034 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1035 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1036 } 1037 break; 1038 1039 case ISD::FORMAL_ARGUMENTS: 1040 case ISD::CALL: 1041 // The only option for this is to custom lower it. 1042 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1043 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1044 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 1045 "Lowering call/formal_arguments produced unexpected # results!"); 1046 1047 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1048 // remember that we legalized all of them, so it doesn't get relegalized. 1049 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1050 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1051 if (Op.ResNo == i) 1052 Tmp2 = Tmp1; 1053 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1054 } 1055 return Tmp2; 1056 case ISD::EXTRACT_SUBREG: { 1057 Tmp1 = LegalizeOp(Node->getOperand(0)); 1058 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1059 assert(idx && "Operand must be a constant"); 1060 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1062 } 1063 break; 1064 case ISD::INSERT_SUBREG: { 1065 Tmp1 = LegalizeOp(Node->getOperand(0)); 1066 Tmp2 = LegalizeOp(Node->getOperand(1)); 1067 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1068 assert(idx && "Operand must be a constant"); 1069 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1070 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1071 } 1072 break; 1073 case ISD::BUILD_VECTOR: 1074 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1075 default: assert(0 && "This action is not supported yet!"); 1076 case TargetLowering::Custom: 1077 Tmp3 = TLI.LowerOperation(Result, DAG); 1078 if (Tmp3.Val) { 1079 Result = Tmp3; 1080 break; 1081 } 1082 // FALLTHROUGH 1083 case TargetLowering::Expand: 1084 Result = ExpandBUILD_VECTOR(Result.Val); 1085 break; 1086 } 1087 break; 1088 case ISD::INSERT_VECTOR_ELT: 1089 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1090 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1091 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1092 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1093 1094 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1095 Node->getValueType(0))) { 1096 default: assert(0 && "This action is not supported yet!"); 1097 case TargetLowering::Legal: 1098 break; 1099 case TargetLowering::Custom: 1100 Tmp3 = TLI.LowerOperation(Result, DAG); 1101 if (Tmp3.Val) { 1102 Result = Tmp3; 1103 break; 1104 } 1105 // FALLTHROUGH 1106 case TargetLowering::Expand: { 1107 // If the insert index is a constant, codegen this as a scalar_to_vector, 1108 // then a shuffle that inserts it into the right position in the vector. 1109 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1110 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1111 Tmp1.getValueType(), Tmp2); 1112 1113 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1114 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1115 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1116 1117 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1118 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1119 // the RHS. 1120 SmallVector<SDOperand, 8> ShufOps; 1121 for (unsigned i = 0; i != NumElts; ++i) { 1122 if (i != InsertPos->getValue()) 1123 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1124 else 1125 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1126 } 1127 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1128 &ShufOps[0], ShufOps.size()); 1129 1130 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1131 Tmp1, ScVec, ShufMask); 1132 Result = LegalizeOp(Result); 1133 break; 1134 } 1135 1136 // If the target doesn't support this, we have to spill the input vector 1137 // to a temporary stack slot, update the element, then reload it. This is 1138 // badness. We could also load the value into a vector register (either 1139 // with a "move to register" or "extload into register" instruction, then 1140 // permute it into place, if the idx is a constant and if the idx is 1141 // supported by the target. 1142 MVT::ValueType VT = Tmp1.getValueType(); 1143 MVT::ValueType EltVT = Tmp2.getValueType(); 1144 MVT::ValueType IdxVT = Tmp3.getValueType(); 1145 MVT::ValueType PtrVT = TLI.getPointerTy(); 1146 SDOperand StackPtr = CreateStackTemporary(VT); 1147 // Store the vector. 1148 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1149 1150 // Truncate or zero extend offset to target pointer type. 1151 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1152 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1153 // Add the offset to the index. 1154 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1155 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1156 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1157 // Store the scalar value. 1158 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1159 // Load the updated vector. 1160 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1161 break; 1162 } 1163 } 1164 break; 1165 case ISD::SCALAR_TO_VECTOR: 1166 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1167 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1168 break; 1169 } 1170 1171 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1172 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1173 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1174 Node->getValueType(0))) { 1175 default: assert(0 && "This action is not supported yet!"); 1176 case TargetLowering::Legal: 1177 break; 1178 case TargetLowering::Custom: 1179 Tmp3 = TLI.LowerOperation(Result, DAG); 1180 if (Tmp3.Val) { 1181 Result = Tmp3; 1182 break; 1183 } 1184 // FALLTHROUGH 1185 case TargetLowering::Expand: 1186 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1187 break; 1188 } 1189 break; 1190 case ISD::VECTOR_SHUFFLE: 1191 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1192 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1193 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1194 1195 // Allow targets to custom lower the SHUFFLEs they support. 1196 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1197 default: assert(0 && "Unknown operation action!"); 1198 case TargetLowering::Legal: 1199 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1200 "vector shuffle should not be created if not legal!"); 1201 break; 1202 case TargetLowering::Custom: 1203 Tmp3 = TLI.LowerOperation(Result, DAG); 1204 if (Tmp3.Val) { 1205 Result = Tmp3; 1206 break; 1207 } 1208 // FALLTHROUGH 1209 case TargetLowering::Expand: { 1210 MVT::ValueType VT = Node->getValueType(0); 1211 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1212 MVT::ValueType PtrVT = TLI.getPointerTy(); 1213 SDOperand Mask = Node->getOperand(2); 1214 unsigned NumElems = Mask.getNumOperands(); 1215 SmallVector<SDOperand,8> Ops; 1216 for (unsigned i = 0; i != NumElems; ++i) { 1217 SDOperand Arg = Mask.getOperand(i); 1218 if (Arg.getOpcode() == ISD::UNDEF) { 1219 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1220 } else { 1221 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1222 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1223 if (Idx < NumElems) 1224 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1225 DAG.getConstant(Idx, PtrVT))); 1226 else 1227 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1228 DAG.getConstant(Idx - NumElems, PtrVT))); 1229 } 1230 } 1231 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1232 break; 1233 } 1234 case TargetLowering::Promote: { 1235 // Change base type to a different vector type. 1236 MVT::ValueType OVT = Node->getValueType(0); 1237 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1238 1239 // Cast the two input vectors. 1240 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1241 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1242 1243 // Convert the shuffle mask to the right # elements. 1244 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1245 assert(Tmp3.Val && "Shuffle not legal?"); 1246 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1247 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1248 break; 1249 } 1250 } 1251 break; 1252 1253 case ISD::EXTRACT_VECTOR_ELT: 1254 Tmp1 = Node->getOperand(0); 1255 Tmp2 = LegalizeOp(Node->getOperand(1)); 1256 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1257 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1258 break; 1259 1260 case ISD::EXTRACT_SUBVECTOR: 1261 Tmp1 = Node->getOperand(0); 1262 Tmp2 = LegalizeOp(Node->getOperand(1)); 1263 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1264 Result = ExpandEXTRACT_SUBVECTOR(Result); 1265 break; 1266 1267 case ISD::CALLSEQ_START: { 1268 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1269 1270 // Recursively Legalize all of the inputs of the call end that do not lead 1271 // to this call start. This ensures that any libcalls that need be inserted 1272 // are inserted *before* the CALLSEQ_START. 1273 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1274 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1275 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1276 NodesLeadingTo); 1277 } 1278 1279 // Now that we legalized all of the inputs (which may have inserted 1280 // libcalls) create the new CALLSEQ_START node. 1281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1282 1283 // Merge in the last call, to ensure that this call start after the last 1284 // call ended. 1285 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1286 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1287 Tmp1 = LegalizeOp(Tmp1); 1288 } 1289 1290 // Do not try to legalize the target-specific arguments (#1+). 1291 if (Tmp1 != Node->getOperand(0)) { 1292 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1293 Ops[0] = Tmp1; 1294 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1295 } 1296 1297 // Remember that the CALLSEQ_START is legalized. 1298 AddLegalizedOperand(Op.getValue(0), Result); 1299 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1300 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1301 1302 // Now that the callseq_start and all of the non-call nodes above this call 1303 // sequence have been legalized, legalize the call itself. During this 1304 // process, no libcalls can/will be inserted, guaranteeing that no calls 1305 // can overlap. 1306 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1307 SDOperand InCallSEQ = LastCALLSEQ_END; 1308 // Note that we are selecting this call! 1309 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1310 IsLegalizingCall = true; 1311 1312 // Legalize the call, starting from the CALLSEQ_END. 1313 LegalizeOp(LastCALLSEQ_END); 1314 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1315 return Result; 1316 } 1317 case ISD::CALLSEQ_END: 1318 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1319 // will cause this node to be legalized as well as handling libcalls right. 1320 if (LastCALLSEQ_END.Val != Node) { 1321 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1322 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1323 assert(I != LegalizedNodes.end() && 1324 "Legalizing the call start should have legalized this node!"); 1325 return I->second; 1326 } 1327 1328 // Otherwise, the call start has been legalized and everything is going 1329 // according to plan. Just legalize ourselves normally here. 1330 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1331 // Do not try to legalize the target-specific arguments (#1+), except for 1332 // an optional flag input. 1333 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1334 if (Tmp1 != Node->getOperand(0)) { 1335 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1336 Ops[0] = Tmp1; 1337 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1338 } 1339 } else { 1340 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1341 if (Tmp1 != Node->getOperand(0) || 1342 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1343 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1344 Ops[0] = Tmp1; 1345 Ops.back() = Tmp2; 1346 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1347 } 1348 } 1349 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1350 // This finishes up call legalization. 1351 IsLegalizingCall = false; 1352 1353 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1354 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1355 if (Node->getNumValues() == 2) 1356 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1357 return Result.getValue(Op.ResNo); 1358 case ISD::DYNAMIC_STACKALLOC: { 1359 MVT::ValueType VT = Node->getValueType(0); 1360 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1361 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1362 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1363 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1364 1365 Tmp1 = Result.getValue(0); 1366 Tmp2 = Result.getValue(1); 1367 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1368 default: assert(0 && "This action is not supported yet!"); 1369 case TargetLowering::Expand: { 1370 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1371 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1372 " not tell us which reg is the stack pointer!"); 1373 SDOperand Chain = Tmp1.getOperand(0); 1374 SDOperand Size = Tmp2.getOperand(1); 1375 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1376 Chain = SP.getValue(1); 1377 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1378 unsigned StackAlign = 1379 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1380 if (Align > StackAlign) 1381 SP = DAG.getNode(ISD::AND, VT, SP, DAG.getConstant(-Align, VT)); 1382 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1383 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1384 Tmp1 = LegalizeOp(Tmp1); 1385 Tmp2 = LegalizeOp(Tmp2); 1386 break; 1387 } 1388 case TargetLowering::Custom: 1389 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1390 if (Tmp3.Val) { 1391 Tmp1 = LegalizeOp(Tmp3); 1392 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1393 } 1394 break; 1395 case TargetLowering::Legal: 1396 break; 1397 } 1398 // Since this op produce two values, make sure to remember that we 1399 // legalized both of them. 1400 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1401 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1402 return Op.ResNo ? Tmp2 : Tmp1; 1403 } 1404 case ISD::INLINEASM: { 1405 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1406 bool Changed = false; 1407 // Legalize all of the operands of the inline asm, in case they are nodes 1408 // that need to be expanded or something. Note we skip the asm string and 1409 // all of the TargetConstant flags. 1410 SDOperand Op = LegalizeOp(Ops[0]); 1411 Changed = Op != Ops[0]; 1412 Ops[0] = Op; 1413 1414 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1415 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1416 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1417 for (++i; NumVals; ++i, --NumVals) { 1418 SDOperand Op = LegalizeOp(Ops[i]); 1419 if (Op != Ops[i]) { 1420 Changed = true; 1421 Ops[i] = Op; 1422 } 1423 } 1424 } 1425 1426 if (HasInFlag) { 1427 Op = LegalizeOp(Ops.back()); 1428 Changed |= Op != Ops.back(); 1429 Ops.back() = Op; 1430 } 1431 1432 if (Changed) 1433 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1434 1435 // INLINE asm returns a chain and flag, make sure to add both to the map. 1436 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1437 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1438 return Result.getValue(Op.ResNo); 1439 } 1440 case ISD::BR: 1441 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1442 // Ensure that libcalls are emitted before a branch. 1443 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1444 Tmp1 = LegalizeOp(Tmp1); 1445 LastCALLSEQ_END = DAG.getEntryNode(); 1446 1447 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1448 break; 1449 case ISD::BRIND: 1450 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1451 // Ensure that libcalls are emitted before a branch. 1452 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1453 Tmp1 = LegalizeOp(Tmp1); 1454 LastCALLSEQ_END = DAG.getEntryNode(); 1455 1456 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1457 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1458 case Legal: 1459 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1460 break; 1461 } 1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1463 break; 1464 case ISD::BR_JT: 1465 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1466 // Ensure that libcalls are emitted before a branch. 1467 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1468 Tmp1 = LegalizeOp(Tmp1); 1469 LastCALLSEQ_END = DAG.getEntryNode(); 1470 1471 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1472 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1473 1474 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1475 default: assert(0 && "This action is not supported yet!"); 1476 case TargetLowering::Legal: break; 1477 case TargetLowering::Custom: 1478 Tmp1 = TLI.LowerOperation(Result, DAG); 1479 if (Tmp1.Val) Result = Tmp1; 1480 break; 1481 case TargetLowering::Expand: { 1482 SDOperand Chain = Result.getOperand(0); 1483 SDOperand Table = Result.getOperand(1); 1484 SDOperand Index = Result.getOperand(2); 1485 1486 MVT::ValueType PTy = TLI.getPointerTy(); 1487 MachineFunction &MF = DAG.getMachineFunction(); 1488 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1489 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1490 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1491 1492 SDOperand LD; 1493 switch (EntrySize) { 1494 default: assert(0 && "Size of jump table not supported yet."); break; 1495 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1496 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1497 } 1498 1499 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1500 // For PIC, the sequence is: 1501 // BRIND(load(Jumptable + index) + RelocBase) 1502 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1503 SDOperand Reloc; 1504 if (TLI.usesGlobalOffsetTable()) 1505 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1506 else 1507 Reloc = Table; 1508 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1509 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1510 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1511 } else { 1512 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1513 } 1514 } 1515 } 1516 break; 1517 case ISD::BRCOND: 1518 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1519 // Ensure that libcalls are emitted before a return. 1520 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1521 Tmp1 = LegalizeOp(Tmp1); 1522 LastCALLSEQ_END = DAG.getEntryNode(); 1523 1524 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1525 case Expand: assert(0 && "It's impossible to expand bools"); 1526 case Legal: 1527 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1528 break; 1529 case Promote: 1530 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1531 1532 // The top bits of the promoted condition are not necessarily zero, ensure 1533 // that the value is properly zero extended. 1534 if (!DAG.MaskedValueIsZero(Tmp2, 1535 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1536 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1537 break; 1538 } 1539 1540 // Basic block destination (Op#2) is always legal. 1541 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1542 1543 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1544 default: assert(0 && "This action is not supported yet!"); 1545 case TargetLowering::Legal: break; 1546 case TargetLowering::Custom: 1547 Tmp1 = TLI.LowerOperation(Result, DAG); 1548 if (Tmp1.Val) Result = Tmp1; 1549 break; 1550 case TargetLowering::Expand: 1551 // Expand brcond's setcc into its constituent parts and create a BR_CC 1552 // Node. 1553 if (Tmp2.getOpcode() == ISD::SETCC) { 1554 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1555 Tmp2.getOperand(0), Tmp2.getOperand(1), 1556 Node->getOperand(2)); 1557 } else { 1558 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1559 DAG.getCondCode(ISD::SETNE), Tmp2, 1560 DAG.getConstant(0, Tmp2.getValueType()), 1561 Node->getOperand(2)); 1562 } 1563 break; 1564 } 1565 break; 1566 case ISD::BR_CC: 1567 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1568 // Ensure that libcalls are emitted before a branch. 1569 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1570 Tmp1 = LegalizeOp(Tmp1); 1571 Tmp2 = Node->getOperand(2); // LHS 1572 Tmp3 = Node->getOperand(3); // RHS 1573 Tmp4 = Node->getOperand(1); // CC 1574 1575 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1576 LastCALLSEQ_END = DAG.getEntryNode(); 1577 1578 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1579 // the LHS is a legal SETCC itself. In this case, we need to compare 1580 // the result against zero to select between true and false values. 1581 if (Tmp3.Val == 0) { 1582 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1583 Tmp4 = DAG.getCondCode(ISD::SETNE); 1584 } 1585 1586 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1587 Node->getOperand(4)); 1588 1589 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1590 default: assert(0 && "Unexpected action for BR_CC!"); 1591 case TargetLowering::Legal: break; 1592 case TargetLowering::Custom: 1593 Tmp4 = TLI.LowerOperation(Result, DAG); 1594 if (Tmp4.Val) Result = Tmp4; 1595 break; 1596 } 1597 break; 1598 case ISD::LOAD: { 1599 LoadSDNode *LD = cast<LoadSDNode>(Node); 1600 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1601 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1602 1603 ISD::LoadExtType ExtType = LD->getExtensionType(); 1604 if (ExtType == ISD::NON_EXTLOAD) { 1605 MVT::ValueType VT = Node->getValueType(0); 1606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1607 Tmp3 = Result.getValue(0); 1608 Tmp4 = Result.getValue(1); 1609 1610 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1611 default: assert(0 && "This action is not supported yet!"); 1612 case TargetLowering::Legal: 1613 // If this is an unaligned load and the target doesn't support it, 1614 // expand it. 1615 if (!TLI.allowsUnalignedMemoryAccesses()) { 1616 unsigned ABIAlignment = TLI.getTargetData()-> 1617 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1618 if (LD->getAlignment() < ABIAlignment){ 1619 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1620 TLI); 1621 Tmp3 = Result.getOperand(0); 1622 Tmp4 = Result.getOperand(1); 1623 LegalizeOp(Tmp3); 1624 LegalizeOp(Tmp4); 1625 } 1626 } 1627 break; 1628 case TargetLowering::Custom: 1629 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1630 if (Tmp1.Val) { 1631 Tmp3 = LegalizeOp(Tmp1); 1632 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1633 } 1634 break; 1635 case TargetLowering::Promote: { 1636 // Only promote a load of vector type to another. 1637 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1638 // Change base type to a different vector type. 1639 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1640 1641 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1642 LD->getSrcValueOffset(), 1643 LD->isVolatile(), LD->getAlignment()); 1644 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1645 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1646 break; 1647 } 1648 } 1649 // Since loads produce two values, make sure to remember that we 1650 // legalized both of them. 1651 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1652 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1653 return Op.ResNo ? Tmp4 : Tmp3; 1654 } else { 1655 MVT::ValueType SrcVT = LD->getLoadedVT(); 1656 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1657 default: assert(0 && "This action is not supported yet!"); 1658 case TargetLowering::Promote: 1659 assert(SrcVT == MVT::i1 && 1660 "Can only promote extending LOAD from i1 -> i8!"); 1661 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1662 LD->getSrcValue(), LD->getSrcValueOffset(), 1663 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1664 Tmp1 = Result.getValue(0); 1665 Tmp2 = Result.getValue(1); 1666 break; 1667 case TargetLowering::Custom: 1668 isCustom = true; 1669 // FALLTHROUGH 1670 case TargetLowering::Legal: 1671 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1672 Tmp1 = Result.getValue(0); 1673 Tmp2 = Result.getValue(1); 1674 1675 if (isCustom) { 1676 Tmp3 = TLI.LowerOperation(Result, DAG); 1677 if (Tmp3.Val) { 1678 Tmp1 = LegalizeOp(Tmp3); 1679 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1680 } 1681 } else { 1682 // If this is an unaligned load and the target doesn't support it, 1683 // expand it. 1684 if (!TLI.allowsUnalignedMemoryAccesses()) { 1685 unsigned ABIAlignment = TLI.getTargetData()-> 1686 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1687 if (LD->getAlignment() < ABIAlignment){ 1688 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1689 TLI); 1690 Tmp1 = Result.getOperand(0); 1691 Tmp2 = Result.getOperand(1); 1692 LegalizeOp(Tmp1); 1693 LegalizeOp(Tmp2); 1694 } 1695 } 1696 } 1697 break; 1698 case TargetLowering::Expand: 1699 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1700 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1701 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1702 LD->getSrcValueOffset(), 1703 LD->isVolatile(), LD->getAlignment()); 1704 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1705 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1706 Tmp2 = LegalizeOp(Load.getValue(1)); 1707 break; 1708 } 1709 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1710 // Turn the unsupported load into an EXTLOAD followed by an explicit 1711 // zero/sign extend inreg. 1712 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1713 Tmp1, Tmp2, LD->getSrcValue(), 1714 LD->getSrcValueOffset(), SrcVT, 1715 LD->isVolatile(), LD->getAlignment()); 1716 SDOperand ValRes; 1717 if (ExtType == ISD::SEXTLOAD) 1718 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1719 Result, DAG.getValueType(SrcVT)); 1720 else 1721 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1722 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1723 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1724 break; 1725 } 1726 // Since loads produce two values, make sure to remember that we legalized 1727 // both of them. 1728 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1729 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1730 return Op.ResNo ? Tmp2 : Tmp1; 1731 } 1732 } 1733 case ISD::EXTRACT_ELEMENT: { 1734 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1735 switch (getTypeAction(OpTy)) { 1736 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1737 case Legal: 1738 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1739 // 1 -> Hi 1740 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1741 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1742 TLI.getShiftAmountTy())); 1743 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1744 } else { 1745 // 0 -> Lo 1746 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1747 Node->getOperand(0)); 1748 } 1749 break; 1750 case Expand: 1751 // Get both the low and high parts. 1752 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1753 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1754 Result = Tmp2; // 1 -> Hi 1755 else 1756 Result = Tmp1; // 0 -> Lo 1757 break; 1758 } 1759 break; 1760 } 1761 1762 case ISD::CopyToReg: 1763 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1764 1765 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1766 "Register type must be legal!"); 1767 // Legalize the incoming value (must be a legal type). 1768 Tmp2 = LegalizeOp(Node->getOperand(2)); 1769 if (Node->getNumValues() == 1) { 1770 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1771 } else { 1772 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1773 if (Node->getNumOperands() == 4) { 1774 Tmp3 = LegalizeOp(Node->getOperand(3)); 1775 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1776 Tmp3); 1777 } else { 1778 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1779 } 1780 1781 // Since this produces two values, make sure to remember that we legalized 1782 // both of them. 1783 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1784 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1785 return Result; 1786 } 1787 break; 1788 1789 case ISD::RET: 1790 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1791 1792 // Ensure that libcalls are emitted before a return. 1793 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1794 Tmp1 = LegalizeOp(Tmp1); 1795 LastCALLSEQ_END = DAG.getEntryNode(); 1796 1797 switch (Node->getNumOperands()) { 1798 case 3: // ret val 1799 Tmp2 = Node->getOperand(1); 1800 Tmp3 = Node->getOperand(2); // Signness 1801 switch (getTypeAction(Tmp2.getValueType())) { 1802 case Legal: 1803 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1804 break; 1805 case Expand: 1806 if (!MVT::isVector(Tmp2.getValueType())) { 1807 SDOperand Lo, Hi; 1808 ExpandOp(Tmp2, Lo, Hi); 1809 1810 // Big endian systems want the hi reg first. 1811 if (!TLI.isLittleEndian()) 1812 std::swap(Lo, Hi); 1813 1814 if (Hi.Val) 1815 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1816 else 1817 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1818 Result = LegalizeOp(Result); 1819 } else { 1820 SDNode *InVal = Tmp2.Val; 1821 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 1822 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 1823 1824 // Figure out if there is a simple type corresponding to this Vector 1825 // type. If so, convert to the vector type. 1826 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1827 if (TLI.isTypeLegal(TVT)) { 1828 // Turn this into a return of the vector type. 1829 Tmp2 = LegalizeOp(Tmp2); 1830 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1831 } else if (NumElems == 1) { 1832 // Turn this into a return of the scalar type. 1833 Tmp2 = ScalarizeVectorOp(Tmp2); 1834 Tmp2 = LegalizeOp(Tmp2); 1835 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1836 1837 // FIXME: Returns of gcc generic vectors smaller than a legal type 1838 // should be returned in integer registers! 1839 1840 // The scalarized value type may not be legal, e.g. it might require 1841 // promotion or expansion. Relegalize the return. 1842 Result = LegalizeOp(Result); 1843 } else { 1844 // FIXME: Returns of gcc generic vectors larger than a legal vector 1845 // type should be returned by reference! 1846 SDOperand Lo, Hi; 1847 SplitVectorOp(Tmp2, Lo, Hi); 1848 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1849 Result = LegalizeOp(Result); 1850 } 1851 } 1852 break; 1853 case Promote: 1854 Tmp2 = PromoteOp(Node->getOperand(1)); 1855 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1856 Result = LegalizeOp(Result); 1857 break; 1858 } 1859 break; 1860 case 1: // ret void 1861 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1862 break; 1863 default: { // ret <values> 1864 SmallVector<SDOperand, 8> NewValues; 1865 NewValues.push_back(Tmp1); 1866 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1867 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1868 case Legal: 1869 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1870 NewValues.push_back(Node->getOperand(i+1)); 1871 break; 1872 case Expand: { 1873 SDOperand Lo, Hi; 1874 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 1875 "FIXME: TODO: implement returning non-legal vector types!"); 1876 ExpandOp(Node->getOperand(i), Lo, Hi); 1877 NewValues.push_back(Lo); 1878 NewValues.push_back(Node->getOperand(i+1)); 1879 if (Hi.Val) { 1880 NewValues.push_back(Hi); 1881 NewValues.push_back(Node->getOperand(i+1)); 1882 } 1883 break; 1884 } 1885 case Promote: 1886 assert(0 && "Can't promote multiple return value yet!"); 1887 } 1888 1889 if (NewValues.size() == Node->getNumOperands()) 1890 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1891 else 1892 Result = DAG.getNode(ISD::RET, MVT::Other, 1893 &NewValues[0], NewValues.size()); 1894 break; 1895 } 1896 } 1897 1898 if (Result.getOpcode() == ISD::RET) { 1899 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1900 default: assert(0 && "This action is not supported yet!"); 1901 case TargetLowering::Legal: break; 1902 case TargetLowering::Custom: 1903 Tmp1 = TLI.LowerOperation(Result, DAG); 1904 if (Tmp1.Val) Result = Tmp1; 1905 break; 1906 } 1907 } 1908 break; 1909 case ISD::STORE: { 1910 StoreSDNode *ST = cast<StoreSDNode>(Node); 1911 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1912 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1913 int SVOffset = ST->getSrcValueOffset(); 1914 unsigned Alignment = ST->getAlignment(); 1915 bool isVolatile = ST->isVolatile(); 1916 1917 if (!ST->isTruncatingStore()) { 1918 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1919 // FIXME: We shouldn't do this for TargetConstantFP's. 1920 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1921 // to phase ordering between legalized code and the dag combiner. This 1922 // probably means that we need to integrate dag combiner and legalizer 1923 // together. 1924 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1925 if (CFP->getValueType(0) == MVT::f32) { 1926 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1927 } else { 1928 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1929 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1930 } 1931 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1932 SVOffset, isVolatile, Alignment); 1933 break; 1934 } 1935 1936 switch (getTypeAction(ST->getStoredVT())) { 1937 case Legal: { 1938 Tmp3 = LegalizeOp(ST->getValue()); 1939 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1940 ST->getOffset()); 1941 1942 MVT::ValueType VT = Tmp3.getValueType(); 1943 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1944 default: assert(0 && "This action is not supported yet!"); 1945 case TargetLowering::Legal: 1946 // If this is an unaligned store and the target doesn't support it, 1947 // expand it. 1948 if (!TLI.allowsUnalignedMemoryAccesses()) { 1949 unsigned ABIAlignment = TLI.getTargetData()-> 1950 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 1951 if (ST->getAlignment() < ABIAlignment) 1952 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 1953 TLI); 1954 } 1955 break; 1956 case TargetLowering::Custom: 1957 Tmp1 = TLI.LowerOperation(Result, DAG); 1958 if (Tmp1.Val) Result = Tmp1; 1959 break; 1960 case TargetLowering::Promote: 1961 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1962 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1963 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1964 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 1965 ST->getSrcValue(), SVOffset, isVolatile, 1966 Alignment); 1967 break; 1968 } 1969 break; 1970 } 1971 case Promote: 1972 // Truncate the value and store the result. 1973 Tmp3 = PromoteOp(ST->getValue()); 1974 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1975 SVOffset, ST->getStoredVT(), 1976 isVolatile, Alignment); 1977 break; 1978 1979 case Expand: 1980 unsigned IncrementSize = 0; 1981 SDOperand Lo, Hi; 1982 1983 // If this is a vector type, then we have to calculate the increment as 1984 // the product of the element size in bytes, and the number of elements 1985 // in the high half of the vector. 1986 if (MVT::isVector(ST->getValue().getValueType())) { 1987 SDNode *InVal = ST->getValue().Val; 1988 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 1989 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 1990 1991 // Figure out if there is a simple type corresponding to this Vector 1992 // type. If so, convert to the vector type. 1993 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1994 if (TLI.isTypeLegal(TVT)) { 1995 // Turn this into a normal store of the vector type. 1996 Tmp3 = LegalizeOp(Node->getOperand(1)); 1997 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1998 SVOffset, isVolatile, Alignment); 1999 Result = LegalizeOp(Result); 2000 break; 2001 } else if (NumElems == 1) { 2002 // Turn this into a normal store of the scalar type. 2003 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2004 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2005 SVOffset, isVolatile, Alignment); 2006 // The scalarized value type may not be legal, e.g. it might require 2007 // promotion or expansion. Relegalize the scalar store. 2008 Result = LegalizeOp(Result); 2009 break; 2010 } else { 2011 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2012 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 2013 } 2014 } else { 2015 ExpandOp(Node->getOperand(1), Lo, Hi); 2016 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2017 2018 if (!TLI.isLittleEndian()) 2019 std::swap(Lo, Hi); 2020 } 2021 2022 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2023 SVOffset, isVolatile, Alignment); 2024 2025 if (Hi.Val == NULL) { 2026 // Must be int <-> float one-to-one expansion. 2027 Result = Lo; 2028 break; 2029 } 2030 2031 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2032 getIntPtrConstant(IncrementSize)); 2033 assert(isTypeLegal(Tmp2.getValueType()) && 2034 "Pointers must be legal!"); 2035 SVOffset += IncrementSize; 2036 if (Alignment > IncrementSize) 2037 Alignment = IncrementSize; 2038 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2039 SVOffset, isVolatile, Alignment); 2040 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2041 break; 2042 } 2043 } else { 2044 // Truncating store 2045 assert(isTypeLegal(ST->getValue().getValueType()) && 2046 "Cannot handle illegal TRUNCSTORE yet!"); 2047 Tmp3 = LegalizeOp(ST->getValue()); 2048 2049 // The only promote case we handle is TRUNCSTORE:i1 X into 2050 // -> TRUNCSTORE:i8 (and X, 1) 2051 if (ST->getStoredVT() == MVT::i1 && 2052 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2053 // Promote the bool to a mask then store. 2054 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2055 DAG.getConstant(1, Tmp3.getValueType())); 2056 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2057 SVOffset, MVT::i8, 2058 isVolatile, Alignment); 2059 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2060 Tmp2 != ST->getBasePtr()) { 2061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2062 ST->getOffset()); 2063 } 2064 2065 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2066 switch (TLI.getStoreXAction(StVT)) { 2067 default: assert(0 && "This action is not supported yet!"); 2068 case TargetLowering::Legal: 2069 // If this is an unaligned store and the target doesn't support it, 2070 // expand it. 2071 if (!TLI.allowsUnalignedMemoryAccesses()) { 2072 unsigned ABIAlignment = TLI.getTargetData()-> 2073 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2074 if (ST->getAlignment() < ABIAlignment) 2075 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2076 TLI); 2077 } 2078 break; 2079 case TargetLowering::Custom: 2080 Tmp1 = TLI.LowerOperation(Result, DAG); 2081 if (Tmp1.Val) Result = Tmp1; 2082 break; 2083 } 2084 } 2085 break; 2086 } 2087 case ISD::PCMARKER: 2088 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2089 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2090 break; 2091 case ISD::STACKSAVE: 2092 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2093 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2094 Tmp1 = Result.getValue(0); 2095 Tmp2 = Result.getValue(1); 2096 2097 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2098 default: assert(0 && "This action is not supported yet!"); 2099 case TargetLowering::Legal: break; 2100 case TargetLowering::Custom: 2101 Tmp3 = TLI.LowerOperation(Result, DAG); 2102 if (Tmp3.Val) { 2103 Tmp1 = LegalizeOp(Tmp3); 2104 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2105 } 2106 break; 2107 case TargetLowering::Expand: 2108 // Expand to CopyFromReg if the target set 2109 // StackPointerRegisterToSaveRestore. 2110 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2111 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2112 Node->getValueType(0)); 2113 Tmp2 = Tmp1.getValue(1); 2114 } else { 2115 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2116 Tmp2 = Node->getOperand(0); 2117 } 2118 break; 2119 } 2120 2121 // Since stacksave produce two values, make sure to remember that we 2122 // legalized both of them. 2123 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2124 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2125 return Op.ResNo ? Tmp2 : Tmp1; 2126 2127 case ISD::STACKRESTORE: 2128 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2129 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2130 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2131 2132 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2133 default: assert(0 && "This action is not supported yet!"); 2134 case TargetLowering::Legal: break; 2135 case TargetLowering::Custom: 2136 Tmp1 = TLI.LowerOperation(Result, DAG); 2137 if (Tmp1.Val) Result = Tmp1; 2138 break; 2139 case TargetLowering::Expand: 2140 // Expand to CopyToReg if the target set 2141 // StackPointerRegisterToSaveRestore. 2142 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2143 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2144 } else { 2145 Result = Tmp1; 2146 } 2147 break; 2148 } 2149 break; 2150 2151 case ISD::READCYCLECOUNTER: 2152 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2153 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2154 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2155 Node->getValueType(0))) { 2156 default: assert(0 && "This action is not supported yet!"); 2157 case TargetLowering::Legal: 2158 Tmp1 = Result.getValue(0); 2159 Tmp2 = Result.getValue(1); 2160 break; 2161 case TargetLowering::Custom: 2162 Result = TLI.LowerOperation(Result, DAG); 2163 Tmp1 = LegalizeOp(Result.getValue(0)); 2164 Tmp2 = LegalizeOp(Result.getValue(1)); 2165 break; 2166 } 2167 2168 // Since rdcc produce two values, make sure to remember that we legalized 2169 // both of them. 2170 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2171 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2172 return Result; 2173 2174 case ISD::SELECT: 2175 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2176 case Expand: assert(0 && "It's impossible to expand bools"); 2177 case Legal: 2178 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2179 break; 2180 case Promote: 2181 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2182 // Make sure the condition is either zero or one. 2183 if (!DAG.MaskedValueIsZero(Tmp1, 2184 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2185 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2186 break; 2187 } 2188 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2189 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2190 2191 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2192 2193 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2194 default: assert(0 && "This action is not supported yet!"); 2195 case TargetLowering::Legal: break; 2196 case TargetLowering::Custom: { 2197 Tmp1 = TLI.LowerOperation(Result, DAG); 2198 if (Tmp1.Val) Result = Tmp1; 2199 break; 2200 } 2201 case TargetLowering::Expand: 2202 if (Tmp1.getOpcode() == ISD::SETCC) { 2203 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2204 Tmp2, Tmp3, 2205 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2206 } else { 2207 Result = DAG.getSelectCC(Tmp1, 2208 DAG.getConstant(0, Tmp1.getValueType()), 2209 Tmp2, Tmp3, ISD::SETNE); 2210 } 2211 break; 2212 case TargetLowering::Promote: { 2213 MVT::ValueType NVT = 2214 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2215 unsigned ExtOp, TruncOp; 2216 if (MVT::isVector(Tmp2.getValueType())) { 2217 ExtOp = ISD::BIT_CONVERT; 2218 TruncOp = ISD::BIT_CONVERT; 2219 } else if (MVT::isInteger(Tmp2.getValueType())) { 2220 ExtOp = ISD::ANY_EXTEND; 2221 TruncOp = ISD::TRUNCATE; 2222 } else { 2223 ExtOp = ISD::FP_EXTEND; 2224 TruncOp = ISD::FP_ROUND; 2225 } 2226 // Promote each of the values to the new type. 2227 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2228 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2229 // Perform the larger operation, then round down. 2230 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2231 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2232 break; 2233 } 2234 } 2235 break; 2236 case ISD::SELECT_CC: { 2237 Tmp1 = Node->getOperand(0); // LHS 2238 Tmp2 = Node->getOperand(1); // RHS 2239 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2240 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2241 SDOperand CC = Node->getOperand(4); 2242 2243 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2244 2245 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2246 // the LHS is a legal SETCC itself. In this case, we need to compare 2247 // the result against zero to select between true and false values. 2248 if (Tmp2.Val == 0) { 2249 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2250 CC = DAG.getCondCode(ISD::SETNE); 2251 } 2252 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2253 2254 // Everything is legal, see if we should expand this op or something. 2255 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2256 default: assert(0 && "This action is not supported yet!"); 2257 case TargetLowering::Legal: break; 2258 case TargetLowering::Custom: 2259 Tmp1 = TLI.LowerOperation(Result, DAG); 2260 if (Tmp1.Val) Result = Tmp1; 2261 break; 2262 } 2263 break; 2264 } 2265 case ISD::SETCC: 2266 Tmp1 = Node->getOperand(0); 2267 Tmp2 = Node->getOperand(1); 2268 Tmp3 = Node->getOperand(2); 2269 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2270 2271 // If we had to Expand the SetCC operands into a SELECT node, then it may 2272 // not always be possible to return a true LHS & RHS. In this case, just 2273 // return the value we legalized, returned in the LHS 2274 if (Tmp2.Val == 0) { 2275 Result = Tmp1; 2276 break; 2277 } 2278 2279 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2280 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2281 case TargetLowering::Custom: 2282 isCustom = true; 2283 // FALLTHROUGH. 2284 case TargetLowering::Legal: 2285 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2286 if (isCustom) { 2287 Tmp4 = TLI.LowerOperation(Result, DAG); 2288 if (Tmp4.Val) Result = Tmp4; 2289 } 2290 break; 2291 case TargetLowering::Promote: { 2292 // First step, figure out the appropriate operation to use. 2293 // Allow SETCC to not be supported for all legal data types 2294 // Mostly this targets FP 2295 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2296 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2297 2298 // Scan for the appropriate larger type to use. 2299 while (1) { 2300 NewInTy = (MVT::ValueType)(NewInTy+1); 2301 2302 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2303 "Fell off of the edge of the integer world"); 2304 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2305 "Fell off of the edge of the floating point world"); 2306 2307 // If the target supports SETCC of this type, use it. 2308 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2309 break; 2310 } 2311 if (MVT::isInteger(NewInTy)) 2312 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2313 else { 2314 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2315 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2316 } 2317 Tmp1 = LegalizeOp(Tmp1); 2318 Tmp2 = LegalizeOp(Tmp2); 2319 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2320 Result = LegalizeOp(Result); 2321 break; 2322 } 2323 case TargetLowering::Expand: 2324 // Expand a setcc node into a select_cc of the same condition, lhs, and 2325 // rhs that selects between const 1 (true) and const 0 (false). 2326 MVT::ValueType VT = Node->getValueType(0); 2327 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2328 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2329 Tmp3); 2330 break; 2331 } 2332 break; 2333 case ISD::MEMSET: 2334 case ISD::MEMCPY: 2335 case ISD::MEMMOVE: { 2336 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2337 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2338 2339 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2340 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2341 case Expand: assert(0 && "Cannot expand a byte!"); 2342 case Legal: 2343 Tmp3 = LegalizeOp(Node->getOperand(2)); 2344 break; 2345 case Promote: 2346 Tmp3 = PromoteOp(Node->getOperand(2)); 2347 break; 2348 } 2349 } else { 2350 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2351 } 2352 2353 SDOperand Tmp4; 2354 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2355 case Expand: { 2356 // Length is too big, just take the lo-part of the length. 2357 SDOperand HiPart; 2358 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2359 break; 2360 } 2361 case Legal: 2362 Tmp4 = LegalizeOp(Node->getOperand(3)); 2363 break; 2364 case Promote: 2365 Tmp4 = PromoteOp(Node->getOperand(3)); 2366 break; 2367 } 2368 2369 SDOperand Tmp5; 2370 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2371 case Expand: assert(0 && "Cannot expand this yet!"); 2372 case Legal: 2373 Tmp5 = LegalizeOp(Node->getOperand(4)); 2374 break; 2375 case Promote: 2376 Tmp5 = PromoteOp(Node->getOperand(4)); 2377 break; 2378 } 2379 2380 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2381 default: assert(0 && "This action not implemented for this operation!"); 2382 case TargetLowering::Custom: 2383 isCustom = true; 2384 // FALLTHROUGH 2385 case TargetLowering::Legal: 2386 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2387 if (isCustom) { 2388 Tmp1 = TLI.LowerOperation(Result, DAG); 2389 if (Tmp1.Val) Result = Tmp1; 2390 } 2391 break; 2392 case TargetLowering::Expand: { 2393 // Otherwise, the target does not support this operation. Lower the 2394 // operation to an explicit libcall as appropriate. 2395 MVT::ValueType IntPtr = TLI.getPointerTy(); 2396 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2397 TargetLowering::ArgListTy Args; 2398 TargetLowering::ArgListEntry Entry; 2399 2400 const char *FnName = 0; 2401 if (Node->getOpcode() == ISD::MEMSET) { 2402 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2403 Args.push_back(Entry); 2404 // Extend the (previously legalized) ubyte argument to be an int value 2405 // for the call. 2406 if (Tmp3.getValueType() > MVT::i32) 2407 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2408 else 2409 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2410 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2411 Args.push_back(Entry); 2412 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2413 Args.push_back(Entry); 2414 2415 FnName = "memset"; 2416 } else if (Node->getOpcode() == ISD::MEMCPY || 2417 Node->getOpcode() == ISD::MEMMOVE) { 2418 Entry.Ty = IntPtrTy; 2419 Entry.Node = Tmp2; Args.push_back(Entry); 2420 Entry.Node = Tmp3; Args.push_back(Entry); 2421 Entry.Node = Tmp4; Args.push_back(Entry); 2422 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2423 } else { 2424 assert(0 && "Unknown op!"); 2425 } 2426 2427 std::pair<SDOperand,SDOperand> CallResult = 2428 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2429 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2430 Result = CallResult.second; 2431 break; 2432 } 2433 } 2434 break; 2435 } 2436 2437 case ISD::SHL_PARTS: 2438 case ISD::SRA_PARTS: 2439 case ISD::SRL_PARTS: { 2440 SmallVector<SDOperand, 8> Ops; 2441 bool Changed = false; 2442 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2443 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2444 Changed |= Ops.back() != Node->getOperand(i); 2445 } 2446 if (Changed) 2447 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2448 2449 switch (TLI.getOperationAction(Node->getOpcode(), 2450 Node->getValueType(0))) { 2451 default: assert(0 && "This action is not supported yet!"); 2452 case TargetLowering::Legal: break; 2453 case TargetLowering::Custom: 2454 Tmp1 = TLI.LowerOperation(Result, DAG); 2455 if (Tmp1.Val) { 2456 SDOperand Tmp2, RetVal(0, 0); 2457 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2458 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2459 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2460 if (i == Op.ResNo) 2461 RetVal = Tmp2; 2462 } 2463 assert(RetVal.Val && "Illegal result number"); 2464 return RetVal; 2465 } 2466 break; 2467 } 2468 2469 // Since these produce multiple values, make sure to remember that we 2470 // legalized all of them. 2471 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2472 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2473 return Result.getValue(Op.ResNo); 2474 } 2475 2476 // Binary operators 2477 case ISD::ADD: 2478 case ISD::SUB: 2479 case ISD::MUL: 2480 case ISD::MULHS: 2481 case ISD::MULHU: 2482 case ISD::UDIV: 2483 case ISD::SDIV: 2484 case ISD::AND: 2485 case ISD::OR: 2486 case ISD::XOR: 2487 case ISD::SHL: 2488 case ISD::SRL: 2489 case ISD::SRA: 2490 case ISD::FADD: 2491 case ISD::FSUB: 2492 case ISD::FMUL: 2493 case ISD::FDIV: 2494 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2495 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2496 case Expand: assert(0 && "Not possible"); 2497 case Legal: 2498 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2499 break; 2500 case Promote: 2501 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2502 break; 2503 } 2504 2505 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2506 2507 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2508 default: assert(0 && "BinOp legalize operation not supported"); 2509 case TargetLowering::Legal: break; 2510 case TargetLowering::Custom: 2511 Tmp1 = TLI.LowerOperation(Result, DAG); 2512 if (Tmp1.Val) Result = Tmp1; 2513 break; 2514 case TargetLowering::Expand: { 2515 if (Node->getValueType(0) == MVT::i32) { 2516 switch (Node->getOpcode()) { 2517 default: assert(0 && "Do not know how to expand this integer BinOp!"); 2518 case ISD::UDIV: 2519 case ISD::SDIV: 2520 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV 2521 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2522 SDOperand Dummy; 2523 bool isSigned = Node->getOpcode() == ISD::SDIV; 2524 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2525 }; 2526 break; 2527 } 2528 2529 assert(MVT::isVector(Node->getValueType(0)) && 2530 "Cannot expand this binary operator!"); 2531 // Expand the operation into a bunch of nasty scalar code. 2532 SmallVector<SDOperand, 8> Ops; 2533 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0)); 2534 MVT::ValueType PtrVT = TLI.getPointerTy(); 2535 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2536 i != e; ++i) { 2537 SDOperand Idx = DAG.getConstant(i, PtrVT); 2538 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2539 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2540 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2541 } 2542 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 2543 &Ops[0], Ops.size()); 2544 break; 2545 } 2546 case TargetLowering::Promote: { 2547 switch (Node->getOpcode()) { 2548 default: assert(0 && "Do not know how to promote this BinOp!"); 2549 case ISD::AND: 2550 case ISD::OR: 2551 case ISD::XOR: { 2552 MVT::ValueType OVT = Node->getValueType(0); 2553 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2554 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2555 // Bit convert each of the values to the new type. 2556 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2557 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2558 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2559 // Bit convert the result back the original type. 2560 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2561 break; 2562 } 2563 } 2564 } 2565 } 2566 break; 2567 2568 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2569 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2570 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2571 case Expand: assert(0 && "Not possible"); 2572 case Legal: 2573 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2574 break; 2575 case Promote: 2576 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2577 break; 2578 } 2579 2580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2581 2582 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2583 default: assert(0 && "Operation not supported"); 2584 case TargetLowering::Custom: 2585 Tmp1 = TLI.LowerOperation(Result, DAG); 2586 if (Tmp1.Val) Result = Tmp1; 2587 break; 2588 case TargetLowering::Legal: break; 2589 case TargetLowering::Expand: { 2590 // If this target supports fabs/fneg natively and select is cheap, 2591 // do this efficiently. 2592 if (!TLI.isSelectExpensive() && 2593 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2594 TargetLowering::Legal && 2595 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2596 TargetLowering::Legal) { 2597 // Get the sign bit of the RHS. 2598 MVT::ValueType IVT = 2599 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2600 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2601 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2602 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2603 // Get the absolute value of the result. 2604 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2605 // Select between the nabs and abs value based on the sign bit of 2606 // the input. 2607 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2608 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2609 AbsVal), 2610 AbsVal); 2611 Result = LegalizeOp(Result); 2612 break; 2613 } 2614 2615 // Otherwise, do bitwise ops! 2616 MVT::ValueType NVT = 2617 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2618 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2619 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2620 Result = LegalizeOp(Result); 2621 break; 2622 } 2623 } 2624 break; 2625 2626 case ISD::ADDC: 2627 case ISD::SUBC: 2628 Tmp1 = LegalizeOp(Node->getOperand(0)); 2629 Tmp2 = LegalizeOp(Node->getOperand(1)); 2630 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2631 // Since this produces two values, make sure to remember that we legalized 2632 // both of them. 2633 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2634 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2635 return Result; 2636 2637 case ISD::ADDE: 2638 case ISD::SUBE: 2639 Tmp1 = LegalizeOp(Node->getOperand(0)); 2640 Tmp2 = LegalizeOp(Node->getOperand(1)); 2641 Tmp3 = LegalizeOp(Node->getOperand(2)); 2642 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2643 // Since this produces two values, make sure to remember that we legalized 2644 // both of them. 2645 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2646 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2647 return Result; 2648 2649 case ISD::BUILD_PAIR: { 2650 MVT::ValueType PairTy = Node->getValueType(0); 2651 // TODO: handle the case where the Lo and Hi operands are not of legal type 2652 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2653 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2654 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2655 case TargetLowering::Promote: 2656 case TargetLowering::Custom: 2657 assert(0 && "Cannot promote/custom this yet!"); 2658 case TargetLowering::Legal: 2659 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2660 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2661 break; 2662 case TargetLowering::Expand: 2663 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2664 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2665 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2666 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2667 TLI.getShiftAmountTy())); 2668 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2669 break; 2670 } 2671 break; 2672 } 2673 2674 case ISD::UREM: 2675 case ISD::SREM: 2676 case ISD::FREM: 2677 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2678 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2679 2680 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2681 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2682 case TargetLowering::Custom: 2683 isCustom = true; 2684 // FALLTHROUGH 2685 case TargetLowering::Legal: 2686 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2687 if (isCustom) { 2688 Tmp1 = TLI.LowerOperation(Result, DAG); 2689 if (Tmp1.Val) Result = Tmp1; 2690 } 2691 break; 2692 case TargetLowering::Expand: 2693 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2694 bool isSigned = DivOpc == ISD::SDIV; 2695 if (MVT::isInteger(Node->getValueType(0))) { 2696 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) == 2697 TargetLowering::Legal) { 2698 // X % Y -> X-X/Y*Y 2699 MVT::ValueType VT = Node->getValueType(0); 2700 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2701 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2702 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2703 } else { 2704 assert(Node->getValueType(0) == MVT::i32 && 2705 "Cannot expand this binary operator!"); 2706 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2707 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2708 SDOperand Dummy; 2709 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2710 } 2711 } else { 2712 // Floating point mod -> fmod libcall. 2713 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2714 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2715 SDOperand Dummy; 2716 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2717 false/*sign irrelevant*/, Dummy); 2718 } 2719 break; 2720 } 2721 break; 2722 case ISD::VAARG: { 2723 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2724 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2725 2726 MVT::ValueType VT = Node->getValueType(0); 2727 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2728 default: assert(0 && "This action is not supported yet!"); 2729 case TargetLowering::Custom: 2730 isCustom = true; 2731 // FALLTHROUGH 2732 case TargetLowering::Legal: 2733 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2734 Result = Result.getValue(0); 2735 Tmp1 = Result.getValue(1); 2736 2737 if (isCustom) { 2738 Tmp2 = TLI.LowerOperation(Result, DAG); 2739 if (Tmp2.Val) { 2740 Result = LegalizeOp(Tmp2); 2741 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2742 } 2743 } 2744 break; 2745 case TargetLowering::Expand: { 2746 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2747 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2748 SV->getValue(), SV->getOffset()); 2749 // Increment the pointer, VAList, to the next vaarg 2750 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2751 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2752 TLI.getPointerTy())); 2753 // Store the incremented VAList to the legalized pointer 2754 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2755 SV->getOffset()); 2756 // Load the actual argument out of the pointer VAList 2757 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2758 Tmp1 = LegalizeOp(Result.getValue(1)); 2759 Result = LegalizeOp(Result); 2760 break; 2761 } 2762 } 2763 // Since VAARG produces two values, make sure to remember that we 2764 // legalized both of them. 2765 AddLegalizedOperand(SDOperand(Node, 0), Result); 2766 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2767 return Op.ResNo ? Tmp1 : Result; 2768 } 2769 2770 case ISD::VACOPY: 2771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2772 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2773 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2774 2775 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2776 default: assert(0 && "This action is not supported yet!"); 2777 case TargetLowering::Custom: 2778 isCustom = true; 2779 // FALLTHROUGH 2780 case TargetLowering::Legal: 2781 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2782 Node->getOperand(3), Node->getOperand(4)); 2783 if (isCustom) { 2784 Tmp1 = TLI.LowerOperation(Result, DAG); 2785 if (Tmp1.Val) Result = Tmp1; 2786 } 2787 break; 2788 case TargetLowering::Expand: 2789 // This defaults to loading a pointer from the input and storing it to the 2790 // output, returning the chain. 2791 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2792 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 2793 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2794 SVD->getOffset()); 2795 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 2796 SVS->getOffset()); 2797 break; 2798 } 2799 break; 2800 2801 case ISD::VAEND: 2802 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2803 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2804 2805 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2806 default: assert(0 && "This action is not supported yet!"); 2807 case TargetLowering::Custom: 2808 isCustom = true; 2809 // FALLTHROUGH 2810 case TargetLowering::Legal: 2811 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2812 if (isCustom) { 2813 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2814 if (Tmp1.Val) Result = Tmp1; 2815 } 2816 break; 2817 case TargetLowering::Expand: 2818 Result = Tmp1; // Default to a no-op, return the chain 2819 break; 2820 } 2821 break; 2822 2823 case ISD::VASTART: 2824 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2825 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2826 2827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2828 2829 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2830 default: assert(0 && "This action is not supported yet!"); 2831 case TargetLowering::Legal: break; 2832 case TargetLowering::Custom: 2833 Tmp1 = TLI.LowerOperation(Result, DAG); 2834 if (Tmp1.Val) Result = Tmp1; 2835 break; 2836 } 2837 break; 2838 2839 case ISD::ROTL: 2840 case ISD::ROTR: 2841 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2842 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2843 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2844 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2845 default: 2846 assert(0 && "ROTL/ROTR legalize operation not supported"); 2847 break; 2848 case TargetLowering::Legal: 2849 break; 2850 case TargetLowering::Custom: 2851 Tmp1 = TLI.LowerOperation(Result, DAG); 2852 if (Tmp1.Val) Result = Tmp1; 2853 break; 2854 case TargetLowering::Promote: 2855 assert(0 && "Do not know how to promote ROTL/ROTR"); 2856 break; 2857 case TargetLowering::Expand: 2858 assert(0 && "Do not know how to expand ROTL/ROTR"); 2859 break; 2860 } 2861 break; 2862 2863 case ISD::BSWAP: 2864 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2865 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2866 case TargetLowering::Custom: 2867 assert(0 && "Cannot custom legalize this yet!"); 2868 case TargetLowering::Legal: 2869 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2870 break; 2871 case TargetLowering::Promote: { 2872 MVT::ValueType OVT = Tmp1.getValueType(); 2873 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2874 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 2875 2876 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2877 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2878 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2879 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2880 break; 2881 } 2882 case TargetLowering::Expand: 2883 Result = ExpandBSWAP(Tmp1); 2884 break; 2885 } 2886 break; 2887 2888 case ISD::CTPOP: 2889 case ISD::CTTZ: 2890 case ISD::CTLZ: 2891 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2892 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2893 case TargetLowering::Custom: 2894 case TargetLowering::Legal: 2895 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2896 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 2897 TargetLowering::Custom) { 2898 Tmp1 = TLI.LowerOperation(Result, DAG); 2899 if (Tmp1.Val) { 2900 Result = Tmp1; 2901 } 2902 } 2903 break; 2904 case TargetLowering::Promote: { 2905 MVT::ValueType OVT = Tmp1.getValueType(); 2906 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2907 2908 // Zero extend the argument. 2909 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2910 // Perform the larger operation, then subtract if needed. 2911 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2912 switch (Node->getOpcode()) { 2913 case ISD::CTPOP: 2914 Result = Tmp1; 2915 break; 2916 case ISD::CTTZ: 2917 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2918 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2919 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 2920 ISD::SETEQ); 2921 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2922 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 2923 break; 2924 case ISD::CTLZ: 2925 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2926 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2927 DAG.getConstant(MVT::getSizeInBits(NVT) - 2928 MVT::getSizeInBits(OVT), NVT)); 2929 break; 2930 } 2931 break; 2932 } 2933 case TargetLowering::Expand: 2934 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2935 break; 2936 } 2937 break; 2938 2939 // Unary operators 2940 case ISD::FABS: 2941 case ISD::FNEG: 2942 case ISD::FSQRT: 2943 case ISD::FSIN: 2944 case ISD::FCOS: 2945 Tmp1 = LegalizeOp(Node->getOperand(0)); 2946 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2947 case TargetLowering::Promote: 2948 case TargetLowering::Custom: 2949 isCustom = true; 2950 // FALLTHROUGH 2951 case TargetLowering::Legal: 2952 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2953 if (isCustom) { 2954 Tmp1 = TLI.LowerOperation(Result, DAG); 2955 if (Tmp1.Val) Result = Tmp1; 2956 } 2957 break; 2958 case TargetLowering::Expand: 2959 switch (Node->getOpcode()) { 2960 default: assert(0 && "Unreachable!"); 2961 case ISD::FNEG: 2962 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2963 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2964 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2965 break; 2966 case ISD::FABS: { 2967 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2968 MVT::ValueType VT = Node->getValueType(0); 2969 Tmp2 = DAG.getConstantFP(0.0, VT); 2970 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2971 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2972 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2973 break; 2974 } 2975 case ISD::FSQRT: 2976 case ISD::FSIN: 2977 case ISD::FCOS: { 2978 MVT::ValueType VT = Node->getValueType(0); 2979 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2980 switch(Node->getOpcode()) { 2981 case ISD::FSQRT: 2982 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 2983 break; 2984 case ISD::FSIN: 2985 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 2986 break; 2987 case ISD::FCOS: 2988 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 2989 break; 2990 default: assert(0 && "Unreachable!"); 2991 } 2992 SDOperand Dummy; 2993 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2994 false/*sign irrelevant*/, Dummy); 2995 break; 2996 } 2997 } 2998 break; 2999 } 3000 break; 3001 case ISD::FPOWI: { 3002 // We always lower FPOWI into a libcall. No target support it yet. 3003 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 3004 ? RTLIB::POWI_F32 : RTLIB::POWI_F64; 3005 SDOperand Dummy; 3006 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3007 false/*sign irrelevant*/, Dummy); 3008 break; 3009 } 3010 case ISD::BIT_CONVERT: 3011 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3012 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3013 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3014 // The input has to be a vector type, we have to either scalarize it, pack 3015 // it, or convert it based on whether the input vector type is legal. 3016 SDNode *InVal = Node->getOperand(0).Val; 3017 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 3018 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 3019 3020 // Figure out if there is a simple type corresponding to this Vector 3021 // type. If so, convert to the vector type. 3022 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3023 if (TLI.isTypeLegal(TVT)) { 3024 // Turn this into a bit convert of the vector input. 3025 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3026 LegalizeOp(Node->getOperand(0))); 3027 break; 3028 } else if (NumElems == 1) { 3029 // Turn this into a bit convert of the scalar input. 3030 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3031 ScalarizeVectorOp(Node->getOperand(0))); 3032 break; 3033 } else { 3034 // FIXME: UNIMP! Store then reload 3035 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3036 } 3037 } else { 3038 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3039 Node->getOperand(0).getValueType())) { 3040 default: assert(0 && "Unknown operation action!"); 3041 case TargetLowering::Expand: 3042 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3043 break; 3044 case TargetLowering::Legal: 3045 Tmp1 = LegalizeOp(Node->getOperand(0)); 3046 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3047 break; 3048 } 3049 } 3050 break; 3051 3052 // Conversion operators. The source and destination have different types. 3053 case ISD::SINT_TO_FP: 3054 case ISD::UINT_TO_FP: { 3055 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3056 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3057 case Legal: 3058 switch (TLI.getOperationAction(Node->getOpcode(), 3059 Node->getOperand(0).getValueType())) { 3060 default: assert(0 && "Unknown operation action!"); 3061 case TargetLowering::Custom: 3062 isCustom = true; 3063 // FALLTHROUGH 3064 case TargetLowering::Legal: 3065 Tmp1 = LegalizeOp(Node->getOperand(0)); 3066 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3067 if (isCustom) { 3068 Tmp1 = TLI.LowerOperation(Result, DAG); 3069 if (Tmp1.Val) Result = Tmp1; 3070 } 3071 break; 3072 case TargetLowering::Expand: 3073 Result = ExpandLegalINT_TO_FP(isSigned, 3074 LegalizeOp(Node->getOperand(0)), 3075 Node->getValueType(0)); 3076 break; 3077 case TargetLowering::Promote: 3078 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3079 Node->getValueType(0), 3080 isSigned); 3081 break; 3082 } 3083 break; 3084 case Expand: 3085 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3086 Node->getValueType(0), Node->getOperand(0)); 3087 break; 3088 case Promote: 3089 Tmp1 = PromoteOp(Node->getOperand(0)); 3090 if (isSigned) { 3091 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3092 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3093 } else { 3094 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3095 Node->getOperand(0).getValueType()); 3096 } 3097 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3098 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3099 break; 3100 } 3101 break; 3102 } 3103 case ISD::TRUNCATE: 3104 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3105 case Legal: 3106 Tmp1 = LegalizeOp(Node->getOperand(0)); 3107 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3108 break; 3109 case Expand: 3110 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3111 3112 // Since the result is legal, we should just be able to truncate the low 3113 // part of the source. 3114 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3115 break; 3116 case Promote: 3117 Result = PromoteOp(Node->getOperand(0)); 3118 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3119 break; 3120 } 3121 break; 3122 3123 case ISD::FP_TO_SINT: 3124 case ISD::FP_TO_UINT: 3125 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3126 case Legal: 3127 Tmp1 = LegalizeOp(Node->getOperand(0)); 3128 3129 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3130 default: assert(0 && "Unknown operation action!"); 3131 case TargetLowering::Custom: 3132 isCustom = true; 3133 // FALLTHROUGH 3134 case TargetLowering::Legal: 3135 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3136 if (isCustom) { 3137 Tmp1 = TLI.LowerOperation(Result, DAG); 3138 if (Tmp1.Val) Result = Tmp1; 3139 } 3140 break; 3141 case TargetLowering::Promote: 3142 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3143 Node->getOpcode() == ISD::FP_TO_SINT); 3144 break; 3145 case TargetLowering::Expand: 3146 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3147 SDOperand True, False; 3148 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3149 MVT::ValueType NVT = Node->getValueType(0); 3150 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 3151 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 3152 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3153 Node->getOperand(0), Tmp2, ISD::SETLT); 3154 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3155 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3156 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3157 Tmp2)); 3158 False = DAG.getNode(ISD::XOR, NVT, False, 3159 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3160 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3161 break; 3162 } else { 3163 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3164 } 3165 break; 3166 } 3167 break; 3168 case Expand: { 3169 // Convert f32 / f64 to i32 / i64. 3170 MVT::ValueType VT = Op.getValueType(); 3171 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3172 switch (Node->getOpcode()) { 3173 case ISD::FP_TO_SINT: 3174 if (Node->getOperand(0).getValueType() == MVT::f32) 3175 LC = (VT == MVT::i32) 3176 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3177 else 3178 LC = (VT == MVT::i32) 3179 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3180 break; 3181 case ISD::FP_TO_UINT: 3182 if (Node->getOperand(0).getValueType() == MVT::f32) 3183 LC = (VT == MVT::i32) 3184 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3185 else 3186 LC = (VT == MVT::i32) 3187 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3188 break; 3189 default: assert(0 && "Unreachable!"); 3190 } 3191 SDOperand Dummy; 3192 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3193 false/*sign irrelevant*/, Dummy); 3194 break; 3195 } 3196 case Promote: 3197 Tmp1 = PromoteOp(Node->getOperand(0)); 3198 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3199 Result = LegalizeOp(Result); 3200 break; 3201 } 3202 break; 3203 3204 case ISD::FP_EXTEND: 3205 case ISD::FP_ROUND: { 3206 MVT::ValueType newVT = Op.getValueType(); 3207 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3208 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3209 // The only way we can lower this is to turn it into a STORE, 3210 // LOAD pair, targetting a temporary location (a stack slot). 3211 3212 // NOTE: there is a choice here between constantly creating new stack 3213 // slots and always reusing the same one. We currently always create 3214 // new ones, as reuse may inhibit scheduling. 3215 MVT::ValueType slotVT = 3216 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT; 3217 const Type *Ty = MVT::getTypeForValueType(slotVT); 3218 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3219 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3220 MachineFunction &MF = DAG.getMachineFunction(); 3221 int SSFI = 3222 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3223 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3224 if (Node->getOpcode() == ISD::FP_EXTEND) { 3225 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), 3226 StackSlot, NULL, 0); 3227 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT, 3228 Result, StackSlot, NULL, 0, oldVT); 3229 } else { 3230 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3231 StackSlot, NULL, 0, newVT); 3232 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT); 3233 } 3234 break; 3235 } 3236 } 3237 // FALL THROUGH 3238 case ISD::ANY_EXTEND: 3239 case ISD::ZERO_EXTEND: 3240 case ISD::SIGN_EXTEND: 3241 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3242 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3243 case Legal: 3244 Tmp1 = LegalizeOp(Node->getOperand(0)); 3245 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3246 break; 3247 case Promote: 3248 switch (Node->getOpcode()) { 3249 case ISD::ANY_EXTEND: 3250 Tmp1 = PromoteOp(Node->getOperand(0)); 3251 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3252 break; 3253 case ISD::ZERO_EXTEND: 3254 Result = PromoteOp(Node->getOperand(0)); 3255 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3256 Result = DAG.getZeroExtendInReg(Result, 3257 Node->getOperand(0).getValueType()); 3258 break; 3259 case ISD::SIGN_EXTEND: 3260 Result = PromoteOp(Node->getOperand(0)); 3261 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3262 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3263 Result, 3264 DAG.getValueType(Node->getOperand(0).getValueType())); 3265 break; 3266 case ISD::FP_EXTEND: 3267 Result = PromoteOp(Node->getOperand(0)); 3268 if (Result.getValueType() != Op.getValueType()) 3269 // Dynamically dead while we have only 2 FP types. 3270 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3271 break; 3272 case ISD::FP_ROUND: 3273 Result = PromoteOp(Node->getOperand(0)); 3274 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3275 break; 3276 } 3277 } 3278 break; 3279 case ISD::FP_ROUND_INREG: 3280 case ISD::SIGN_EXTEND_INREG: { 3281 Tmp1 = LegalizeOp(Node->getOperand(0)); 3282 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3283 3284 // If this operation is not supported, convert it to a shl/shr or load/store 3285 // pair. 3286 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3287 default: assert(0 && "This action not supported for this op yet!"); 3288 case TargetLowering::Legal: 3289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3290 break; 3291 case TargetLowering::Expand: 3292 // If this is an integer extend and shifts are supported, do that. 3293 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3294 // NOTE: we could fall back on load/store here too for targets without 3295 // SAR. However, it is doubtful that any exist. 3296 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3297 MVT::getSizeInBits(ExtraVT); 3298 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3299 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3300 Node->getOperand(0), ShiftCst); 3301 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3302 Result, ShiftCst); 3303 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3304 // The only way we can lower this is to turn it into a TRUNCSTORE, 3305 // EXTLOAD pair, targetting a temporary location (a stack slot). 3306 3307 // NOTE: there is a choice here between constantly creating new stack 3308 // slots and always reusing the same one. We currently always create 3309 // new ones, as reuse may inhibit scheduling. 3310 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3311 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3312 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3313 MachineFunction &MF = DAG.getMachineFunction(); 3314 int SSFI = 3315 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3316 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3317 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3318 StackSlot, NULL, 0, ExtraVT); 3319 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3320 Result, StackSlot, NULL, 0, ExtraVT); 3321 } else { 3322 assert(0 && "Unknown op"); 3323 } 3324 break; 3325 } 3326 break; 3327 } 3328 case ISD::ADJUST_TRAMP: { 3329 Tmp1 = LegalizeOp(Node->getOperand(0)); 3330 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3331 default: assert(0 && "This action is not supported yet!"); 3332 case TargetLowering::Custom: 3333 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3334 Result = TLI.LowerOperation(Result, DAG); 3335 if (Result.Val) break; 3336 // FALL THROUGH 3337 case TargetLowering::Expand: 3338 Result = Tmp1; 3339 break; 3340 } 3341 break; 3342 } 3343 case ISD::TRAMPOLINE: { 3344 SDOperand Ops[6]; 3345 for (unsigned i = 0; i != 6; ++i) 3346 Ops[i] = LegalizeOp(Node->getOperand(i)); 3347 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3348 // The only option for this node is to custom lower it. 3349 Result = TLI.LowerOperation(Result, DAG); 3350 assert(Result.Val && "Should always custom lower!"); 3351 break; 3352 } 3353 } 3354 3355 assert(Result.getValueType() == Op.getValueType() && 3356 "Bad legalization!"); 3357 3358 // Make sure that the generated code is itself legal. 3359 if (Result != Op) 3360 Result = LegalizeOp(Result); 3361 3362 // Note that LegalizeOp may be reentered even from single-use nodes, which 3363 // means that we always must cache transformed nodes. 3364 AddLegalizedOperand(Op, Result); 3365 return Result; 3366} 3367 3368/// PromoteOp - Given an operation that produces a value in an invalid type, 3369/// promote it to compute the value into a larger type. The produced value will 3370/// have the correct bits for the low portion of the register, but no guarantee 3371/// is made about the top bits: it may be zero, sign-extended, or garbage. 3372SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3373 MVT::ValueType VT = Op.getValueType(); 3374 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3375 assert(getTypeAction(VT) == Promote && 3376 "Caller should expand or legalize operands that are not promotable!"); 3377 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3378 "Cannot promote to smaller type!"); 3379 3380 SDOperand Tmp1, Tmp2, Tmp3; 3381 SDOperand Result; 3382 SDNode *Node = Op.Val; 3383 3384 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3385 if (I != PromotedNodes.end()) return I->second; 3386 3387 switch (Node->getOpcode()) { 3388 case ISD::CopyFromReg: 3389 assert(0 && "CopyFromReg must be legal!"); 3390 default: 3391#ifndef NDEBUG 3392 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3393#endif 3394 assert(0 && "Do not know how to promote this operator!"); 3395 abort(); 3396 case ISD::UNDEF: 3397 Result = DAG.getNode(ISD::UNDEF, NVT); 3398 break; 3399 case ISD::Constant: 3400 if (VT != MVT::i1) 3401 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3402 else 3403 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3404 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3405 break; 3406 case ISD::ConstantFP: 3407 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3408 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3409 break; 3410 3411 case ISD::SETCC: 3412 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3413 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3414 Node->getOperand(1), Node->getOperand(2)); 3415 break; 3416 3417 case ISD::TRUNCATE: 3418 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3419 case Legal: 3420 Result = LegalizeOp(Node->getOperand(0)); 3421 assert(Result.getValueType() >= NVT && 3422 "This truncation doesn't make sense!"); 3423 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3424 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3425 break; 3426 case Promote: 3427 // The truncation is not required, because we don't guarantee anything 3428 // about high bits anyway. 3429 Result = PromoteOp(Node->getOperand(0)); 3430 break; 3431 case Expand: 3432 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3433 // Truncate the low part of the expanded value to the result type 3434 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3435 } 3436 break; 3437 case ISD::SIGN_EXTEND: 3438 case ISD::ZERO_EXTEND: 3439 case ISD::ANY_EXTEND: 3440 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3441 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3442 case Legal: 3443 // Input is legal? Just do extend all the way to the larger type. 3444 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3445 break; 3446 case Promote: 3447 // Promote the reg if it's smaller. 3448 Result = PromoteOp(Node->getOperand(0)); 3449 // The high bits are not guaranteed to be anything. Insert an extend. 3450 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3451 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3452 DAG.getValueType(Node->getOperand(0).getValueType())); 3453 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3454 Result = DAG.getZeroExtendInReg(Result, 3455 Node->getOperand(0).getValueType()); 3456 break; 3457 } 3458 break; 3459 case ISD::BIT_CONVERT: 3460 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3461 Result = PromoteOp(Result); 3462 break; 3463 3464 case ISD::FP_EXTEND: 3465 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3466 case ISD::FP_ROUND: 3467 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3468 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3469 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3470 case Legal: 3471 // Input is legal? Do an FP_ROUND_INREG. 3472 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3473 DAG.getValueType(VT)); 3474 break; 3475 } 3476 break; 3477 3478 case ISD::SINT_TO_FP: 3479 case ISD::UINT_TO_FP: 3480 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3481 case Legal: 3482 // No extra round required here. 3483 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3484 break; 3485 3486 case Promote: 3487 Result = PromoteOp(Node->getOperand(0)); 3488 if (Node->getOpcode() == ISD::SINT_TO_FP) 3489 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3490 Result, 3491 DAG.getValueType(Node->getOperand(0).getValueType())); 3492 else 3493 Result = DAG.getZeroExtendInReg(Result, 3494 Node->getOperand(0).getValueType()); 3495 // No extra round required here. 3496 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3497 break; 3498 case Expand: 3499 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3500 Node->getOperand(0)); 3501 // Round if we cannot tolerate excess precision. 3502 if (NoExcessFPPrecision) 3503 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3504 DAG.getValueType(VT)); 3505 break; 3506 } 3507 break; 3508 3509 case ISD::SIGN_EXTEND_INREG: 3510 Result = PromoteOp(Node->getOperand(0)); 3511 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3512 Node->getOperand(1)); 3513 break; 3514 case ISD::FP_TO_SINT: 3515 case ISD::FP_TO_UINT: 3516 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3517 case Legal: 3518 case Expand: 3519 Tmp1 = Node->getOperand(0); 3520 break; 3521 case Promote: 3522 // The input result is prerounded, so we don't have to do anything 3523 // special. 3524 Tmp1 = PromoteOp(Node->getOperand(0)); 3525 break; 3526 } 3527 // If we're promoting a UINT to a larger size, check to see if the new node 3528 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3529 // we can use that instead. This allows us to generate better code for 3530 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3531 // legal, such as PowerPC. 3532 if (Node->getOpcode() == ISD::FP_TO_UINT && 3533 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3534 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3535 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3536 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3537 } else { 3538 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3539 } 3540 break; 3541 3542 case ISD::FABS: 3543 case ISD::FNEG: 3544 Tmp1 = PromoteOp(Node->getOperand(0)); 3545 assert(Tmp1.getValueType() == NVT); 3546 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3547 // NOTE: we do not have to do any extra rounding here for 3548 // NoExcessFPPrecision, because we know the input will have the appropriate 3549 // precision, and these operations don't modify precision at all. 3550 break; 3551 3552 case ISD::FSQRT: 3553 case ISD::FSIN: 3554 case ISD::FCOS: 3555 Tmp1 = PromoteOp(Node->getOperand(0)); 3556 assert(Tmp1.getValueType() == NVT); 3557 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3558 if (NoExcessFPPrecision) 3559 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3560 DAG.getValueType(VT)); 3561 break; 3562 3563 case ISD::FPOWI: { 3564 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3565 // directly as well, which may be better. 3566 Tmp1 = PromoteOp(Node->getOperand(0)); 3567 assert(Tmp1.getValueType() == NVT); 3568 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3569 if (NoExcessFPPrecision) 3570 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3571 DAG.getValueType(VT)); 3572 break; 3573 } 3574 3575 case ISD::AND: 3576 case ISD::OR: 3577 case ISD::XOR: 3578 case ISD::ADD: 3579 case ISD::SUB: 3580 case ISD::MUL: 3581 // The input may have strange things in the top bits of the registers, but 3582 // these operations don't care. They may have weird bits going out, but 3583 // that too is okay if they are integer operations. 3584 Tmp1 = PromoteOp(Node->getOperand(0)); 3585 Tmp2 = PromoteOp(Node->getOperand(1)); 3586 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3587 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3588 break; 3589 case ISD::FADD: 3590 case ISD::FSUB: 3591 case ISD::FMUL: 3592 Tmp1 = PromoteOp(Node->getOperand(0)); 3593 Tmp2 = PromoteOp(Node->getOperand(1)); 3594 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3595 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3596 3597 // Floating point operations will give excess precision that we may not be 3598 // able to tolerate. If we DO allow excess precision, just leave it, 3599 // otherwise excise it. 3600 // FIXME: Why would we need to round FP ops more than integer ones? 3601 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3602 if (NoExcessFPPrecision) 3603 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3604 DAG.getValueType(VT)); 3605 break; 3606 3607 case ISD::SDIV: 3608 case ISD::SREM: 3609 // These operators require that their input be sign extended. 3610 Tmp1 = PromoteOp(Node->getOperand(0)); 3611 Tmp2 = PromoteOp(Node->getOperand(1)); 3612 if (MVT::isInteger(NVT)) { 3613 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3614 DAG.getValueType(VT)); 3615 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3616 DAG.getValueType(VT)); 3617 } 3618 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3619 3620 // Perform FP_ROUND: this is probably overly pessimistic. 3621 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3622 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3623 DAG.getValueType(VT)); 3624 break; 3625 case ISD::FDIV: 3626 case ISD::FREM: 3627 case ISD::FCOPYSIGN: 3628 // These operators require that their input be fp extended. 3629 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3630 case Legal: 3631 Tmp1 = LegalizeOp(Node->getOperand(0)); 3632 break; 3633 case Promote: 3634 Tmp1 = PromoteOp(Node->getOperand(0)); 3635 break; 3636 case Expand: 3637 assert(0 && "not implemented"); 3638 } 3639 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3640 case Legal: 3641 Tmp2 = LegalizeOp(Node->getOperand(1)); 3642 break; 3643 case Promote: 3644 Tmp2 = PromoteOp(Node->getOperand(1)); 3645 break; 3646 case Expand: 3647 assert(0 && "not implemented"); 3648 } 3649 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3650 3651 // Perform FP_ROUND: this is probably overly pessimistic. 3652 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3653 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3654 DAG.getValueType(VT)); 3655 break; 3656 3657 case ISD::UDIV: 3658 case ISD::UREM: 3659 // These operators require that their input be zero extended. 3660 Tmp1 = PromoteOp(Node->getOperand(0)); 3661 Tmp2 = PromoteOp(Node->getOperand(1)); 3662 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3663 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3664 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3665 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3666 break; 3667 3668 case ISD::SHL: 3669 Tmp1 = PromoteOp(Node->getOperand(0)); 3670 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3671 break; 3672 case ISD::SRA: 3673 // The input value must be properly sign extended. 3674 Tmp1 = PromoteOp(Node->getOperand(0)); 3675 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3676 DAG.getValueType(VT)); 3677 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3678 break; 3679 case ISD::SRL: 3680 // The input value must be properly zero extended. 3681 Tmp1 = PromoteOp(Node->getOperand(0)); 3682 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3683 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3684 break; 3685 3686 case ISD::VAARG: 3687 Tmp1 = Node->getOperand(0); // Get the chain. 3688 Tmp2 = Node->getOperand(1); // Get the pointer. 3689 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3690 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3691 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3692 } else { 3693 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3694 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3695 SV->getValue(), SV->getOffset()); 3696 // Increment the pointer, VAList, to the next vaarg 3697 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3698 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3699 TLI.getPointerTy())); 3700 // Store the incremented VAList to the legalized pointer 3701 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3702 SV->getOffset()); 3703 // Load the actual argument out of the pointer VAList 3704 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3705 } 3706 // Remember that we legalized the chain. 3707 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3708 break; 3709 3710 case ISD::LOAD: { 3711 LoadSDNode *LD = cast<LoadSDNode>(Node); 3712 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3713 ? ISD::EXTLOAD : LD->getExtensionType(); 3714 Result = DAG.getExtLoad(ExtType, NVT, 3715 LD->getChain(), LD->getBasePtr(), 3716 LD->getSrcValue(), LD->getSrcValueOffset(), 3717 LD->getLoadedVT(), 3718 LD->isVolatile(), 3719 LD->getAlignment()); 3720 // Remember that we legalized the chain. 3721 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3722 break; 3723 } 3724 case ISD::SELECT: 3725 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3726 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3727 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3728 break; 3729 case ISD::SELECT_CC: 3730 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3731 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3732 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3733 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3734 break; 3735 case ISD::BSWAP: 3736 Tmp1 = Node->getOperand(0); 3737 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3738 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3739 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3740 DAG.getConstant(MVT::getSizeInBits(NVT) - 3741 MVT::getSizeInBits(VT), 3742 TLI.getShiftAmountTy())); 3743 break; 3744 case ISD::CTPOP: 3745 case ISD::CTTZ: 3746 case ISD::CTLZ: 3747 // Zero extend the argument 3748 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3749 // Perform the larger operation, then subtract if needed. 3750 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3751 switch(Node->getOpcode()) { 3752 case ISD::CTPOP: 3753 Result = Tmp1; 3754 break; 3755 case ISD::CTTZ: 3756 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3757 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3758 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3759 ISD::SETEQ); 3760 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3761 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 3762 break; 3763 case ISD::CTLZ: 3764 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3765 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3766 DAG.getConstant(MVT::getSizeInBits(NVT) - 3767 MVT::getSizeInBits(VT), NVT)); 3768 break; 3769 } 3770 break; 3771 case ISD::EXTRACT_SUBVECTOR: 3772 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 3773 break; 3774 case ISD::EXTRACT_VECTOR_ELT: 3775 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3776 break; 3777 } 3778 3779 assert(Result.Val && "Didn't set a result!"); 3780 3781 // Make sure the result is itself legal. 3782 Result = LegalizeOp(Result); 3783 3784 // Remember that we promoted this! 3785 AddPromotedOperand(Op, Result); 3786 return Result; 3787} 3788 3789/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3790/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 3791/// based on the vector type. The return type of this matches the element type 3792/// of the vector, which may not be legal for the target. 3793SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3794 // We know that operand #0 is the Vec vector. If the index is a constant 3795 // or if the invec is a supported hardware type, we can use it. Otherwise, 3796 // lower to a store then an indexed load. 3797 SDOperand Vec = Op.getOperand(0); 3798 SDOperand Idx = Op.getOperand(1); 3799 3800 SDNode *InVal = Vec.Val; 3801 MVT::ValueType TVT = InVal->getValueType(0); 3802 unsigned NumElems = MVT::getVectorNumElements(TVT); 3803 3804 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 3805 default: assert(0 && "This action is not supported yet!"); 3806 case TargetLowering::Custom: { 3807 Vec = LegalizeOp(Vec); 3808 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3809 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 3810 if (Tmp3.Val) 3811 return Tmp3; 3812 break; 3813 } 3814 case TargetLowering::Legal: 3815 if (isTypeLegal(TVT)) { 3816 Vec = LegalizeOp(Vec); 3817 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3818 return Op; 3819 } 3820 break; 3821 case TargetLowering::Expand: 3822 break; 3823 } 3824 3825 if (NumElems == 1) { 3826 // This must be an access of the only element. Return it. 3827 Op = ScalarizeVectorOp(Vec); 3828 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 3829 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 3830 SDOperand Lo, Hi; 3831 SplitVectorOp(Vec, Lo, Hi); 3832 if (CIdx->getValue() < NumElems/2) { 3833 Vec = Lo; 3834 } else { 3835 Vec = Hi; 3836 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 3837 Idx.getValueType()); 3838 } 3839 3840 // It's now an extract from the appropriate high or low part. Recurse. 3841 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3842 Op = ExpandEXTRACT_VECTOR_ELT(Op); 3843 } else { 3844 // Store the value to a temporary stack slot, then LOAD the scalar 3845 // element back out. 3846 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType()); 3847 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 3848 3849 // Add the offset to the index. 3850 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3851 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3852 DAG.getConstant(EltSize, Idx.getValueType())); 3853 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3854 3855 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 3856 } 3857 return Op; 3858} 3859 3860/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 3861/// we assume the operation can be split if it is not already legal. 3862SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 3863 // We know that operand #0 is the Vec vector. For now we assume the index 3864 // is a constant and that the extracted result is a supported hardware type. 3865 SDOperand Vec = Op.getOperand(0); 3866 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3867 3868 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 3869 3870 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 3871 // This must be an access of the desired vector length. Return it. 3872 return Vec; 3873 } 3874 3875 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 3876 SDOperand Lo, Hi; 3877 SplitVectorOp(Vec, Lo, Hi); 3878 if (CIdx->getValue() < NumElems/2) { 3879 Vec = Lo; 3880 } else { 3881 Vec = Hi; 3882 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3883 } 3884 3885 // It's now an extract from the appropriate high or low part. Recurse. 3886 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3887 return ExpandEXTRACT_SUBVECTOR(Op); 3888} 3889 3890/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3891/// with condition CC on the current target. This usually involves legalizing 3892/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3893/// there may be no choice but to create a new SetCC node to represent the 3894/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3895/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3896void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3897 SDOperand &RHS, 3898 SDOperand &CC) { 3899 SDOperand Tmp1, Tmp2, Result; 3900 3901 switch (getTypeAction(LHS.getValueType())) { 3902 case Legal: 3903 Tmp1 = LegalizeOp(LHS); // LHS 3904 Tmp2 = LegalizeOp(RHS); // RHS 3905 break; 3906 case Promote: 3907 Tmp1 = PromoteOp(LHS); // LHS 3908 Tmp2 = PromoteOp(RHS); // RHS 3909 3910 // If this is an FP compare, the operands have already been extended. 3911 if (MVT::isInteger(LHS.getValueType())) { 3912 MVT::ValueType VT = LHS.getValueType(); 3913 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3914 3915 // Otherwise, we have to insert explicit sign or zero extends. Note 3916 // that we could insert sign extends for ALL conditions, but zero extend 3917 // is cheaper on many machines (an AND instead of two shifts), so prefer 3918 // it. 3919 switch (cast<CondCodeSDNode>(CC)->get()) { 3920 default: assert(0 && "Unknown integer comparison!"); 3921 case ISD::SETEQ: 3922 case ISD::SETNE: 3923 case ISD::SETUGE: 3924 case ISD::SETUGT: 3925 case ISD::SETULE: 3926 case ISD::SETULT: 3927 // ALL of these operations will work if we either sign or zero extend 3928 // the operands (including the unsigned comparisons!). Zero extend is 3929 // usually a simpler/cheaper operation, so prefer it. 3930 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3931 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3932 break; 3933 case ISD::SETGE: 3934 case ISD::SETGT: 3935 case ISD::SETLT: 3936 case ISD::SETLE: 3937 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3938 DAG.getValueType(VT)); 3939 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3940 DAG.getValueType(VT)); 3941 break; 3942 } 3943 } 3944 break; 3945 case Expand: { 3946 MVT::ValueType VT = LHS.getValueType(); 3947 if (VT == MVT::f32 || VT == MVT::f64) { 3948 // Expand into one or more soft-fp libcall(s). 3949 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 3950 switch (cast<CondCodeSDNode>(CC)->get()) { 3951 case ISD::SETEQ: 3952 case ISD::SETOEQ: 3953 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3954 break; 3955 case ISD::SETNE: 3956 case ISD::SETUNE: 3957 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 3958 break; 3959 case ISD::SETGE: 3960 case ISD::SETOGE: 3961 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3962 break; 3963 case ISD::SETLT: 3964 case ISD::SETOLT: 3965 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3966 break; 3967 case ISD::SETLE: 3968 case ISD::SETOLE: 3969 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3970 break; 3971 case ISD::SETGT: 3972 case ISD::SETOGT: 3973 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3974 break; 3975 case ISD::SETUO: 3976 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3977 break; 3978 case ISD::SETO: 3979 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 3980 break; 3981 default: 3982 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3983 switch (cast<CondCodeSDNode>(CC)->get()) { 3984 case ISD::SETONE: 3985 // SETONE = SETOLT | SETOGT 3986 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3987 // Fallthrough 3988 case ISD::SETUGT: 3989 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3990 break; 3991 case ISD::SETUGE: 3992 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3993 break; 3994 case ISD::SETULT: 3995 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3996 break; 3997 case ISD::SETULE: 3998 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3999 break; 4000 case ISD::SETUEQ: 4001 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4002 break; 4003 default: assert(0 && "Unsupported FP setcc!"); 4004 } 4005 } 4006 4007 SDOperand Dummy; 4008 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4009 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4010 false /*sign irrelevant*/, Dummy); 4011 Tmp2 = DAG.getConstant(0, MVT::i32); 4012 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4013 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4014 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4015 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4016 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4017 false /*sign irrelevant*/, Dummy); 4018 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4019 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4020 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4021 Tmp2 = SDOperand(); 4022 } 4023 LHS = Tmp1; 4024 RHS = Tmp2; 4025 return; 4026 } 4027 4028 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4029 ExpandOp(LHS, LHSLo, LHSHi); 4030 ExpandOp(RHS, RHSLo, RHSHi); 4031 switch (cast<CondCodeSDNode>(CC)->get()) { 4032 case ISD::SETEQ: 4033 case ISD::SETNE: 4034 if (RHSLo == RHSHi) 4035 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4036 if (RHSCST->isAllOnesValue()) { 4037 // Comparison to -1. 4038 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4039 Tmp2 = RHSLo; 4040 break; 4041 } 4042 4043 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4044 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4045 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4046 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4047 break; 4048 default: 4049 // If this is a comparison of the sign bit, just look at the top part. 4050 // X > -1, x < 0 4051 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4052 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4053 CST->getValue() == 0) || // X < 0 4054 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4055 CST->isAllOnesValue())) { // X > -1 4056 Tmp1 = LHSHi; 4057 Tmp2 = RHSHi; 4058 break; 4059 } 4060 4061 // FIXME: This generated code sucks. 4062 ISD::CondCode LowCC; 4063 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4064 switch (CCCode) { 4065 default: assert(0 && "Unknown integer setcc!"); 4066 case ISD::SETLT: 4067 case ISD::SETULT: LowCC = ISD::SETULT; break; 4068 case ISD::SETGT: 4069 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4070 case ISD::SETLE: 4071 case ISD::SETULE: LowCC = ISD::SETULE; break; 4072 case ISD::SETGE: 4073 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4074 } 4075 4076 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4077 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4078 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4079 4080 // NOTE: on targets without efficient SELECT of bools, we can always use 4081 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4082 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4083 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4084 false, DagCombineInfo); 4085 if (!Tmp1.Val) 4086 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4087 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4088 CCCode, false, DagCombineInfo); 4089 if (!Tmp2.Val) 4090 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 4091 4092 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4093 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4094 if ((Tmp1C && Tmp1C->getValue() == 0) || 4095 (Tmp2C && Tmp2C->getValue() == 0 && 4096 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4097 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4098 (Tmp2C && Tmp2C->getValue() == 1 && 4099 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4100 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4101 // low part is known false, returns high part. 4102 // For LE / GE, if high part is known false, ignore the low part. 4103 // For LT / GT, if high part is known true, ignore the low part. 4104 Tmp1 = Tmp2; 4105 Tmp2 = SDOperand(); 4106 } else { 4107 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4108 ISD::SETEQ, false, DagCombineInfo); 4109 if (!Result.Val) 4110 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4111 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4112 Result, Tmp1, Tmp2)); 4113 Tmp1 = Result; 4114 Tmp2 = SDOperand(); 4115 } 4116 } 4117 } 4118 } 4119 LHS = Tmp1; 4120 RHS = Tmp2; 4121} 4122 4123/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 4124/// The resultant code need not be legal. Note that SrcOp is the input operand 4125/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 4126SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 4127 SDOperand SrcOp) { 4128 // Create the stack frame object. 4129 SDOperand FIPtr = CreateStackTemporary(DestVT); 4130 4131 // Emit a store to the stack slot. 4132 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4133 // Result is a load from the stack slot. 4134 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4135} 4136 4137SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4138 // Create a vector sized/aligned stack slot, store the value to element #0, 4139 // then load the whole vector back out. 4140 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 4141 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4142 NULL, 0); 4143 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4144} 4145 4146 4147/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4148/// support the operation, but do support the resultant vector type. 4149SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4150 4151 // If the only non-undef value is the low element, turn this into a 4152 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4153 unsigned NumElems = Node->getNumOperands(); 4154 bool isOnlyLowElement = true; 4155 SDOperand SplatValue = Node->getOperand(0); 4156 std::map<SDOperand, std::vector<unsigned> > Values; 4157 Values[SplatValue].push_back(0); 4158 bool isConstant = true; 4159 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4160 SplatValue.getOpcode() != ISD::UNDEF) 4161 isConstant = false; 4162 4163 for (unsigned i = 1; i < NumElems; ++i) { 4164 SDOperand V = Node->getOperand(i); 4165 Values[V].push_back(i); 4166 if (V.getOpcode() != ISD::UNDEF) 4167 isOnlyLowElement = false; 4168 if (SplatValue != V) 4169 SplatValue = SDOperand(0,0); 4170 4171 // If this isn't a constant element or an undef, we can't use a constant 4172 // pool load. 4173 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4174 V.getOpcode() != ISD::UNDEF) 4175 isConstant = false; 4176 } 4177 4178 if (isOnlyLowElement) { 4179 // If the low element is an undef too, then this whole things is an undef. 4180 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4181 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4182 // Otherwise, turn this into a scalar_to_vector node. 4183 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4184 Node->getOperand(0)); 4185 } 4186 4187 // If all elements are constants, create a load from the constant pool. 4188 if (isConstant) { 4189 MVT::ValueType VT = Node->getValueType(0); 4190 const Type *OpNTy = 4191 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4192 std::vector<Constant*> CV; 4193 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4194 if (ConstantFPSDNode *V = 4195 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4196 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 4197 } else if (ConstantSDNode *V = 4198 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4199 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4200 } else { 4201 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4202 CV.push_back(UndefValue::get(OpNTy)); 4203 } 4204 } 4205 Constant *CP = ConstantVector::get(CV); 4206 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4207 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4208 } 4209 4210 if (SplatValue.Val) { // Splat of one value? 4211 // Build the shuffle constant vector: <0, 0, 0, 0> 4212 MVT::ValueType MaskVT = 4213 MVT::getIntVectorWithNumElements(NumElems); 4214 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4215 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4216 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4217 &ZeroVec[0], ZeroVec.size()); 4218 4219 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4220 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4221 // Get the splatted value into the low element of a vector register. 4222 SDOperand LowValVec = 4223 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4224 4225 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4226 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4227 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4228 SplatMask); 4229 } 4230 } 4231 4232 // If there are only two unique elements, we may be able to turn this into a 4233 // vector shuffle. 4234 if (Values.size() == 2) { 4235 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4236 MVT::ValueType MaskVT = 4237 MVT::getIntVectorWithNumElements(NumElems); 4238 std::vector<SDOperand> MaskVec(NumElems); 4239 unsigned i = 0; 4240 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4241 E = Values.end(); I != E; ++I) { 4242 for (std::vector<unsigned>::iterator II = I->second.begin(), 4243 EE = I->second.end(); II != EE; ++II) 4244 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4245 i += NumElems; 4246 } 4247 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4248 &MaskVec[0], MaskVec.size()); 4249 4250 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4251 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4252 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4253 SmallVector<SDOperand, 8> Ops; 4254 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4255 E = Values.end(); I != E; ++I) { 4256 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4257 I->first); 4258 Ops.push_back(Op); 4259 } 4260 Ops.push_back(ShuffleMask); 4261 4262 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4263 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4264 &Ops[0], Ops.size()); 4265 } 4266 } 4267 4268 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4269 // aligned object on the stack, store each element into it, then load 4270 // the result as a vector. 4271 MVT::ValueType VT = Node->getValueType(0); 4272 // Create the stack frame object. 4273 SDOperand FIPtr = CreateStackTemporary(VT); 4274 4275 // Emit a store of each element to the stack slot. 4276 SmallVector<SDOperand, 8> Stores; 4277 unsigned TypeByteSize = 4278 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4279 // Store (in the right endianness) the elements to memory. 4280 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4281 // Ignore undef elements. 4282 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4283 4284 unsigned Offset = TypeByteSize*i; 4285 4286 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4287 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4288 4289 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4290 NULL, 0)); 4291 } 4292 4293 SDOperand StoreChain; 4294 if (!Stores.empty()) // Not all undef elements? 4295 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4296 &Stores[0], Stores.size()); 4297 else 4298 StoreChain = DAG.getEntryNode(); 4299 4300 // Result is a load from the stack slot. 4301 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4302} 4303 4304/// CreateStackTemporary - Create a stack temporary, suitable for holding the 4305/// specified value type. 4306SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 4307 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4308 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 4309 const Type *Ty = MVT::getTypeForValueType(VT); 4310 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); 4311 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 4312 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 4313} 4314 4315void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4316 SDOperand Op, SDOperand Amt, 4317 SDOperand &Lo, SDOperand &Hi) { 4318 // Expand the subcomponents. 4319 SDOperand LHSL, LHSH; 4320 ExpandOp(Op, LHSL, LHSH); 4321 4322 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4323 MVT::ValueType VT = LHSL.getValueType(); 4324 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4325 Hi = Lo.getValue(1); 4326} 4327 4328 4329/// ExpandShift - Try to find a clever way to expand this shift operation out to 4330/// smaller elements. If we can't find a way that is more efficient than a 4331/// libcall on this target, return false. Otherwise, return true with the 4332/// low-parts expanded into Lo and Hi. 4333bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4334 SDOperand &Lo, SDOperand &Hi) { 4335 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4336 "This is not a shift!"); 4337 4338 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4339 SDOperand ShAmt = LegalizeOp(Amt); 4340 MVT::ValueType ShTy = ShAmt.getValueType(); 4341 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4342 unsigned NVTBits = MVT::getSizeInBits(NVT); 4343 4344 // Handle the case when Amt is an immediate. Other cases are currently broken 4345 // and are disabled. 4346 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4347 unsigned Cst = CN->getValue(); 4348 // Expand the incoming operand to be shifted, so that we have its parts 4349 SDOperand InL, InH; 4350 ExpandOp(Op, InL, InH); 4351 switch(Opc) { 4352 case ISD::SHL: 4353 if (Cst > VTBits) { 4354 Lo = DAG.getConstant(0, NVT); 4355 Hi = DAG.getConstant(0, NVT); 4356 } else if (Cst > NVTBits) { 4357 Lo = DAG.getConstant(0, NVT); 4358 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4359 } else if (Cst == NVTBits) { 4360 Lo = DAG.getConstant(0, NVT); 4361 Hi = InL; 4362 } else { 4363 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4364 Hi = DAG.getNode(ISD::OR, NVT, 4365 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4366 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4367 } 4368 return true; 4369 case ISD::SRL: 4370 if (Cst > VTBits) { 4371 Lo = DAG.getConstant(0, NVT); 4372 Hi = DAG.getConstant(0, NVT); 4373 } else if (Cst > NVTBits) { 4374 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4375 Hi = DAG.getConstant(0, NVT); 4376 } else if (Cst == NVTBits) { 4377 Lo = InH; 4378 Hi = DAG.getConstant(0, NVT); 4379 } else { 4380 Lo = DAG.getNode(ISD::OR, NVT, 4381 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4382 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4383 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4384 } 4385 return true; 4386 case ISD::SRA: 4387 if (Cst > VTBits) { 4388 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4389 DAG.getConstant(NVTBits-1, ShTy)); 4390 } else if (Cst > NVTBits) { 4391 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4392 DAG.getConstant(Cst-NVTBits, ShTy)); 4393 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4394 DAG.getConstant(NVTBits-1, ShTy)); 4395 } else if (Cst == NVTBits) { 4396 Lo = InH; 4397 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4398 DAG.getConstant(NVTBits-1, ShTy)); 4399 } else { 4400 Lo = DAG.getNode(ISD::OR, NVT, 4401 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4402 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4403 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4404 } 4405 return true; 4406 } 4407 } 4408 4409 // Okay, the shift amount isn't constant. However, if we can tell that it is 4410 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4411 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4412 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4413 4414 // If we know that the high bit of the shift amount is one, then we can do 4415 // this as a couple of simple shifts. 4416 if (KnownOne & Mask) { 4417 // Mask out the high bit, which we know is set. 4418 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4419 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4420 4421 // Expand the incoming operand to be shifted, so that we have its parts 4422 SDOperand InL, InH; 4423 ExpandOp(Op, InL, InH); 4424 switch(Opc) { 4425 case ISD::SHL: 4426 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4427 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4428 return true; 4429 case ISD::SRL: 4430 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4431 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4432 return true; 4433 case ISD::SRA: 4434 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4435 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4436 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4437 return true; 4438 } 4439 } 4440 4441 // If we know that the high bit of the shift amount is zero, then we can do 4442 // this as a couple of simple shifts. 4443 if (KnownZero & Mask) { 4444 // Compute 32-amt. 4445 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4446 DAG.getConstant(NVTBits, Amt.getValueType()), 4447 Amt); 4448 4449 // Expand the incoming operand to be shifted, so that we have its parts 4450 SDOperand InL, InH; 4451 ExpandOp(Op, InL, InH); 4452 switch(Opc) { 4453 case ISD::SHL: 4454 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4455 Hi = DAG.getNode(ISD::OR, NVT, 4456 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4457 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4458 return true; 4459 case ISD::SRL: 4460 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4461 Lo = DAG.getNode(ISD::OR, NVT, 4462 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4463 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4464 return true; 4465 case ISD::SRA: 4466 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4467 Lo = DAG.getNode(ISD::OR, NVT, 4468 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4469 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4470 return true; 4471 } 4472 } 4473 4474 return false; 4475} 4476 4477 4478// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4479// does not fit into a register, return the lo part and set the hi part to the 4480// by-reg argument. If it does fit into a single register, return the result 4481// and leave the Hi part unset. 4482SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4483 bool isSigned, SDOperand &Hi) { 4484 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4485 // The input chain to this libcall is the entry node of the function. 4486 // Legalizing the call will automatically add the previous call to the 4487 // dependence. 4488 SDOperand InChain = DAG.getEntryNode(); 4489 4490 TargetLowering::ArgListTy Args; 4491 TargetLowering::ArgListEntry Entry; 4492 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4493 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4494 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4495 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4496 Entry.isSExt = isSigned; 4497 Args.push_back(Entry); 4498 } 4499 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4500 4501 // Splice the libcall in wherever FindInputOutputChains tells us to. 4502 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4503 std::pair<SDOperand,SDOperand> CallInfo = 4504 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4505 Callee, Args, DAG); 4506 4507 // Legalize the call sequence, starting with the chain. This will advance 4508 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4509 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4510 LegalizeOp(CallInfo.second); 4511 SDOperand Result; 4512 switch (getTypeAction(CallInfo.first.getValueType())) { 4513 default: assert(0 && "Unknown thing"); 4514 case Legal: 4515 Result = CallInfo.first; 4516 break; 4517 case Expand: 4518 ExpandOp(CallInfo.first, Result, Hi); 4519 break; 4520 } 4521 return Result; 4522} 4523 4524 4525/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4526/// 4527SDOperand SelectionDAGLegalize:: 4528ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4529 assert(getTypeAction(Source.getValueType()) == Expand && 4530 "This is not an expansion!"); 4531 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4532 4533 if (!isSigned) { 4534 assert(Source.getValueType() == MVT::i64 && 4535 "This only works for 64-bit -> FP"); 4536 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4537 // incoming integer is set. To handle this, we dynamically test to see if 4538 // it is set, and, if so, add a fudge factor. 4539 SDOperand Lo, Hi; 4540 ExpandOp(Source, Lo, Hi); 4541 4542 // If this is unsigned, and not supported, first perform the conversion to 4543 // signed, then adjust the result if the sign bit is set. 4544 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4545 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4546 4547 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4548 DAG.getConstant(0, Hi.getValueType()), 4549 ISD::SETLT); 4550 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4551 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4552 SignSet, Four, Zero); 4553 uint64_t FF = 0x5f800000ULL; 4554 if (TLI.isLittleEndian()) FF <<= 32; 4555 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4556 4557 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4558 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4559 SDOperand FudgeInReg; 4560 if (DestTy == MVT::f32) 4561 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4562 else { 4563 assert(DestTy == MVT::f64 && "Unexpected conversion"); 4564 // FIXME: Avoid the extend by construction the right constantpool? 4565 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 4566 CPIdx, NULL, 0, MVT::f32); 4567 } 4568 MVT::ValueType SCVT = SignedConv.getValueType(); 4569 if (SCVT != DestTy) { 4570 // Destination type needs to be expanded as well. The FADD now we are 4571 // constructing will be expanded into a libcall. 4572 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 4573 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 4574 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 4575 SignedConv, SignedConv.getValue(1)); 4576 } 4577 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 4578 } 4579 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4580 } 4581 4582 // Check to see if the target has a custom way to lower this. If so, use it. 4583 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4584 default: assert(0 && "This action not implemented for this operation!"); 4585 case TargetLowering::Legal: 4586 case TargetLowering::Expand: 4587 break; // This case is handled below. 4588 case TargetLowering::Custom: { 4589 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4590 Source), DAG); 4591 if (NV.Val) 4592 return LegalizeOp(NV); 4593 break; // The target decided this was legal after all 4594 } 4595 } 4596 4597 // Expand the source, then glue it back together for the call. We must expand 4598 // the source in case it is shared (this pass of legalize must traverse it). 4599 SDOperand SrcLo, SrcHi; 4600 ExpandOp(Source, SrcLo, SrcHi); 4601 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4602 4603 RTLIB::Libcall LC; 4604 if (DestTy == MVT::f32) 4605 LC = RTLIB::SINTTOFP_I64_F32; 4606 else { 4607 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4608 LC = RTLIB::SINTTOFP_I64_F64; 4609 } 4610 4611 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 4612 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4613 SDOperand UnusedHiPart; 4614 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4615 UnusedHiPart); 4616} 4617 4618/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4619/// INT_TO_FP operation of the specified operand when the target requests that 4620/// we expand it. At this point, we know that the result and operand types are 4621/// legal for the target. 4622SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4623 SDOperand Op0, 4624 MVT::ValueType DestVT) { 4625 if (Op0.getValueType() == MVT::i32) { 4626 // simple 32-bit [signed|unsigned] integer to float/double expansion 4627 4628 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4629 MachineFunction &MF = DAG.getMachineFunction(); 4630 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4631 unsigned StackAlign = 4632 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 4633 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4634 // get address of 8 byte buffer 4635 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4636 // word offset constant for Hi/Lo address computation 4637 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4638 // set up Hi and Lo (into buffer) address based on endian 4639 SDOperand Hi = StackSlot; 4640 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4641 if (TLI.isLittleEndian()) 4642 std::swap(Hi, Lo); 4643 4644 // if signed map to unsigned space 4645 SDOperand Op0Mapped; 4646 if (isSigned) { 4647 // constant used to invert sign bit (signed to unsigned mapping) 4648 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4649 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4650 } else { 4651 Op0Mapped = Op0; 4652 } 4653 // store the lo of the constructed double - based on integer input 4654 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4655 Op0Mapped, Lo, NULL, 0); 4656 // initial hi portion of constructed double 4657 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4658 // store the hi of the constructed double - biased exponent 4659 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4660 // load the constructed double 4661 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4662 // FP constant to bias correct the final result 4663 SDOperand Bias = DAG.getConstantFP(isSigned ? 4664 BitsToDouble(0x4330000080000000ULL) 4665 : BitsToDouble(0x4330000000000000ULL), 4666 MVT::f64); 4667 // subtract the bias 4668 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4669 // final result 4670 SDOperand Result; 4671 // handle final rounding 4672 if (DestVT == MVT::f64) { 4673 // do nothing 4674 Result = Sub; 4675 } else { 4676 // if f32 then cast to f32 4677 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 4678 } 4679 return Result; 4680 } 4681 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4682 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4683 4684 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4685 DAG.getConstant(0, Op0.getValueType()), 4686 ISD::SETLT); 4687 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4688 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4689 SignSet, Four, Zero); 4690 4691 // If the sign bit of the integer is set, the large number will be treated 4692 // as a negative number. To counteract this, the dynamic code adds an 4693 // offset depending on the data type. 4694 uint64_t FF; 4695 switch (Op0.getValueType()) { 4696 default: assert(0 && "Unsupported integer type!"); 4697 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4698 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4699 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4700 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4701 } 4702 if (TLI.isLittleEndian()) FF <<= 32; 4703 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4704 4705 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4706 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4707 SDOperand FudgeInReg; 4708 if (DestVT == MVT::f32) 4709 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4710 else { 4711 assert(DestVT == MVT::f64 && "Unexpected conversion"); 4712 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 4713 DAG.getEntryNode(), CPIdx, 4714 NULL, 0, MVT::f32)); 4715 } 4716 4717 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 4718} 4719 4720/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 4721/// *INT_TO_FP operation of the specified operand when the target requests that 4722/// we promote it. At this point, we know that the result and operand types are 4723/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 4724/// operation that takes a larger input. 4725SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 4726 MVT::ValueType DestVT, 4727 bool isSigned) { 4728 // First step, figure out the appropriate *INT_TO_FP operation to use. 4729 MVT::ValueType NewInTy = LegalOp.getValueType(); 4730 4731 unsigned OpToUse = 0; 4732 4733 // Scan for the appropriate larger type to use. 4734 while (1) { 4735 NewInTy = (MVT::ValueType)(NewInTy+1); 4736 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 4737 4738 // If the target supports SINT_TO_FP of this type, use it. 4739 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 4740 default: break; 4741 case TargetLowering::Legal: 4742 if (!TLI.isTypeLegal(NewInTy)) 4743 break; // Can't use this datatype. 4744 // FALL THROUGH. 4745 case TargetLowering::Custom: 4746 OpToUse = ISD::SINT_TO_FP; 4747 break; 4748 } 4749 if (OpToUse) break; 4750 if (isSigned) continue; 4751 4752 // If the target supports UINT_TO_FP of this type, use it. 4753 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4754 default: break; 4755 case TargetLowering::Legal: 4756 if (!TLI.isTypeLegal(NewInTy)) 4757 break; // Can't use this datatype. 4758 // FALL THROUGH. 4759 case TargetLowering::Custom: 4760 OpToUse = ISD::UINT_TO_FP; 4761 break; 4762 } 4763 if (OpToUse) break; 4764 4765 // Otherwise, try a larger type. 4766 } 4767 4768 // Okay, we found the operation and type to use. Zero extend our input to the 4769 // desired type then run the operation on it. 4770 return DAG.getNode(OpToUse, DestVT, 4771 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4772 NewInTy, LegalOp)); 4773} 4774 4775/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4776/// FP_TO_*INT operation of the specified operand when the target requests that 4777/// we promote it. At this point, we know that the result and operand types are 4778/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4779/// operation that returns a larger result. 4780SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4781 MVT::ValueType DestVT, 4782 bool isSigned) { 4783 // First step, figure out the appropriate FP_TO*INT operation to use. 4784 MVT::ValueType NewOutTy = DestVT; 4785 4786 unsigned OpToUse = 0; 4787 4788 // Scan for the appropriate larger type to use. 4789 while (1) { 4790 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4791 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4792 4793 // If the target supports FP_TO_SINT returning this type, use it. 4794 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4795 default: break; 4796 case TargetLowering::Legal: 4797 if (!TLI.isTypeLegal(NewOutTy)) 4798 break; // Can't use this datatype. 4799 // FALL THROUGH. 4800 case TargetLowering::Custom: 4801 OpToUse = ISD::FP_TO_SINT; 4802 break; 4803 } 4804 if (OpToUse) break; 4805 4806 // If the target supports FP_TO_UINT of this type, use it. 4807 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4808 default: break; 4809 case TargetLowering::Legal: 4810 if (!TLI.isTypeLegal(NewOutTy)) 4811 break; // Can't use this datatype. 4812 // FALL THROUGH. 4813 case TargetLowering::Custom: 4814 OpToUse = ISD::FP_TO_UINT; 4815 break; 4816 } 4817 if (OpToUse) break; 4818 4819 // Otherwise, try a larger type. 4820 } 4821 4822 // Okay, we found the operation and type to use. Truncate the result of the 4823 // extended FP_TO_*INT operation to the desired size. 4824 return DAG.getNode(ISD::TRUNCATE, DestVT, 4825 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4826} 4827 4828/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4829/// 4830SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4831 MVT::ValueType VT = Op.getValueType(); 4832 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4833 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4834 switch (VT) { 4835 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4836 case MVT::i16: 4837 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4838 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4839 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4840 case MVT::i32: 4841 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4842 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4843 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4844 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4845 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4846 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4847 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4848 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4849 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4850 case MVT::i64: 4851 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4852 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4853 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4854 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4855 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4856 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4857 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4858 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4859 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4860 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4861 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4862 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4863 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4864 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4865 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4866 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4867 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4868 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4869 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4870 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4871 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4872 } 4873} 4874 4875/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4876/// 4877SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4878 switch (Opc) { 4879 default: assert(0 && "Cannot expand this yet!"); 4880 case ISD::CTPOP: { 4881 static const uint64_t mask[6] = { 4882 0x5555555555555555ULL, 0x3333333333333333ULL, 4883 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4884 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4885 }; 4886 MVT::ValueType VT = Op.getValueType(); 4887 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4888 unsigned len = MVT::getSizeInBits(VT); 4889 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4890 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4891 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4892 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4893 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4894 DAG.getNode(ISD::AND, VT, 4895 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4896 } 4897 return Op; 4898 } 4899 case ISD::CTLZ: { 4900 // for now, we do this: 4901 // x = x | (x >> 1); 4902 // x = x | (x >> 2); 4903 // ... 4904 // x = x | (x >>16); 4905 // x = x | (x >>32); // for 64-bit input 4906 // return popcount(~x); 4907 // 4908 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4909 MVT::ValueType VT = Op.getValueType(); 4910 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4911 unsigned len = MVT::getSizeInBits(VT); 4912 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4913 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4914 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4915 } 4916 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4917 return DAG.getNode(ISD::CTPOP, VT, Op); 4918 } 4919 case ISD::CTTZ: { 4920 // for now, we use: { return popcount(~x & (x - 1)); } 4921 // unless the target has ctlz but not ctpop, in which case we use: 4922 // { return 32 - nlz(~x & (x-1)); } 4923 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4924 MVT::ValueType VT = Op.getValueType(); 4925 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4926 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4927 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4928 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4929 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4930 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4931 TLI.isOperationLegal(ISD::CTLZ, VT)) 4932 return DAG.getNode(ISD::SUB, VT, 4933 DAG.getConstant(MVT::getSizeInBits(VT), VT), 4934 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4935 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4936 } 4937 } 4938} 4939 4940/// ExpandOp - Expand the specified SDOperand into its two component pieces 4941/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4942/// LegalizeNodes map is filled in for any results that are not expanded, the 4943/// ExpandedNodes map is filled in for any results that are expanded, and the 4944/// Lo/Hi values are returned. 4945void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4946 MVT::ValueType VT = Op.getValueType(); 4947 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4948 SDNode *Node = Op.Val; 4949 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4950 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 4951 MVT::isVector(VT)) && 4952 "Cannot expand to FP value or to larger int value!"); 4953 4954 // See if we already expanded it. 4955 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4956 = ExpandedNodes.find(Op); 4957 if (I != ExpandedNodes.end()) { 4958 Lo = I->second.first; 4959 Hi = I->second.second; 4960 return; 4961 } 4962 4963 switch (Node->getOpcode()) { 4964 case ISD::CopyFromReg: 4965 assert(0 && "CopyFromReg must be legal!"); 4966 default: 4967#ifndef NDEBUG 4968 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4969#endif 4970 assert(0 && "Do not know how to expand this operator!"); 4971 abort(); 4972 case ISD::UNDEF: 4973 NVT = TLI.getTypeToExpandTo(VT); 4974 Lo = DAG.getNode(ISD::UNDEF, NVT); 4975 Hi = DAG.getNode(ISD::UNDEF, NVT); 4976 break; 4977 case ISD::Constant: { 4978 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4979 Lo = DAG.getConstant(Cst, NVT); 4980 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4981 break; 4982 } 4983 case ISD::ConstantFP: { 4984 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 4985 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 4986 if (getTypeAction(Lo.getValueType()) == Expand) 4987 ExpandOp(Lo, Lo, Hi); 4988 break; 4989 } 4990 case ISD::BUILD_PAIR: 4991 // Return the operands. 4992 Lo = Node->getOperand(0); 4993 Hi = Node->getOperand(1); 4994 break; 4995 4996 case ISD::SIGN_EXTEND_INREG: 4997 ExpandOp(Node->getOperand(0), Lo, Hi); 4998 // sext_inreg the low part if needed. 4999 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5000 5001 // The high part gets the sign extension from the lo-part. This handles 5002 // things like sextinreg V:i64 from i8. 5003 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5004 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5005 TLI.getShiftAmountTy())); 5006 break; 5007 5008 case ISD::BSWAP: { 5009 ExpandOp(Node->getOperand(0), Lo, Hi); 5010 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5011 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5012 Lo = TempLo; 5013 break; 5014 } 5015 5016 case ISD::CTPOP: 5017 ExpandOp(Node->getOperand(0), Lo, Hi); 5018 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5019 DAG.getNode(ISD::CTPOP, NVT, Lo), 5020 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5021 Hi = DAG.getConstant(0, NVT); 5022 break; 5023 5024 case ISD::CTLZ: { 5025 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5026 ExpandOp(Node->getOperand(0), Lo, Hi); 5027 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5028 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5029 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5030 ISD::SETNE); 5031 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5032 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5033 5034 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5035 Hi = DAG.getConstant(0, NVT); 5036 break; 5037 } 5038 5039 case ISD::CTTZ: { 5040 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5041 ExpandOp(Node->getOperand(0), Lo, Hi); 5042 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5043 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5044 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5045 ISD::SETNE); 5046 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5047 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5048 5049 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5050 Hi = DAG.getConstant(0, NVT); 5051 break; 5052 } 5053 5054 case ISD::VAARG: { 5055 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5056 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5057 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5058 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5059 5060 // Remember that we legalized the chain. 5061 Hi = LegalizeOp(Hi); 5062 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5063 if (!TLI.isLittleEndian()) 5064 std::swap(Lo, Hi); 5065 break; 5066 } 5067 5068 case ISD::LOAD: { 5069 LoadSDNode *LD = cast<LoadSDNode>(Node); 5070 SDOperand Ch = LD->getChain(); // Legalize the chain. 5071 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5072 ISD::LoadExtType ExtType = LD->getExtensionType(); 5073 int SVOffset = LD->getSrcValueOffset(); 5074 unsigned Alignment = LD->getAlignment(); 5075 bool isVolatile = LD->isVolatile(); 5076 5077 if (ExtType == ISD::NON_EXTLOAD) { 5078 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5079 isVolatile, Alignment); 5080 if (VT == MVT::f32 || VT == MVT::f64) { 5081 // f32->i32 or f64->i64 one to one expansion. 5082 // Remember that we legalized the chain. 5083 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5084 // Recursively expand the new load. 5085 if (getTypeAction(NVT) == Expand) 5086 ExpandOp(Lo, Lo, Hi); 5087 break; 5088 } 5089 5090 // Increment the pointer to the other half. 5091 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5092 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5093 getIntPtrConstant(IncrementSize)); 5094 SVOffset += IncrementSize; 5095 if (Alignment > IncrementSize) 5096 Alignment = IncrementSize; 5097 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5098 isVolatile, Alignment); 5099 5100 // Build a factor node to remember that this load is independent of the 5101 // other one. 5102 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5103 Hi.getValue(1)); 5104 5105 // Remember that we legalized the chain. 5106 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5107 if (!TLI.isLittleEndian()) 5108 std::swap(Lo, Hi); 5109 } else { 5110 MVT::ValueType EVT = LD->getLoadedVT(); 5111 5112 if (VT == MVT::f64 && EVT == MVT::f32) { 5113 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5114 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5115 SVOffset, isVolatile, Alignment); 5116 // Remember that we legalized the chain. 5117 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5118 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5119 break; 5120 } 5121 5122 if (EVT == NVT) 5123 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5124 SVOffset, isVolatile, Alignment); 5125 else 5126 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5127 SVOffset, EVT, isVolatile, 5128 Alignment); 5129 5130 // Remember that we legalized the chain. 5131 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5132 5133 if (ExtType == ISD::SEXTLOAD) { 5134 // The high part is obtained by SRA'ing all but one of the bits of the 5135 // lo part. 5136 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5137 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5138 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5139 } else if (ExtType == ISD::ZEXTLOAD) { 5140 // The high part is just a zero. 5141 Hi = DAG.getConstant(0, NVT); 5142 } else /* if (ExtType == ISD::EXTLOAD) */ { 5143 // The high part is undefined. 5144 Hi = DAG.getNode(ISD::UNDEF, NVT); 5145 } 5146 } 5147 break; 5148 } 5149 case ISD::AND: 5150 case ISD::OR: 5151 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5152 SDOperand LL, LH, RL, RH; 5153 ExpandOp(Node->getOperand(0), LL, LH); 5154 ExpandOp(Node->getOperand(1), RL, RH); 5155 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5156 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5157 break; 5158 } 5159 case ISD::SELECT: { 5160 SDOperand LL, LH, RL, RH; 5161 ExpandOp(Node->getOperand(1), LL, LH); 5162 ExpandOp(Node->getOperand(2), RL, RH); 5163 if (getTypeAction(NVT) == Expand) 5164 NVT = TLI.getTypeToExpandTo(NVT); 5165 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5166 if (VT != MVT::f32) 5167 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5168 break; 5169 } 5170 case ISD::SELECT_CC: { 5171 SDOperand TL, TH, FL, FH; 5172 ExpandOp(Node->getOperand(2), TL, TH); 5173 ExpandOp(Node->getOperand(3), FL, FH); 5174 if (getTypeAction(NVT) == Expand) 5175 NVT = TLI.getTypeToExpandTo(NVT); 5176 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5177 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5178 if (VT != MVT::f32) 5179 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5180 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5181 break; 5182 } 5183 case ISD::ANY_EXTEND: 5184 // The low part is any extension of the input (which degenerates to a copy). 5185 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5186 // The high part is undefined. 5187 Hi = DAG.getNode(ISD::UNDEF, NVT); 5188 break; 5189 case ISD::SIGN_EXTEND: { 5190 // The low part is just a sign extension of the input (which degenerates to 5191 // a copy). 5192 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5193 5194 // The high part is obtained by SRA'ing all but one of the bits of the lo 5195 // part. 5196 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5197 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5198 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5199 break; 5200 } 5201 case ISD::ZERO_EXTEND: 5202 // The low part is just a zero extension of the input (which degenerates to 5203 // a copy). 5204 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5205 5206 // The high part is just a zero. 5207 Hi = DAG.getConstant(0, NVT); 5208 break; 5209 5210 case ISD::TRUNCATE: { 5211 // The input value must be larger than this value. Expand *it*. 5212 SDOperand NewLo; 5213 ExpandOp(Node->getOperand(0), NewLo, Hi); 5214 5215 // The low part is now either the right size, or it is closer. If not the 5216 // right size, make an illegal truncate so we recursively expand it. 5217 if (NewLo.getValueType() != Node->getValueType(0)) 5218 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5219 ExpandOp(NewLo, Lo, Hi); 5220 break; 5221 } 5222 5223 case ISD::BIT_CONVERT: { 5224 SDOperand Tmp; 5225 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5226 // If the target wants to, allow it to lower this itself. 5227 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5228 case Expand: assert(0 && "cannot expand FP!"); 5229 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5230 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5231 } 5232 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5233 } 5234 5235 // f32 / f64 must be expanded to i32 / i64. 5236 if (VT == MVT::f32 || VT == MVT::f64) { 5237 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5238 if (getTypeAction(NVT) == Expand) 5239 ExpandOp(Lo, Lo, Hi); 5240 break; 5241 } 5242 5243 // If source operand will be expanded to the same type as VT, i.e. 5244 // i64 <- f64, i32 <- f32, expand the source operand instead. 5245 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5246 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5247 ExpandOp(Node->getOperand(0), Lo, Hi); 5248 break; 5249 } 5250 5251 // Turn this into a load/store pair by default. 5252 if (Tmp.Val == 0) 5253 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5254 5255 ExpandOp(Tmp, Lo, Hi); 5256 break; 5257 } 5258 5259 case ISD::READCYCLECOUNTER: 5260 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5261 TargetLowering::Custom && 5262 "Must custom expand ReadCycleCounter"); 5263 Lo = TLI.LowerOperation(Op, DAG); 5264 assert(Lo.Val && "Node must be custom expanded!"); 5265 Hi = Lo.getValue(1); 5266 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5267 LegalizeOp(Lo.getValue(2))); 5268 break; 5269 5270 // These operators cannot be expanded directly, emit them as calls to 5271 // library functions. 5272 case ISD::FP_TO_SINT: { 5273 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5274 SDOperand Op; 5275 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5276 case Expand: assert(0 && "cannot expand FP!"); 5277 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5278 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5279 } 5280 5281 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5282 5283 // Now that the custom expander is done, expand the result, which is still 5284 // VT. 5285 if (Op.Val) { 5286 ExpandOp(Op, Lo, Hi); 5287 break; 5288 } 5289 } 5290 5291 RTLIB::Libcall LC; 5292 if (Node->getOperand(0).getValueType() == MVT::f32) 5293 LC = RTLIB::FPTOSINT_F32_I64; 5294 else 5295 LC = RTLIB::FPTOSINT_F64_I64; 5296 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5297 false/*sign irrelevant*/, Hi); 5298 break; 5299 } 5300 5301 case ISD::FP_TO_UINT: { 5302 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5303 SDOperand Op; 5304 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5305 case Expand: assert(0 && "cannot expand FP!"); 5306 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5307 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5308 } 5309 5310 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5311 5312 // Now that the custom expander is done, expand the result. 5313 if (Op.Val) { 5314 ExpandOp(Op, Lo, Hi); 5315 break; 5316 } 5317 } 5318 5319 RTLIB::Libcall LC; 5320 if (Node->getOperand(0).getValueType() == MVT::f32) 5321 LC = RTLIB::FPTOUINT_F32_I64; 5322 else 5323 LC = RTLIB::FPTOUINT_F64_I64; 5324 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5325 false/*sign irrelevant*/, Hi); 5326 break; 5327 } 5328 5329 case ISD::SHL: { 5330 // If the target wants custom lowering, do so. 5331 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5332 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5333 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5334 Op = TLI.LowerOperation(Op, DAG); 5335 if (Op.Val) { 5336 // Now that the custom expander is done, expand the result, which is 5337 // still VT. 5338 ExpandOp(Op, Lo, Hi); 5339 break; 5340 } 5341 } 5342 5343 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5344 // this X << 1 as X+X. 5345 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5346 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5347 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5348 SDOperand LoOps[2], HiOps[3]; 5349 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5350 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5351 LoOps[1] = LoOps[0]; 5352 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5353 5354 HiOps[1] = HiOps[0]; 5355 HiOps[2] = Lo.getValue(1); 5356 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5357 break; 5358 } 5359 } 5360 5361 // If we can emit an efficient shift operation, do so now. 5362 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5363 break; 5364 5365 // If this target supports SHL_PARTS, use it. 5366 TargetLowering::LegalizeAction Action = 5367 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5368 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5369 Action == TargetLowering::Custom) { 5370 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5371 break; 5372 } 5373 5374 // Otherwise, emit a libcall. 5375 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5376 false/*left shift=unsigned*/, Hi); 5377 break; 5378 } 5379 5380 case ISD::SRA: { 5381 // If the target wants custom lowering, do so. 5382 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5383 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5384 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5385 Op = TLI.LowerOperation(Op, DAG); 5386 if (Op.Val) { 5387 // Now that the custom expander is done, expand the result, which is 5388 // still VT. 5389 ExpandOp(Op, Lo, Hi); 5390 break; 5391 } 5392 } 5393 5394 // If we can emit an efficient shift operation, do so now. 5395 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5396 break; 5397 5398 // If this target supports SRA_PARTS, use it. 5399 TargetLowering::LegalizeAction Action = 5400 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5401 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5402 Action == TargetLowering::Custom) { 5403 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5404 break; 5405 } 5406 5407 // Otherwise, emit a libcall. 5408 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5409 true/*ashr is signed*/, Hi); 5410 break; 5411 } 5412 5413 case ISD::SRL: { 5414 // If the target wants custom lowering, do so. 5415 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5416 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5417 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5418 Op = TLI.LowerOperation(Op, DAG); 5419 if (Op.Val) { 5420 // Now that the custom expander is done, expand the result, which is 5421 // still VT. 5422 ExpandOp(Op, Lo, Hi); 5423 break; 5424 } 5425 } 5426 5427 // If we can emit an efficient shift operation, do so now. 5428 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5429 break; 5430 5431 // If this target supports SRL_PARTS, use it. 5432 TargetLowering::LegalizeAction Action = 5433 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5434 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5435 Action == TargetLowering::Custom) { 5436 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5437 break; 5438 } 5439 5440 // Otherwise, emit a libcall. 5441 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5442 false/*lshr is unsigned*/, Hi); 5443 break; 5444 } 5445 5446 case ISD::ADD: 5447 case ISD::SUB: { 5448 // If the target wants to custom expand this, let them. 5449 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5450 TargetLowering::Custom) { 5451 Op = TLI.LowerOperation(Op, DAG); 5452 if (Op.Val) { 5453 ExpandOp(Op, Lo, Hi); 5454 break; 5455 } 5456 } 5457 5458 // Expand the subcomponents. 5459 SDOperand LHSL, LHSH, RHSL, RHSH; 5460 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5461 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5462 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5463 SDOperand LoOps[2], HiOps[3]; 5464 LoOps[0] = LHSL; 5465 LoOps[1] = RHSL; 5466 HiOps[0] = LHSH; 5467 HiOps[1] = RHSH; 5468 if (Node->getOpcode() == ISD::ADD) { 5469 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5470 HiOps[2] = Lo.getValue(1); 5471 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5472 } else { 5473 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5474 HiOps[2] = Lo.getValue(1); 5475 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5476 } 5477 break; 5478 } 5479 5480 case ISD::ADDC: 5481 case ISD::SUBC: { 5482 // Expand the subcomponents. 5483 SDOperand LHSL, LHSH, RHSL, RHSH; 5484 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5485 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5486 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5487 SDOperand LoOps[2] = { LHSL, RHSL }; 5488 SDOperand HiOps[3] = { LHSH, RHSH }; 5489 5490 if (Node->getOpcode() == ISD::ADDC) { 5491 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5492 HiOps[2] = Lo.getValue(1); 5493 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5494 } else { 5495 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5496 HiOps[2] = Lo.getValue(1); 5497 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5498 } 5499 // Remember that we legalized the flag. 5500 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5501 break; 5502 } 5503 case ISD::ADDE: 5504 case ISD::SUBE: { 5505 // Expand the subcomponents. 5506 SDOperand LHSL, LHSH, RHSL, RHSH; 5507 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5508 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5509 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5510 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5511 SDOperand HiOps[3] = { LHSH, RHSH }; 5512 5513 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 5514 HiOps[2] = Lo.getValue(1); 5515 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 5516 5517 // Remember that we legalized the flag. 5518 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5519 break; 5520 } 5521 case ISD::MUL: { 5522 // If the target wants to custom expand this, let them. 5523 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5524 SDOperand New = TLI.LowerOperation(Op, DAG); 5525 if (New.Val) { 5526 ExpandOp(New, Lo, Hi); 5527 break; 5528 } 5529 } 5530 5531 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5532 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5533 if (HasMULHS || HasMULHU) { 5534 SDOperand LL, LH, RL, RH; 5535 ExpandOp(Node->getOperand(0), LL, LH); 5536 ExpandOp(Node->getOperand(1), RL, RH); 5537 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 5538 // FIXME: Move this to the dag combiner. 5539 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 5540 // extended the sign bit of the low half through the upper half, and if so 5541 // emit a MULHS instead of the alternate sequence that is valid for any 5542 // i64 x i64 multiply. 5543 if (HasMULHS && 5544 // is RH an extension of the sign bit of RL? 5545 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 5546 RH.getOperand(1).getOpcode() == ISD::Constant && 5547 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 5548 // is LH an extension of the sign bit of LL? 5549 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 5550 LH.getOperand(1).getOpcode() == ISD::Constant && 5551 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 5552 // Low part: 5553 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5554 // High part: 5555 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5556 break; 5557 } else if (HasMULHU) { 5558 // Low part: 5559 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5560 5561 // High part: 5562 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5563 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5564 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5565 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5566 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5567 break; 5568 } 5569 } 5570 5571 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5572 false/*sign irrelevant*/, Hi); 5573 break; 5574 } 5575 case ISD::SDIV: 5576 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5577 break; 5578 case ISD::UDIV: 5579 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5580 break; 5581 case ISD::SREM: 5582 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5583 break; 5584 case ISD::UREM: 5585 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5586 break; 5587 5588 case ISD::FADD: 5589 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5590 ? RTLIB::ADD_F32 : RTLIB::ADD_F64), 5591 Node, false, Hi); 5592 break; 5593 case ISD::FSUB: 5594 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5595 ? RTLIB::SUB_F32 : RTLIB::SUB_F64), 5596 Node, false, Hi); 5597 break; 5598 case ISD::FMUL: 5599 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5600 ? RTLIB::MUL_F32 : RTLIB::MUL_F64), 5601 Node, false, Hi); 5602 break; 5603 case ISD::FDIV: 5604 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5605 ? RTLIB::DIV_F32 : RTLIB::DIV_F64), 5606 Node, false, Hi); 5607 break; 5608 case ISD::FP_EXTEND: 5609 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5610 break; 5611 case ISD::FP_ROUND: 5612 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5613 break; 5614 case ISD::FPOWI: 5615 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5616 ? RTLIB::POWI_F32 : RTLIB::POWI_F64), 5617 Node, false, Hi); 5618 break; 5619 case ISD::FSQRT: 5620 case ISD::FSIN: 5621 case ISD::FCOS: { 5622 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5623 switch(Node->getOpcode()) { 5624 case ISD::FSQRT: 5625 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 5626 break; 5627 case ISD::FSIN: 5628 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 5629 break; 5630 case ISD::FCOS: 5631 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 5632 break; 5633 default: assert(0 && "Unreachable!"); 5634 } 5635 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 5636 break; 5637 } 5638 case ISD::FABS: { 5639 SDOperand Mask = (VT == MVT::f64) 5640 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 5641 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 5642 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5643 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5644 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 5645 if (getTypeAction(NVT) == Expand) 5646 ExpandOp(Lo, Lo, Hi); 5647 break; 5648 } 5649 case ISD::FNEG: { 5650 SDOperand Mask = (VT == MVT::f64) 5651 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 5652 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 5653 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5654 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5655 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 5656 if (getTypeAction(NVT) == Expand) 5657 ExpandOp(Lo, Lo, Hi); 5658 break; 5659 } 5660 case ISD::FCOPYSIGN: { 5661 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 5662 if (getTypeAction(NVT) == Expand) 5663 ExpandOp(Lo, Lo, Hi); 5664 break; 5665 } 5666 case ISD::SINT_TO_FP: 5667 case ISD::UINT_TO_FP: { 5668 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 5669 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 5670 RTLIB::Libcall LC; 5671 if (Node->getOperand(0).getValueType() == MVT::i64) { 5672 if (VT == MVT::f32) 5673 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 5674 else 5675 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 5676 } else { 5677 if (VT == MVT::f32) 5678 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5679 else 5680 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5681 } 5682 5683 // Promote the operand if needed. 5684 if (getTypeAction(SrcVT) == Promote) { 5685 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 5686 Tmp = isSigned 5687 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 5688 DAG.getValueType(SrcVT)) 5689 : DAG.getZeroExtendInReg(Tmp, SrcVT); 5690 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 5691 } 5692 5693 const char *LibCall = TLI.getLibcallName(LC); 5694 if (LibCall) 5695 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 5696 else { 5697 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 5698 Node->getOperand(0)); 5699 if (getTypeAction(Lo.getValueType()) == Expand) 5700 ExpandOp(Lo, Lo, Hi); 5701 } 5702 break; 5703 } 5704 } 5705 5706 // Make sure the resultant values have been legalized themselves, unless this 5707 // is a type that requires multi-step expansion. 5708 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 5709 Lo = LegalizeOp(Lo); 5710 if (Hi.Val) 5711 // Don't legalize the high part if it is expanded to a single node. 5712 Hi = LegalizeOp(Hi); 5713 } 5714 5715 // Remember in a map if the values will be reused later. 5716 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 5717 assert(isNew && "Value already expanded?!?"); 5718} 5719 5720/// SplitVectorOp - Given an operand of vector type, break it down into 5721/// two smaller values, still of vector type. 5722void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 5723 SDOperand &Hi) { 5724 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 5725 SDNode *Node = Op.Val; 5726 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0)); 5727 assert(NumElements > 1 && "Cannot split a single element vector!"); 5728 unsigned NewNumElts = NumElements/2; 5729 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0)); 5730 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts); 5731 5732 // See if we already split it. 5733 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5734 = SplitNodes.find(Op); 5735 if (I != SplitNodes.end()) { 5736 Lo = I->second.first; 5737 Hi = I->second.second; 5738 return; 5739 } 5740 5741 switch (Node->getOpcode()) { 5742 default: 5743#ifndef NDEBUG 5744 Node->dump(&DAG); 5745#endif 5746 assert(0 && "Unhandled operation in SplitVectorOp!"); 5747 case ISD::BUILD_PAIR: 5748 Lo = Node->getOperand(0); 5749 Hi = Node->getOperand(1); 5750 break; 5751 case ISD::BUILD_VECTOR: { 5752 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5753 Node->op_begin()+NewNumElts); 5754 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size()); 5755 5756 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 5757 Node->op_end()); 5758 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size()); 5759 break; 5760 } 5761 case ISD::CONCAT_VECTORS: { 5762 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 5763 if (NewNumSubvectors == 1) { 5764 Lo = Node->getOperand(0); 5765 Hi = Node->getOperand(1); 5766 } else { 5767 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5768 Node->op_begin()+NewNumSubvectors); 5769 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size()); 5770 5771 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 5772 Node->op_end()); 5773 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size()); 5774 } 5775 break; 5776 } 5777 case ISD::ADD: 5778 case ISD::SUB: 5779 case ISD::MUL: 5780 case ISD::FADD: 5781 case ISD::FSUB: 5782 case ISD::FMUL: 5783 case ISD::SDIV: 5784 case ISD::UDIV: 5785 case ISD::FDIV: 5786 case ISD::AND: 5787 case ISD::OR: 5788 case ISD::XOR: { 5789 SDOperand LL, LH, RL, RH; 5790 SplitVectorOp(Node->getOperand(0), LL, LH); 5791 SplitVectorOp(Node->getOperand(1), RL, RH); 5792 5793 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL); 5794 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH); 5795 break; 5796 } 5797 case ISD::LOAD: { 5798 LoadSDNode *LD = cast<LoadSDNode>(Node); 5799 SDOperand Ch = LD->getChain(); 5800 SDOperand Ptr = LD->getBasePtr(); 5801 const Value *SV = LD->getSrcValue(); 5802 int SVOffset = LD->getSrcValueOffset(); 5803 unsigned Alignment = LD->getAlignment(); 5804 bool isVolatile = LD->isVolatile(); 5805 5806 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 5807 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8; 5808 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5809 getIntPtrConstant(IncrementSize)); 5810 SVOffset += IncrementSize; 5811 if (Alignment > IncrementSize) 5812 Alignment = IncrementSize; 5813 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 5814 5815 // Build a factor node to remember that this load is independent of the 5816 // other one. 5817 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5818 Hi.getValue(1)); 5819 5820 // Remember that we legalized the chain. 5821 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5822 break; 5823 } 5824 case ISD::BIT_CONVERT: { 5825 // We know the result is a vector. The input may be either a vector or a 5826 // scalar value. 5827 SDOperand InOp = Node->getOperand(0); 5828 if (!MVT::isVector(InOp.getValueType()) || 5829 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 5830 // The input is a scalar or single-element vector. 5831 // Lower to a store/load so that it can be split. 5832 // FIXME: this could be improved probably. 5833 SDOperand Ptr = CreateStackTemporary(InOp.getValueType()); 5834 5835 SDOperand St = DAG.getStore(DAG.getEntryNode(), 5836 InOp, Ptr, NULL, 0); 5837 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 5838 } 5839 // Split the vector and convert each of the pieces now. 5840 SplitVectorOp(InOp, Lo, Hi); 5841 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo); 5842 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi); 5843 break; 5844 } 5845 } 5846 5847 // Remember in a map if the values will be reused later. 5848 bool isNew = 5849 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 5850 assert(isNew && "Value already split?!?"); 5851} 5852 5853 5854/// ScalarizeVectorOp - Given an operand of single-element vector type 5855/// (e.g. v1f32), convert it into the equivalent operation that returns a 5856/// scalar (e.g. f32) value. 5857SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 5858 assert(MVT::isVector(Op.getValueType()) && 5859 "Bad ScalarizeVectorOp invocation!"); 5860 SDNode *Node = Op.Val; 5861 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 5862 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 5863 5864 // See if we already scalarized it. 5865 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 5866 if (I != ScalarizedNodes.end()) return I->second; 5867 5868 SDOperand Result; 5869 switch (Node->getOpcode()) { 5870 default: 5871#ifndef NDEBUG 5872 Node->dump(&DAG); cerr << "\n"; 5873#endif 5874 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 5875 case ISD::ADD: 5876 case ISD::FADD: 5877 case ISD::SUB: 5878 case ISD::FSUB: 5879 case ISD::MUL: 5880 case ISD::FMUL: 5881 case ISD::SDIV: 5882 case ISD::UDIV: 5883 case ISD::FDIV: 5884 case ISD::SREM: 5885 case ISD::UREM: 5886 case ISD::FREM: 5887 case ISD::AND: 5888 case ISD::OR: 5889 case ISD::XOR: 5890 Result = DAG.getNode(Node->getOpcode(), 5891 NewVT, 5892 ScalarizeVectorOp(Node->getOperand(0)), 5893 ScalarizeVectorOp(Node->getOperand(1))); 5894 break; 5895 case ISD::FNEG: 5896 case ISD::FABS: 5897 case ISD::FSQRT: 5898 case ISD::FSIN: 5899 case ISD::FCOS: 5900 Result = DAG.getNode(Node->getOpcode(), 5901 NewVT, 5902 ScalarizeVectorOp(Node->getOperand(0))); 5903 break; 5904 case ISD::LOAD: { 5905 LoadSDNode *LD = cast<LoadSDNode>(Node); 5906 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 5907 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 5908 5909 const Value *SV = LD->getSrcValue(); 5910 int SVOffset = LD->getSrcValueOffset(); 5911 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 5912 LD->isVolatile(), LD->getAlignment()); 5913 5914 // Remember that we legalized the chain. 5915 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 5916 break; 5917 } 5918 case ISD::BUILD_VECTOR: 5919 Result = Node->getOperand(0); 5920 break; 5921 case ISD::INSERT_VECTOR_ELT: 5922 // Returning the inserted scalar element. 5923 Result = Node->getOperand(1); 5924 break; 5925 case ISD::CONCAT_VECTORS: 5926 assert(Node->getOperand(0).getValueType() == NewVT && 5927 "Concat of non-legal vectors not yet supported!"); 5928 Result = Node->getOperand(0); 5929 break; 5930 case ISD::VECTOR_SHUFFLE: { 5931 // Figure out if the scalar is the LHS or RHS and return it. 5932 SDOperand EltNum = Node->getOperand(2).getOperand(0); 5933 if (cast<ConstantSDNode>(EltNum)->getValue()) 5934 Result = ScalarizeVectorOp(Node->getOperand(1)); 5935 else 5936 Result = ScalarizeVectorOp(Node->getOperand(0)); 5937 break; 5938 } 5939 case ISD::EXTRACT_SUBVECTOR: 5940 Result = Node->getOperand(0); 5941 assert(Result.getValueType() == NewVT); 5942 break; 5943 case ISD::BIT_CONVERT: 5944 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 5945 break; 5946 case ISD::SELECT: 5947 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 5948 ScalarizeVectorOp(Op.getOperand(1)), 5949 ScalarizeVectorOp(Op.getOperand(2))); 5950 break; 5951 } 5952 5953 if (TLI.isTypeLegal(NewVT)) 5954 Result = LegalizeOp(Result); 5955 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 5956 assert(isNew && "Value already scalarized?"); 5957 return Result; 5958} 5959 5960 5961// SelectionDAG::Legalize - This is the entry point for the file. 5962// 5963void SelectionDAG::Legalize() { 5964 if (ViewLegalizeDAGs) viewGraph(); 5965 5966 /// run - This is the main entry point to this class. 5967 /// 5968 SelectionDAGLegalize(*this).LegalizeDAG(); 5969} 5970 5971