LegalizeDAG.cpp revision 9ab9ee8209c313713a54db2d9451751d8cfb9e2a
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38#ifndef NDEBUG 39static cl::opt<bool> 40ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 41 cl::desc("Pop up a window to show dags before legalize")); 42#else 43static const bool ViewLegalizeDAGs = 0; 44#endif 45 46//===----------------------------------------------------------------------===// 47/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 48/// hacks on it until the target machine can handle it. This involves 49/// eliminating value sizes the machine cannot handle (promoting small sizes to 50/// large sizes or splitting up large values into small values) as well as 51/// eliminating operations the machine cannot handle. 52/// 53/// This code also does a small amount of optimization and recognition of idioms 54/// as part of its processing. For example, if a target does not support a 55/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 56/// will attempt merge setcc and brc instructions into brcc's. 57/// 58namespace { 59class VISIBILITY_HIDDEN SelectionDAGLegalize { 60 TargetLowering &TLI; 61 SelectionDAG &DAG; 62 63 // Libcall insertion helpers. 64 65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 66 /// legalized. We use this to ensure that calls are properly serialized 67 /// against each other, including inserted libcalls. 68 SDOperand LastCALLSEQ_END; 69 70 /// IsLegalizingCall - This member is used *only* for purposes of providing 71 /// helpful assertions that a libcall isn't created while another call is 72 /// being legalized (which could lead to non-serialized call sequences). 73 bool IsLegalizingCall; 74 75 enum LegalizeAction { 76 Legal, // The target natively supports this operation. 77 Promote, // This operation should be executed in a larger type. 78 Expand // Try to expand this to other ops, otherwise use a libcall. 79 }; 80 81 /// ValueTypeActions - This is a bitvector that contains two bits for each 82 /// value type, where the two bits correspond to the LegalizeAction enum. 83 /// This can be queried with "getTypeAction(VT)". 84 TargetLowering::ValueTypeActionImpl ValueTypeActions; 85 86 /// LegalizedNodes - For nodes that are of legal width, and that have more 87 /// than one use, this map indicates what regularized operand to use. This 88 /// allows us to avoid legalizing the same thing more than once. 89 DenseMap<SDOperand, SDOperand> LegalizedNodes; 90 91 /// PromotedNodes - For nodes that are below legal width, and that have more 92 /// than one use, this map indicates what promoted value to use. This allows 93 /// us to avoid promoting the same thing more than once. 94 DenseMap<SDOperand, SDOperand> PromotedNodes; 95 96 /// ExpandedNodes - For nodes that need to be expanded this map indicates 97 /// which which operands are the expanded version of the input. This allows 98 /// us to avoid expanding the same node more than once. 99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 100 101 /// SplitNodes - For vector nodes that need to be split, this map indicates 102 /// which which operands are the split version of the input. This allows us 103 /// to avoid splitting the same node more than once. 104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 105 106 /// ScalarizedNodes - For nodes that need to be converted from vector types to 107 /// scalar types, this contains the mapping of ones we have already 108 /// processed to the result. 109 std::map<SDOperand, SDOperand> ScalarizedNodes; 110 111 void AddLegalizedOperand(SDOperand From, SDOperand To) { 112 LegalizedNodes.insert(std::make_pair(From, To)); 113 // If someone requests legalization of the new node, return itself. 114 if (From != To) 115 LegalizedNodes.insert(std::make_pair(To, To)); 116 } 117 void AddPromotedOperand(SDOperand From, SDOperand To) { 118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 119 assert(isNew && "Got into the map somehow?"); 120 // If someone requests legalization of the new node, return itself. 121 LegalizedNodes.insert(std::make_pair(To, To)); 122 } 123 124public: 125 126 SelectionDAGLegalize(SelectionDAG &DAG); 127 128 /// getTypeAction - Return how we should legalize values of this type, either 129 /// it is already legal or we need to expand it into multiple registers of 130 /// smaller integer type, or we need to promote it to a larger type. 131 LegalizeAction getTypeAction(MVT::ValueType VT) const { 132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 133 } 134 135 /// isTypeLegal - Return true if this type is legal on this target. 136 /// 137 bool isTypeLegal(MVT::ValueType VT) const { 138 return getTypeAction(VT) == Legal; 139 } 140 141 void LegalizeDAG(); 142 143private: 144 /// HandleOp - Legalize, Promote, or Expand the specified operand as 145 /// appropriate for its type. 146 void HandleOp(SDOperand Op); 147 148 /// LegalizeOp - We know that the specified value has a legal type. 149 /// Recursively ensure that the operands have legal types, then return the 150 /// result. 151 SDOperand LegalizeOp(SDOperand O); 152 153 /// UnrollVectorOp - We know that the given vector has a legal type, however 154 /// the operation it performs is not legal and is an operation that we have 155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 156 /// operating on each element individually. 157 SDOperand UnrollVectorOp(SDOperand O); 158 159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 161 /// is necessary to spill the vector being inserted into to memory, perform 162 /// the insert there, and then read the result back. 163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, 164 SDOperand Idx); 165 166 /// PromoteOp - Given an operation that produces a value in an invalid type, 167 /// promote it to compute the value into a larger type. The produced value 168 /// will have the correct bits for the low portion of the register, but no 169 /// guarantee is made about the top bits: it may be zero, sign-extended, or 170 /// garbage. 171 SDOperand PromoteOp(SDOperand O); 172 173 /// ExpandOp - Expand the specified SDOperand into its two component pieces 174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 175 /// the LegalizeNodes map is filled in for any results that are not expanded, 176 /// the ExpandedNodes map is filled in for any results that are expanded, and 177 /// the Lo/Hi values are returned. This applies to integer types and Vector 178 /// types. 179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 180 181 /// SplitVectorOp - Given an operand of vector type, break it down into 182 /// two smaller values. 183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 184 185 /// ScalarizeVectorOp - Given an operand of single-element vector type 186 /// (e.g. v1f32), convert it into the equivalent operation that returns a 187 /// scalar (e.g. f32) value. 188 SDOperand ScalarizeVectorOp(SDOperand O); 189 190 /// isShuffleLegal - Return true if a vector shuffle is legal with the 191 /// specified mask and type. Targets can specify exactly which masks they 192 /// support and the code generator is tasked with not creating illegal masks. 193 /// 194 /// Note that this will also return true for shuffles that are promoted to a 195 /// different type. 196 /// 197 /// If this is a legal shuffle, this method returns the (possibly promoted) 198 /// build_vector Mask. If it's not a legal shuffle, it returns null. 199 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 200 201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 203 204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 205 206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 207 SDOperand &Hi); 208 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 209 SDOperand Source); 210 211 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, 212 MVT::ValueType DestVT); 213 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 214 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 215 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 216 SDOperand LegalOp, 217 MVT::ValueType DestVT); 218 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 219 bool isSigned); 220 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 221 bool isSigned); 222 223 SDOperand ExpandBSWAP(SDOperand Op); 224 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 225 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 226 SDOperand &Lo, SDOperand &Hi); 227 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 228 SDOperand &Lo, SDOperand &Hi); 229 230 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 231 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 232}; 233} 234 235/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 236/// specified mask and type. Targets can specify exactly which masks they 237/// support and the code generator is tasked with not creating illegal masks. 238/// 239/// Note that this will also return true for shuffles that are promoted to a 240/// different type. 241SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 242 SDOperand Mask) const { 243 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 244 default: return 0; 245 case TargetLowering::Legal: 246 case TargetLowering::Custom: 247 break; 248 case TargetLowering::Promote: { 249 // If this is promoted to a different type, convert the shuffle mask and 250 // ask if it is legal in the promoted type! 251 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 252 253 // If we changed # elements, change the shuffle mask. 254 unsigned NumEltsGrowth = 255 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 256 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 257 if (NumEltsGrowth > 1) { 258 // Renumber the elements. 259 SmallVector<SDOperand, 8> Ops; 260 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 261 SDOperand InOp = Mask.getOperand(i); 262 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 263 if (InOp.getOpcode() == ISD::UNDEF) 264 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 265 else { 266 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 267 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 268 } 269 } 270 } 271 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 272 } 273 VT = NVT; 274 break; 275 } 276 } 277 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 278} 279 280SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 281 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 282 ValueTypeActions(TLI.getValueTypeActions()) { 283 assert(MVT::LAST_VALUETYPE <= 32 && 284 "Too many value types for ValueTypeActions to hold!"); 285} 286 287/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 288/// contains all of a nodes operands before it contains the node. 289static void ComputeTopDownOrdering(SelectionDAG &DAG, 290 SmallVector<SDNode*, 64> &Order) { 291 292 DenseMap<SDNode*, unsigned> Visited; 293 std::vector<SDNode*> Worklist; 294 Worklist.reserve(128); 295 296 // Compute ordering from all of the leaves in the graphs, those (like the 297 // entry node) that have no operands. 298 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 299 E = DAG.allnodes_end(); I != E; ++I) { 300 if (I->getNumOperands() == 0) { 301 Visited[I] = 0 - 1U; 302 Worklist.push_back(I); 303 } 304 } 305 306 while (!Worklist.empty()) { 307 SDNode *N = Worklist.back(); 308 Worklist.pop_back(); 309 310 if (++Visited[N] != N->getNumOperands()) 311 continue; // Haven't visited all operands yet 312 313 Order.push_back(N); 314 315 // Now that we have N in, add anything that uses it if all of their operands 316 // are now done. 317 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 318 UI != E; ++UI) 319 Worklist.push_back(UI->getUser()); 320 } 321 322 assert(Order.size() == Visited.size() && 323 Order.size() == 324 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 325 "Error: DAG is cyclic!"); 326} 327 328 329void SelectionDAGLegalize::LegalizeDAG() { 330 LastCALLSEQ_END = DAG.getEntryNode(); 331 IsLegalizingCall = false; 332 333 // The legalize process is inherently a bottom-up recursive process (users 334 // legalize their uses before themselves). Given infinite stack space, we 335 // could just start legalizing on the root and traverse the whole graph. In 336 // practice however, this causes us to run out of stack space on large basic 337 // blocks. To avoid this problem, compute an ordering of the nodes where each 338 // node is only legalized after all of its operands are legalized. 339 SmallVector<SDNode*, 64> Order; 340 ComputeTopDownOrdering(DAG, Order); 341 342 for (unsigned i = 0, e = Order.size(); i != e; ++i) 343 HandleOp(SDOperand(Order[i], 0)); 344 345 // Finally, it's possible the root changed. Get the new root. 346 SDOperand OldRoot = DAG.getRoot(); 347 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 348 DAG.setRoot(LegalizedNodes[OldRoot]); 349 350 ExpandedNodes.clear(); 351 LegalizedNodes.clear(); 352 PromotedNodes.clear(); 353 SplitNodes.clear(); 354 ScalarizedNodes.clear(); 355 356 // Remove dead nodes now. 357 DAG.RemoveDeadNodes(); 358} 359 360 361/// FindCallEndFromCallStart - Given a chained node that is part of a call 362/// sequence, find the CALLSEQ_END node that terminates the call sequence. 363static SDNode *FindCallEndFromCallStart(SDNode *Node) { 364 if (Node->getOpcode() == ISD::CALLSEQ_END) 365 return Node; 366 if (Node->use_empty()) 367 return 0; // No CallSeqEnd 368 369 // The chain is usually at the end. 370 SDOperand TheChain(Node, Node->getNumValues()-1); 371 if (TheChain.getValueType() != MVT::Other) { 372 // Sometimes it's at the beginning. 373 TheChain = SDOperand(Node, 0); 374 if (TheChain.getValueType() != MVT::Other) { 375 // Otherwise, hunt for it. 376 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 377 if (Node->getValueType(i) == MVT::Other) { 378 TheChain = SDOperand(Node, i); 379 break; 380 } 381 382 // Otherwise, we walked into a node without a chain. 383 if (TheChain.getValueType() != MVT::Other) 384 return 0; 385 } 386 } 387 388 for (SDNode::use_iterator UI = Node->use_begin(), 389 E = Node->use_end(); UI != E; ++UI) { 390 391 // Make sure to only follow users of our token chain. 392 SDNode *User = UI->getUser(); 393 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 394 if (User->getOperand(i) == TheChain) 395 if (SDNode *Result = FindCallEndFromCallStart(User)) 396 return Result; 397 } 398 return 0; 399} 400 401/// FindCallStartFromCallEnd - Given a chained node that is part of a call 402/// sequence, find the CALLSEQ_START node that initiates the call sequence. 403static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 404 assert(Node && "Didn't find callseq_start for a call??"); 405 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 406 407 assert(Node->getOperand(0).getValueType() == MVT::Other && 408 "Node doesn't have a token chain argument!"); 409 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 410} 411 412/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 413/// see if any uses can reach Dest. If no dest operands can get to dest, 414/// legalize them, legalize ourself, and return false, otherwise, return true. 415/// 416/// Keep track of the nodes we fine that actually do lead to Dest in 417/// NodesLeadingTo. This avoids retraversing them exponential number of times. 418/// 419bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 420 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 421 if (N == Dest) return true; // N certainly leads to Dest :) 422 423 // If we've already processed this node and it does lead to Dest, there is no 424 // need to reprocess it. 425 if (NodesLeadingTo.count(N)) return true; 426 427 // If the first result of this node has been already legalized, then it cannot 428 // reach N. 429 switch (getTypeAction(N->getValueType(0))) { 430 case Legal: 431 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 432 break; 433 case Promote: 434 if (PromotedNodes.count(SDOperand(N, 0))) return false; 435 break; 436 case Expand: 437 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 438 break; 439 } 440 441 // Okay, this node has not already been legalized. Check and legalize all 442 // operands. If none lead to Dest, then we can legalize this node. 443 bool OperandsLeadToDest = false; 444 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 445 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 446 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 447 448 if (OperandsLeadToDest) { 449 NodesLeadingTo.insert(N); 450 return true; 451 } 452 453 // Okay, this node looks safe, legalize it and return false. 454 HandleOp(SDOperand(N, 0)); 455 return false; 456} 457 458/// HandleOp - Legalize, Promote, or Expand the specified operand as 459/// appropriate for its type. 460void SelectionDAGLegalize::HandleOp(SDOperand Op) { 461 MVT::ValueType VT = Op.getValueType(); 462 switch (getTypeAction(VT)) { 463 default: assert(0 && "Bad type action!"); 464 case Legal: (void)LegalizeOp(Op); break; 465 case Promote: (void)PromoteOp(Op); break; 466 case Expand: 467 if (!MVT::isVector(VT)) { 468 // If this is an illegal scalar, expand it into its two component 469 // pieces. 470 SDOperand X, Y; 471 if (Op.getOpcode() == ISD::TargetConstant) 472 break; // Allow illegal target nodes. 473 ExpandOp(Op, X, Y); 474 } else if (MVT::getVectorNumElements(VT) == 1) { 475 // If this is an illegal single element vector, convert it to a 476 // scalar operation. 477 (void)ScalarizeVectorOp(Op); 478 } else { 479 // Otherwise, this is an illegal multiple element vector. 480 // Split it in half and legalize both parts. 481 SDOperand X, Y; 482 SplitVectorOp(Op, X, Y); 483 } 484 break; 485 } 486} 487 488/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 489/// a load from the constant pool. 490static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 491 SelectionDAG &DAG, TargetLowering &TLI) { 492 bool Extend = false; 493 494 // If a FP immediate is precise when represented as a float and if the 495 // target can do an extending load from float to double, we put it into 496 // the constant pool as a float, even if it's is statically typed as a 497 // double. This shrinks FP constants and canonicalizes them for targets where 498 // an FP extending load is the same cost as a normal load (such as on the x87 499 // fp stack or PPC FP unit). 500 MVT::ValueType VT = CFP->getValueType(0); 501 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 502 if (!UseCP) { 503 if (VT!=MVT::f64 && VT!=MVT::f32) 504 assert(0 && "Invalid type expansion"); 505 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 506 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 507 } 508 509 MVT::ValueType OrigVT = VT; 510 MVT::ValueType SVT = VT; 511 while (SVT != MVT::f32) { 512 SVT = (unsigned)SVT - 1; 513 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 514 // Only do this if the target has a native EXTLOAD instruction from 515 // smaller type. 516 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 517 TLI.ShouldShrinkFPConstant(OrigVT)) { 518 const Type *SType = MVT::getTypeForValueType(SVT); 519 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 520 VT = SVT; 521 Extend = true; 522 } 523 } 524 525 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 526 if (Extend) 527 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 528 CPIdx, PseudoSourceValue::getConstantPool(), 529 0, VT); 530 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 531 PseudoSourceValue::getConstantPool(), 0); 532} 533 534 535/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 536/// operations. 537static 538SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 539 SelectionDAG &DAG, TargetLowering &TLI) { 540 MVT::ValueType VT = Node->getValueType(0); 541 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 542 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 543 "fcopysign expansion only supported for f32 and f64"); 544 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 545 546 // First get the sign bit of second operand. 547 SDOperand Mask1 = (SrcVT == MVT::f64) 548 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 549 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 550 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 551 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 552 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 553 // Shift right or sign-extend it if the two operands have different types. 554 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 555 if (SizeDiff > 0) { 556 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 557 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 558 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 559 } else if (SizeDiff < 0) 560 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 561 562 // Clear the sign bit of first operand. 563 SDOperand Mask2 = (VT == MVT::f64) 564 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 565 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 566 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 567 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 568 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 569 570 // Or the value with the sign bit. 571 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 572 return Result; 573} 574 575/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 576static 577SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 578 TargetLowering &TLI) { 579 SDOperand Chain = ST->getChain(); 580 SDOperand Ptr = ST->getBasePtr(); 581 SDOperand Val = ST->getValue(); 582 MVT::ValueType VT = Val.getValueType(); 583 int Alignment = ST->getAlignment(); 584 int SVOffset = ST->getSrcValueOffset(); 585 if (MVT::isFloatingPoint(ST->getMemoryVT()) || 586 MVT::isVector(ST->getMemoryVT())) { 587 // Expand to a bitconvert of the value to the integer type of the 588 // same size, then a (misaligned) int store. 589 MVT::ValueType intVT; 590 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128) 591 intVT = MVT::i128; 592 else if (MVT::is64BitVector(VT) || VT==MVT::f64) 593 intVT = MVT::i64; 594 else if (VT==MVT::f32) 595 intVT = MVT::i32; 596 else 597 assert(0 && "Unaligned store of unsupported type"); 598 599 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 600 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 601 SVOffset, ST->isVolatile(), Alignment); 602 } 603 assert(MVT::isInteger(ST->getMemoryVT()) && 604 !MVT::isVector(ST->getMemoryVT()) && 605 "Unaligned store of unknown type."); 606 // Get the half-size VT 607 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1; 608 int NumBits = MVT::getSizeInBits(NewStoredVT); 609 int IncrementSize = NumBits / 8; 610 611 // Divide the stored value in two parts. 612 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 613 SDOperand Lo = Val; 614 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 615 616 // Store the two parts 617 SDOperand Store1, Store2; 618 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 619 ST->getSrcValue(), SVOffset, NewStoredVT, 620 ST->isVolatile(), Alignment); 621 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 622 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 623 Alignment = MinAlign(Alignment, IncrementSize); 624 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 625 ST->getSrcValue(), SVOffset + IncrementSize, 626 NewStoredVT, ST->isVolatile(), Alignment); 627 628 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 629} 630 631/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 632static 633SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 634 TargetLowering &TLI) { 635 int SVOffset = LD->getSrcValueOffset(); 636 SDOperand Chain = LD->getChain(); 637 SDOperand Ptr = LD->getBasePtr(); 638 MVT::ValueType VT = LD->getValueType(0); 639 MVT::ValueType LoadedVT = LD->getMemoryVT(); 640 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) { 641 // Expand to a (misaligned) integer load of the same size, 642 // then bitconvert to floating point or vector. 643 MVT::ValueType intVT; 644 if (MVT::is128BitVector(LoadedVT) || 645 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 646 intVT = MVT::i128; 647 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64) 648 intVT = MVT::i64; 649 else if (LoadedVT == MVT::f32) 650 intVT = MVT::i32; 651 else 652 assert(0 && "Unaligned load of unsupported type"); 653 654 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 655 SVOffset, LD->isVolatile(), 656 LD->getAlignment()); 657 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 658 if (MVT::isFloatingPoint(VT) && LoadedVT != VT) 659 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 660 661 SDOperand Ops[] = { Result, Chain }; 662 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 663 Ops, 2); 664 } 665 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) && 666 "Unaligned load of unsupported type."); 667 668 // Compute the new VT that is half the size of the old one. This is an 669 // integer MVT. 670 unsigned NumBits = MVT::getSizeInBits(LoadedVT); 671 MVT::ValueType NewLoadedVT; 672 NewLoadedVT = MVT::getIntegerType(NumBits/2); 673 NumBits >>= 1; 674 675 unsigned Alignment = LD->getAlignment(); 676 unsigned IncrementSize = NumBits / 8; 677 ISD::LoadExtType HiExtType = LD->getExtensionType(); 678 679 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 680 if (HiExtType == ISD::NON_EXTLOAD) 681 HiExtType = ISD::ZEXTLOAD; 682 683 // Load the value in two parts 684 SDOperand Lo, Hi; 685 if (TLI.isLittleEndian()) { 686 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 687 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 688 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 689 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 690 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 691 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 692 MinAlign(Alignment, IncrementSize)); 693 } else { 694 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 695 NewLoadedVT,LD->isVolatile(), Alignment); 696 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 697 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 698 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 699 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 700 MinAlign(Alignment, IncrementSize)); 701 } 702 703 // aggregate the two parts 704 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 705 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 706 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 707 708 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 709 Hi.getValue(1)); 710 711 SDOperand Ops[] = { Result, TF }; 712 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 713} 714 715/// UnrollVectorOp - We know that the given vector has a legal type, however 716/// the operation it performs is not legal and is an operation that we have 717/// no way of lowering. "Unroll" the vector, splitting out the scalars and 718/// operating on each element individually. 719SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 720 MVT::ValueType VT = Op.getValueType(); 721 assert(isTypeLegal(VT) && 722 "Caller should expand or promote operands that are not legal!"); 723 assert(Op.Val->getNumValues() == 1 && 724 "Can't unroll a vector with multiple results!"); 725 unsigned NE = MVT::getVectorNumElements(VT); 726 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 727 728 SmallVector<SDOperand, 8> Scalars; 729 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 730 for (unsigned i = 0; i != NE; ++i) { 731 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 732 SDOperand Operand = Op.getOperand(j); 733 MVT::ValueType OperandVT = Operand.getValueType(); 734 if (MVT::isVector(OperandVT)) { 735 // A vector operand; extract a single element. 736 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 737 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 738 OperandEltVT, 739 Operand, 740 DAG.getConstant(i, MVT::i32)); 741 } else { 742 // A scalar operand; just use it as is. 743 Operands[j] = Operand; 744 } 745 } 746 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 747 &Operands[0], Operands.size())); 748 } 749 750 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 751} 752 753/// GetFPLibCall - Return the right libcall for the given floating point type. 754static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, 755 RTLIB::Libcall Call_F32, 756 RTLIB::Libcall Call_F64, 757 RTLIB::Libcall Call_F80, 758 RTLIB::Libcall Call_PPCF128) { 759 return 760 VT == MVT::f32 ? Call_F32 : 761 VT == MVT::f64 ? Call_F64 : 762 VT == MVT::f80 ? Call_F80 : 763 VT == MVT::ppcf128 ? Call_PPCF128 : 764 RTLIB::UNKNOWN_LIBCALL; 765} 766 767/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 768/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 769/// is necessary to spill the vector being inserted into to memory, perform 770/// the insert there, and then read the result back. 771SDOperand SelectionDAGLegalize:: 772PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { 773 SDOperand Tmp1 = Vec; 774 SDOperand Tmp2 = Val; 775 SDOperand Tmp3 = Idx; 776 777 // If the target doesn't support this, we have to spill the input vector 778 // to a temporary stack slot, update the element, then reload it. This is 779 // badness. We could also load the value into a vector register (either 780 // with a "move to register" or "extload into register" instruction, then 781 // permute it into place, if the idx is a constant and if the idx is 782 // supported by the target. 783 MVT::ValueType VT = Tmp1.getValueType(); 784 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 785 MVT::ValueType IdxVT = Tmp3.getValueType(); 786 MVT::ValueType PtrVT = TLI.getPointerTy(); 787 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 788 789 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); 790 int SPFI = StackPtrFI->getIndex(); 791 792 // Store the vector. 793 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 794 PseudoSourceValue::getFixedStack(), 795 SPFI); 796 797 // Truncate or zero extend offset to target pointer type. 798 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 799 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 800 // Add the offset to the index. 801 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 802 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 803 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 804 // Store the scalar value. 805 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 806 PseudoSourceValue::getFixedStack(), SPFI, EltVT); 807 // Load the updated vector. 808 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI); 809} 810 811/// LegalizeOp - We know that the specified value has a legal type, and 812/// that its operands are legal. Now ensure that the operation itself 813/// is legal, recursively ensuring that the operands' operations remain 814/// legal. 815SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 816 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 817 return Op; 818 819 assert(isTypeLegal(Op.getValueType()) && 820 "Caller should expand or promote operands that are not legal!"); 821 SDNode *Node = Op.Val; 822 823 // If this operation defines any values that cannot be represented in a 824 // register on this target, make sure to expand or promote them. 825 if (Node->getNumValues() > 1) { 826 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 827 if (getTypeAction(Node->getValueType(i)) != Legal) { 828 HandleOp(Op.getValue(i)); 829 assert(LegalizedNodes.count(Op) && 830 "Handling didn't add legal operands!"); 831 return LegalizedNodes[Op]; 832 } 833 } 834 835 // Note that LegalizeOp may be reentered even from single-use nodes, which 836 // means that we always must cache transformed nodes. 837 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 838 if (I != LegalizedNodes.end()) return I->second; 839 840 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 841 SDOperand Result = Op; 842 bool isCustom = false; 843 844 switch (Node->getOpcode()) { 845 case ISD::FrameIndex: 846 case ISD::EntryToken: 847 case ISD::Register: 848 case ISD::BasicBlock: 849 case ISD::TargetFrameIndex: 850 case ISD::TargetJumpTable: 851 case ISD::TargetConstant: 852 case ISD::TargetConstantFP: 853 case ISD::TargetConstantPool: 854 case ISD::TargetGlobalAddress: 855 case ISD::TargetGlobalTLSAddress: 856 case ISD::TargetExternalSymbol: 857 case ISD::VALUETYPE: 858 case ISD::SRCVALUE: 859 case ISD::MEMOPERAND: 860 case ISD::STRING: 861 case ISD::CONDCODE: 862 case ISD::ARG_FLAGS: 863 // Primitives must all be legal. 864 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 865 "This must be legal!"); 866 break; 867 default: 868 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 869 // If this is a target node, legalize it by legalizing the operands then 870 // passing it through. 871 SmallVector<SDOperand, 8> Ops; 872 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 873 Ops.push_back(LegalizeOp(Node->getOperand(i))); 874 875 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 876 877 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 878 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 879 return Result.getValue(Op.ResNo); 880 } 881 // Otherwise this is an unhandled builtin node. splat. 882#ifndef NDEBUG 883 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 884#endif 885 assert(0 && "Do not know how to legalize this operator!"); 886 abort(); 887 case ISD::GLOBAL_OFFSET_TABLE: 888 case ISD::GlobalAddress: 889 case ISD::GlobalTLSAddress: 890 case ISD::ExternalSymbol: 891 case ISD::ConstantPool: 892 case ISD::JumpTable: // Nothing to do. 893 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 894 default: assert(0 && "This action is not supported yet!"); 895 case TargetLowering::Custom: 896 Tmp1 = TLI.LowerOperation(Op, DAG); 897 if (Tmp1.Val) Result = Tmp1; 898 // FALLTHROUGH if the target doesn't want to lower this op after all. 899 case TargetLowering::Legal: 900 break; 901 } 902 break; 903 case ISD::FRAMEADDR: 904 case ISD::RETURNADDR: 905 // The only option for these nodes is to custom lower them. If the target 906 // does not custom lower them, then return zero. 907 Tmp1 = TLI.LowerOperation(Op, DAG); 908 if (Tmp1.Val) 909 Result = Tmp1; 910 else 911 Result = DAG.getConstant(0, TLI.getPointerTy()); 912 break; 913 case ISD::FRAME_TO_ARGS_OFFSET: { 914 MVT::ValueType VT = Node->getValueType(0); 915 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 916 default: assert(0 && "This action is not supported yet!"); 917 case TargetLowering::Custom: 918 Result = TLI.LowerOperation(Op, DAG); 919 if (Result.Val) break; 920 // Fall Thru 921 case TargetLowering::Legal: 922 Result = DAG.getConstant(0, VT); 923 break; 924 } 925 } 926 break; 927 case ISD::EXCEPTIONADDR: { 928 Tmp1 = LegalizeOp(Node->getOperand(0)); 929 MVT::ValueType VT = Node->getValueType(0); 930 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 931 default: assert(0 && "This action is not supported yet!"); 932 case TargetLowering::Expand: { 933 unsigned Reg = TLI.getExceptionAddressRegister(); 934 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 935 } 936 break; 937 case TargetLowering::Custom: 938 Result = TLI.LowerOperation(Op, DAG); 939 if (Result.Val) break; 940 // Fall Thru 941 case TargetLowering::Legal: { 942 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 943 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 944 Ops, 2); 945 break; 946 } 947 } 948 } 949 if (Result.Val->getNumValues() == 1) break; 950 951 assert(Result.Val->getNumValues() == 2 && 952 "Cannot return more than two values!"); 953 954 // Since we produced two values, make sure to remember that we 955 // legalized both of them. 956 Tmp1 = LegalizeOp(Result); 957 Tmp2 = LegalizeOp(Result.getValue(1)); 958 AddLegalizedOperand(Op.getValue(0), Tmp1); 959 AddLegalizedOperand(Op.getValue(1), Tmp2); 960 return Op.ResNo ? Tmp2 : Tmp1; 961 case ISD::EHSELECTION: { 962 Tmp1 = LegalizeOp(Node->getOperand(0)); 963 Tmp2 = LegalizeOp(Node->getOperand(1)); 964 MVT::ValueType VT = Node->getValueType(0); 965 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 966 default: assert(0 && "This action is not supported yet!"); 967 case TargetLowering::Expand: { 968 unsigned Reg = TLI.getExceptionSelectorRegister(); 969 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 970 } 971 break; 972 case TargetLowering::Custom: 973 Result = TLI.LowerOperation(Op, DAG); 974 if (Result.Val) break; 975 // Fall Thru 976 case TargetLowering::Legal: { 977 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 978 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 979 Ops, 2); 980 break; 981 } 982 } 983 } 984 if (Result.Val->getNumValues() == 1) break; 985 986 assert(Result.Val->getNumValues() == 2 && 987 "Cannot return more than two values!"); 988 989 // Since we produced two values, make sure to remember that we 990 // legalized both of them. 991 Tmp1 = LegalizeOp(Result); 992 Tmp2 = LegalizeOp(Result.getValue(1)); 993 AddLegalizedOperand(Op.getValue(0), Tmp1); 994 AddLegalizedOperand(Op.getValue(1), Tmp2); 995 return Op.ResNo ? Tmp2 : Tmp1; 996 case ISD::EH_RETURN: { 997 MVT::ValueType VT = Node->getValueType(0); 998 // The only "good" option for this node is to custom lower it. 999 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1000 default: assert(0 && "This action is not supported at all!"); 1001 case TargetLowering::Custom: 1002 Result = TLI.LowerOperation(Op, DAG); 1003 if (Result.Val) break; 1004 // Fall Thru 1005 case TargetLowering::Legal: 1006 // Target does not know, how to lower this, lower to noop 1007 Result = LegalizeOp(Node->getOperand(0)); 1008 break; 1009 } 1010 } 1011 break; 1012 case ISD::AssertSext: 1013 case ISD::AssertZext: 1014 Tmp1 = LegalizeOp(Node->getOperand(0)); 1015 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1016 break; 1017 case ISD::MERGE_VALUES: 1018 // Legalize eliminates MERGE_VALUES nodes. 1019 Result = Node->getOperand(Op.ResNo); 1020 break; 1021 case ISD::CopyFromReg: 1022 Tmp1 = LegalizeOp(Node->getOperand(0)); 1023 Result = Op.getValue(0); 1024 if (Node->getNumValues() == 2) { 1025 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1026 } else { 1027 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1028 if (Node->getNumOperands() == 3) { 1029 Tmp2 = LegalizeOp(Node->getOperand(2)); 1030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1031 } else { 1032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1033 } 1034 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1035 } 1036 // Since CopyFromReg produces two values, make sure to remember that we 1037 // legalized both of them. 1038 AddLegalizedOperand(Op.getValue(0), Result); 1039 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1040 return Result.getValue(Op.ResNo); 1041 case ISD::UNDEF: { 1042 MVT::ValueType VT = Op.getValueType(); 1043 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1044 default: assert(0 && "This action is not supported yet!"); 1045 case TargetLowering::Expand: 1046 if (MVT::isInteger(VT)) 1047 Result = DAG.getConstant(0, VT); 1048 else if (MVT::isFloatingPoint(VT)) 1049 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 1050 VT); 1051 else 1052 assert(0 && "Unknown value type!"); 1053 break; 1054 case TargetLowering::Legal: 1055 break; 1056 } 1057 break; 1058 } 1059 1060 case ISD::INTRINSIC_W_CHAIN: 1061 case ISD::INTRINSIC_WO_CHAIN: 1062 case ISD::INTRINSIC_VOID: { 1063 SmallVector<SDOperand, 8> Ops; 1064 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1065 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1066 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1067 1068 // Allow the target to custom lower its intrinsics if it wants to. 1069 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1070 TargetLowering::Custom) { 1071 Tmp3 = TLI.LowerOperation(Result, DAG); 1072 if (Tmp3.Val) Result = Tmp3; 1073 } 1074 1075 if (Result.Val->getNumValues() == 1) break; 1076 1077 // Must have return value and chain result. 1078 assert(Result.Val->getNumValues() == 2 && 1079 "Cannot return more than two values!"); 1080 1081 // Since loads produce two values, make sure to remember that we 1082 // legalized both of them. 1083 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1084 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1085 return Result.getValue(Op.ResNo); 1086 } 1087 1088 case ISD::LOCATION: 1089 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1091 1092 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1093 case TargetLowering::Promote: 1094 default: assert(0 && "This action is not supported yet!"); 1095 case TargetLowering::Expand: { 1096 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1097 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1098 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1099 1100 if (MMI && (useDEBUG_LOC || useLABEL)) { 1101 const std::string &FName = 1102 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1103 const std::string &DirName = 1104 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1105 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1106 1107 SmallVector<SDOperand, 8> Ops; 1108 Ops.push_back(Tmp1); // chain 1109 SDOperand LineOp = Node->getOperand(1); 1110 SDOperand ColOp = Node->getOperand(2); 1111 1112 if (useDEBUG_LOC) { 1113 Ops.push_back(LineOp); // line # 1114 Ops.push_back(ColOp); // col # 1115 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1116 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1117 } else { 1118 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1119 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1120 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1121 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1122 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label 1123 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size()); 1124 } 1125 } else { 1126 Result = Tmp1; // chain 1127 } 1128 break; 1129 } 1130 case TargetLowering::Legal: 1131 if (Tmp1 != Node->getOperand(0) || 1132 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1133 SmallVector<SDOperand, 8> Ops; 1134 Ops.push_back(Tmp1); 1135 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1136 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1137 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1138 } else { 1139 // Otherwise promote them. 1140 Ops.push_back(PromoteOp(Node->getOperand(1))); 1141 Ops.push_back(PromoteOp(Node->getOperand(2))); 1142 } 1143 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1144 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1145 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1146 } 1147 break; 1148 } 1149 break; 1150 1151 case ISD::DECLARE: 1152 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1153 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1154 default: assert(0 && "This action is not supported yet!"); 1155 case TargetLowering::Legal: 1156 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1160 break; 1161 case TargetLowering::Expand: 1162 Result = LegalizeOp(Node->getOperand(0)); 1163 break; 1164 } 1165 break; 1166 1167 case ISD::DEBUG_LOC: 1168 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1169 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1170 default: assert(0 && "This action is not supported yet!"); 1171 case TargetLowering::Legal: 1172 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1173 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1174 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1175 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1177 break; 1178 } 1179 break; 1180 1181 case ISD::LABEL: 1182 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!"); 1183 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1184 default: assert(0 && "This action is not supported yet!"); 1185 case TargetLowering::Legal: 1186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1187 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1188 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand. 1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1190 break; 1191 case TargetLowering::Expand: 1192 Result = LegalizeOp(Node->getOperand(0)); 1193 break; 1194 } 1195 break; 1196 1197 case ISD::PREFETCH: 1198 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1199 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1200 default: assert(0 && "This action is not supported yet!"); 1201 case TargetLowering::Legal: 1202 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1204 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1205 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1207 break; 1208 case TargetLowering::Expand: 1209 // It's a noop. 1210 Result = LegalizeOp(Node->getOperand(0)); 1211 break; 1212 } 1213 break; 1214 1215 case ISD::MEMBARRIER: { 1216 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1217 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1218 default: assert(0 && "This action is not supported yet!"); 1219 case TargetLowering::Legal: { 1220 SDOperand Ops[6]; 1221 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1222 for (int x = 1; x < 6; ++x) { 1223 Ops[x] = Node->getOperand(x); 1224 if (!isTypeLegal(Ops[x].getValueType())) 1225 Ops[x] = PromoteOp(Ops[x]); 1226 } 1227 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1228 break; 1229 } 1230 case TargetLowering::Expand: 1231 //There is no libgcc call for this op 1232 Result = Node->getOperand(0); // Noop 1233 break; 1234 } 1235 break; 1236 } 1237 1238 case ISD::ATOMIC_LCS: { 1239 unsigned int num_operands = 4; 1240 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1241 SDOperand Ops[4]; 1242 for (unsigned int x = 0; x < num_operands; ++x) 1243 Ops[x] = LegalizeOp(Node->getOperand(x)); 1244 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1245 1246 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1247 default: assert(0 && "This action is not supported yet!"); 1248 case TargetLowering::Custom: 1249 Result = TLI.LowerOperation(Result, DAG); 1250 break; 1251 case TargetLowering::Legal: 1252 break; 1253 } 1254 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1255 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1256 return Result.getValue(Op.ResNo); 1257 } 1258 case ISD::ATOMIC_LAS: 1259 case ISD::ATOMIC_LSS: 1260 case ISD::ATOMIC_LOAD_AND: 1261 case ISD::ATOMIC_LOAD_OR: 1262 case ISD::ATOMIC_LOAD_XOR: 1263 case ISD::ATOMIC_LOAD_MIN: 1264 case ISD::ATOMIC_LOAD_MAX: 1265 case ISD::ATOMIC_LOAD_UMIN: 1266 case ISD::ATOMIC_LOAD_UMAX: 1267 case ISD::ATOMIC_SWAP: { 1268 unsigned int num_operands = 3; 1269 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1270 SDOperand Ops[3]; 1271 for (unsigned int x = 0; x < num_operands; ++x) 1272 Ops[x] = LegalizeOp(Node->getOperand(x)); 1273 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1274 1275 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1276 default: assert(0 && "This action is not supported yet!"); 1277 case TargetLowering::Custom: 1278 Result = TLI.LowerOperation(Result, DAG); 1279 break; 1280 case TargetLowering::Expand: 1281 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0); 1282 break; 1283 case TargetLowering::Legal: 1284 break; 1285 } 1286 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1287 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1288 return Result.getValue(Op.ResNo); 1289 } 1290 case ISD::Constant: { 1291 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1292 unsigned opAction = 1293 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1294 1295 // We know we don't need to expand constants here, constants only have one 1296 // value and we check that it is fine above. 1297 1298 if (opAction == TargetLowering::Custom) { 1299 Tmp1 = TLI.LowerOperation(Result, DAG); 1300 if (Tmp1.Val) 1301 Result = Tmp1; 1302 } 1303 break; 1304 } 1305 case ISD::ConstantFP: { 1306 // Spill FP immediates to the constant pool if the target cannot directly 1307 // codegen them. Targets often have some immediate values that can be 1308 // efficiently generated into an FP register without a load. We explicitly 1309 // leave these constants as ConstantFP nodes for the target to deal with. 1310 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1311 1312 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1313 default: assert(0 && "This action is not supported yet!"); 1314 case TargetLowering::Legal: 1315 break; 1316 case TargetLowering::Custom: 1317 Tmp3 = TLI.LowerOperation(Result, DAG); 1318 if (Tmp3.Val) { 1319 Result = Tmp3; 1320 break; 1321 } 1322 // FALLTHROUGH 1323 case TargetLowering::Expand: { 1324 // Check to see if this FP immediate is already legal. 1325 bool isLegal = false; 1326 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1327 E = TLI.legal_fpimm_end(); I != E; ++I) { 1328 if (CFP->isExactlyValue(*I)) { 1329 isLegal = true; 1330 break; 1331 } 1332 } 1333 // If this is a legal constant, turn it into a TargetConstantFP node. 1334 if (isLegal) 1335 break; 1336 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1337 } 1338 } 1339 break; 1340 } 1341 case ISD::TokenFactor: 1342 if (Node->getNumOperands() == 2) { 1343 Tmp1 = LegalizeOp(Node->getOperand(0)); 1344 Tmp2 = LegalizeOp(Node->getOperand(1)); 1345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1346 } else if (Node->getNumOperands() == 3) { 1347 Tmp1 = LegalizeOp(Node->getOperand(0)); 1348 Tmp2 = LegalizeOp(Node->getOperand(1)); 1349 Tmp3 = LegalizeOp(Node->getOperand(2)); 1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1351 } else { 1352 SmallVector<SDOperand, 8> Ops; 1353 // Legalize the operands. 1354 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1355 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1356 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1357 } 1358 break; 1359 1360 case ISD::FORMAL_ARGUMENTS: 1361 case ISD::CALL: 1362 // The only option for this is to custom lower it. 1363 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1364 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1365 // A call within a calling sequence must be legalized to something 1366 // other than the normal CALLSEQ_END. Violating this gets Legalize 1367 // into an infinite loop. 1368 assert ((!IsLegalizingCall || 1369 Node->getOpcode() != ISD::CALL || 1370 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1371 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1372 1373 // The number of incoming and outgoing values should match; unless the final 1374 // outgoing value is a flag. 1375 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1376 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1377 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1378 MVT::Flag)) && 1379 "Lowering call/formal_arguments produced unexpected # results!"); 1380 1381 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1382 // remember that we legalized all of them, so it doesn't get relegalized. 1383 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1384 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1385 continue; 1386 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1387 if (Op.ResNo == i) 1388 Tmp2 = Tmp1; 1389 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1390 } 1391 return Tmp2; 1392 case ISD::EXTRACT_SUBREG: { 1393 Tmp1 = LegalizeOp(Node->getOperand(0)); 1394 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1395 assert(idx && "Operand must be a constant"); 1396 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1398 } 1399 break; 1400 case ISD::INSERT_SUBREG: { 1401 Tmp1 = LegalizeOp(Node->getOperand(0)); 1402 Tmp2 = LegalizeOp(Node->getOperand(1)); 1403 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1404 assert(idx && "Operand must be a constant"); 1405 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1406 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1407 } 1408 break; 1409 case ISD::BUILD_VECTOR: 1410 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1411 default: assert(0 && "This action is not supported yet!"); 1412 case TargetLowering::Custom: 1413 Tmp3 = TLI.LowerOperation(Result, DAG); 1414 if (Tmp3.Val) { 1415 Result = Tmp3; 1416 break; 1417 } 1418 // FALLTHROUGH 1419 case TargetLowering::Expand: 1420 Result = ExpandBUILD_VECTOR(Result.Val); 1421 break; 1422 } 1423 break; 1424 case ISD::INSERT_VECTOR_ELT: 1425 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1426 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1427 1428 // The type of the value to insert may not be legal, even though the vector 1429 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1430 // here. 1431 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1432 default: assert(0 && "Cannot expand insert element operand"); 1433 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1434 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1435 } 1436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1437 1438 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1439 Node->getValueType(0))) { 1440 default: assert(0 && "This action is not supported yet!"); 1441 case TargetLowering::Legal: 1442 break; 1443 case TargetLowering::Custom: 1444 Tmp4 = TLI.LowerOperation(Result, DAG); 1445 if (Tmp4.Val) { 1446 Result = Tmp4; 1447 break; 1448 } 1449 // FALLTHROUGH 1450 case TargetLowering::Expand: { 1451 // If the insert index is a constant, codegen this as a scalar_to_vector, 1452 // then a shuffle that inserts it into the right position in the vector. 1453 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1454 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1455 // match the element type of the vector being created. 1456 if (Tmp2.getValueType() == 1457 MVT::getVectorElementType(Op.getValueType())) { 1458 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1459 Tmp1.getValueType(), Tmp2); 1460 1461 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1462 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1463 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1464 1465 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1466 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1467 // elt 0 of the RHS. 1468 SmallVector<SDOperand, 8> ShufOps; 1469 for (unsigned i = 0; i != NumElts; ++i) { 1470 if (i != InsertPos->getValue()) 1471 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1472 else 1473 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1474 } 1475 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1476 &ShufOps[0], ShufOps.size()); 1477 1478 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1479 Tmp1, ScVec, ShufMask); 1480 Result = LegalizeOp(Result); 1481 break; 1482 } 1483 } 1484 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1485 break; 1486 } 1487 } 1488 break; 1489 case ISD::SCALAR_TO_VECTOR: 1490 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1491 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1492 break; 1493 } 1494 1495 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1496 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1497 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1498 Node->getValueType(0))) { 1499 default: assert(0 && "This action is not supported yet!"); 1500 case TargetLowering::Legal: 1501 break; 1502 case TargetLowering::Custom: 1503 Tmp3 = TLI.LowerOperation(Result, DAG); 1504 if (Tmp3.Val) { 1505 Result = Tmp3; 1506 break; 1507 } 1508 // FALLTHROUGH 1509 case TargetLowering::Expand: 1510 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1511 break; 1512 } 1513 break; 1514 case ISD::VECTOR_SHUFFLE: 1515 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1516 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1518 1519 // Allow targets to custom lower the SHUFFLEs they support. 1520 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1521 default: assert(0 && "Unknown operation action!"); 1522 case TargetLowering::Legal: 1523 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1524 "vector shuffle should not be created if not legal!"); 1525 break; 1526 case TargetLowering::Custom: 1527 Tmp3 = TLI.LowerOperation(Result, DAG); 1528 if (Tmp3.Val) { 1529 Result = Tmp3; 1530 break; 1531 } 1532 // FALLTHROUGH 1533 case TargetLowering::Expand: { 1534 MVT::ValueType VT = Node->getValueType(0); 1535 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1536 MVT::ValueType PtrVT = TLI.getPointerTy(); 1537 SDOperand Mask = Node->getOperand(2); 1538 unsigned NumElems = Mask.getNumOperands(); 1539 SmallVector<SDOperand,8> Ops; 1540 for (unsigned i = 0; i != NumElems; ++i) { 1541 SDOperand Arg = Mask.getOperand(i); 1542 if (Arg.getOpcode() == ISD::UNDEF) { 1543 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1544 } else { 1545 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1546 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1547 if (Idx < NumElems) 1548 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1549 DAG.getConstant(Idx, PtrVT))); 1550 else 1551 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1552 DAG.getConstant(Idx - NumElems, PtrVT))); 1553 } 1554 } 1555 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1556 break; 1557 } 1558 case TargetLowering::Promote: { 1559 // Change base type to a different vector type. 1560 MVT::ValueType OVT = Node->getValueType(0); 1561 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1562 1563 // Cast the two input vectors. 1564 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1565 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1566 1567 // Convert the shuffle mask to the right # elements. 1568 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1569 assert(Tmp3.Val && "Shuffle not legal?"); 1570 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1571 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1572 break; 1573 } 1574 } 1575 break; 1576 1577 case ISD::EXTRACT_VECTOR_ELT: 1578 Tmp1 = Node->getOperand(0); 1579 Tmp2 = LegalizeOp(Node->getOperand(1)); 1580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1581 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1582 break; 1583 1584 case ISD::EXTRACT_SUBVECTOR: 1585 Tmp1 = Node->getOperand(0); 1586 Tmp2 = LegalizeOp(Node->getOperand(1)); 1587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1588 Result = ExpandEXTRACT_SUBVECTOR(Result); 1589 break; 1590 1591 case ISD::CALLSEQ_START: { 1592 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1593 1594 // Recursively Legalize all of the inputs of the call end that do not lead 1595 // to this call start. This ensures that any libcalls that need be inserted 1596 // are inserted *before* the CALLSEQ_START. 1597 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1598 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1599 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1600 NodesLeadingTo); 1601 } 1602 1603 // Now that we legalized all of the inputs (which may have inserted 1604 // libcalls) create the new CALLSEQ_START node. 1605 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1606 1607 // Merge in the last call, to ensure that this call start after the last 1608 // call ended. 1609 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1610 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1611 Tmp1 = LegalizeOp(Tmp1); 1612 } 1613 1614 // Do not try to legalize the target-specific arguments (#1+). 1615 if (Tmp1 != Node->getOperand(0)) { 1616 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1617 Ops[0] = Tmp1; 1618 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1619 } 1620 1621 // Remember that the CALLSEQ_START is legalized. 1622 AddLegalizedOperand(Op.getValue(0), Result); 1623 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1624 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1625 1626 // Now that the callseq_start and all of the non-call nodes above this call 1627 // sequence have been legalized, legalize the call itself. During this 1628 // process, no libcalls can/will be inserted, guaranteeing that no calls 1629 // can overlap. 1630 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1631 SDOperand InCallSEQ = LastCALLSEQ_END; 1632 // Note that we are selecting this call! 1633 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1634 IsLegalizingCall = true; 1635 1636 // Legalize the call, starting from the CALLSEQ_END. 1637 LegalizeOp(LastCALLSEQ_END); 1638 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1639 return Result; 1640 } 1641 case ISD::CALLSEQ_END: 1642 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1643 // will cause this node to be legalized as well as handling libcalls right. 1644 if (LastCALLSEQ_END.Val != Node) { 1645 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1646 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1647 assert(I != LegalizedNodes.end() && 1648 "Legalizing the call start should have legalized this node!"); 1649 return I->second; 1650 } 1651 1652 // Otherwise, the call start has been legalized and everything is going 1653 // according to plan. Just legalize ourselves normally here. 1654 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1655 // Do not try to legalize the target-specific arguments (#1+), except for 1656 // an optional flag input. 1657 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1658 if (Tmp1 != Node->getOperand(0)) { 1659 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1660 Ops[0] = Tmp1; 1661 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1662 } 1663 } else { 1664 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1665 if (Tmp1 != Node->getOperand(0) || 1666 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1667 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1668 Ops[0] = Tmp1; 1669 Ops.back() = Tmp2; 1670 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1671 } 1672 } 1673 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1674 // This finishes up call legalization. 1675 IsLegalizingCall = false; 1676 1677 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1678 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1679 if (Node->getNumValues() == 2) 1680 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1681 return Result.getValue(Op.ResNo); 1682 case ISD::DYNAMIC_STACKALLOC: { 1683 MVT::ValueType VT = Node->getValueType(0); 1684 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1685 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1686 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1687 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1688 1689 Tmp1 = Result.getValue(0); 1690 Tmp2 = Result.getValue(1); 1691 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1692 default: assert(0 && "This action is not supported yet!"); 1693 case TargetLowering::Expand: { 1694 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1695 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1696 " not tell us which reg is the stack pointer!"); 1697 SDOperand Chain = Tmp1.getOperand(0); 1698 1699 // Chain the dynamic stack allocation so that it doesn't modify the stack 1700 // pointer when other instructions are using the stack. 1701 Chain = DAG.getCALLSEQ_START(Chain, 1702 DAG.getConstant(0, TLI.getPointerTy())); 1703 1704 SDOperand Size = Tmp2.getOperand(1); 1705 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1706 Chain = SP.getValue(1); 1707 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1708 unsigned StackAlign = 1709 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1710 if (Align > StackAlign) 1711 SP = DAG.getNode(ISD::AND, VT, SP, 1712 DAG.getConstant(-(uint64_t)Align, VT)); 1713 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1714 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1715 1716 Tmp2 = 1717 DAG.getCALLSEQ_END(Chain, 1718 DAG.getConstant(0, TLI.getPointerTy()), 1719 DAG.getConstant(0, TLI.getPointerTy()), 1720 SDOperand()); 1721 1722 Tmp1 = LegalizeOp(Tmp1); 1723 Tmp2 = LegalizeOp(Tmp2); 1724 break; 1725 } 1726 case TargetLowering::Custom: 1727 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1728 if (Tmp3.Val) { 1729 Tmp1 = LegalizeOp(Tmp3); 1730 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1731 } 1732 break; 1733 case TargetLowering::Legal: 1734 break; 1735 } 1736 // Since this op produce two values, make sure to remember that we 1737 // legalized both of them. 1738 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1739 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1740 return Op.ResNo ? Tmp2 : Tmp1; 1741 } 1742 case ISD::INLINEASM: { 1743 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1744 bool Changed = false; 1745 // Legalize all of the operands of the inline asm, in case they are nodes 1746 // that need to be expanded or something. Note we skip the asm string and 1747 // all of the TargetConstant flags. 1748 SDOperand Op = LegalizeOp(Ops[0]); 1749 Changed = Op != Ops[0]; 1750 Ops[0] = Op; 1751 1752 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1753 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1754 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1755 for (++i; NumVals; ++i, --NumVals) { 1756 SDOperand Op = LegalizeOp(Ops[i]); 1757 if (Op != Ops[i]) { 1758 Changed = true; 1759 Ops[i] = Op; 1760 } 1761 } 1762 } 1763 1764 if (HasInFlag) { 1765 Op = LegalizeOp(Ops.back()); 1766 Changed |= Op != Ops.back(); 1767 Ops.back() = Op; 1768 } 1769 1770 if (Changed) 1771 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1772 1773 // INLINE asm returns a chain and flag, make sure to add both to the map. 1774 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1775 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1776 return Result.getValue(Op.ResNo); 1777 } 1778 case ISD::BR: 1779 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1780 // Ensure that libcalls are emitted before a branch. 1781 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1782 Tmp1 = LegalizeOp(Tmp1); 1783 LastCALLSEQ_END = DAG.getEntryNode(); 1784 1785 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1786 break; 1787 case ISD::BRIND: 1788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1789 // Ensure that libcalls are emitted before a branch. 1790 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1791 Tmp1 = LegalizeOp(Tmp1); 1792 LastCALLSEQ_END = DAG.getEntryNode(); 1793 1794 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1795 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1796 case Legal: 1797 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1798 break; 1799 } 1800 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1801 break; 1802 case ISD::BR_JT: 1803 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1804 // Ensure that libcalls are emitted before a branch. 1805 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1806 Tmp1 = LegalizeOp(Tmp1); 1807 LastCALLSEQ_END = DAG.getEntryNode(); 1808 1809 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1810 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1811 1812 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1813 default: assert(0 && "This action is not supported yet!"); 1814 case TargetLowering::Legal: break; 1815 case TargetLowering::Custom: 1816 Tmp1 = TLI.LowerOperation(Result, DAG); 1817 if (Tmp1.Val) Result = Tmp1; 1818 break; 1819 case TargetLowering::Expand: { 1820 SDOperand Chain = Result.getOperand(0); 1821 SDOperand Table = Result.getOperand(1); 1822 SDOperand Index = Result.getOperand(2); 1823 1824 MVT::ValueType PTy = TLI.getPointerTy(); 1825 MachineFunction &MF = DAG.getMachineFunction(); 1826 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1827 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1828 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1829 1830 SDOperand LD; 1831 switch (EntrySize) { 1832 default: assert(0 && "Size of jump table not supported yet."); break; 1833 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1834 PseudoSourceValue::getJumpTable(), 0); break; 1835 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1836 PseudoSourceValue::getJumpTable(), 0); break; 1837 } 1838 1839 Addr = LD; 1840 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1841 // For PIC, the sequence is: 1842 // BRIND(load(Jumptable + index) + RelocBase) 1843 // RelocBase can be JumpTable, GOT or some sort of global base. 1844 if (PTy != MVT::i32) 1845 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1846 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1847 TLI.getPICJumpTableRelocBase(Table, DAG)); 1848 } 1849 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1850 } 1851 } 1852 break; 1853 case ISD::BRCOND: 1854 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1855 // Ensure that libcalls are emitted before a return. 1856 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1857 Tmp1 = LegalizeOp(Tmp1); 1858 LastCALLSEQ_END = DAG.getEntryNode(); 1859 1860 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1861 case Expand: assert(0 && "It's impossible to expand bools"); 1862 case Legal: 1863 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1864 break; 1865 case Promote: { 1866 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1867 1868 // The top bits of the promoted condition are not necessarily zero, ensure 1869 // that the value is properly zero extended. 1870 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1871 if (!DAG.MaskedValueIsZero(Tmp2, 1872 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1873 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1874 break; 1875 } 1876 } 1877 1878 // Basic block destination (Op#2) is always legal. 1879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1880 1881 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1882 default: assert(0 && "This action is not supported yet!"); 1883 case TargetLowering::Legal: break; 1884 case TargetLowering::Custom: 1885 Tmp1 = TLI.LowerOperation(Result, DAG); 1886 if (Tmp1.Val) Result = Tmp1; 1887 break; 1888 case TargetLowering::Expand: 1889 // Expand brcond's setcc into its constituent parts and create a BR_CC 1890 // Node. 1891 if (Tmp2.getOpcode() == ISD::SETCC) { 1892 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1893 Tmp2.getOperand(0), Tmp2.getOperand(1), 1894 Node->getOperand(2)); 1895 } else { 1896 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1897 DAG.getCondCode(ISD::SETNE), Tmp2, 1898 DAG.getConstant(0, Tmp2.getValueType()), 1899 Node->getOperand(2)); 1900 } 1901 break; 1902 } 1903 break; 1904 case ISD::BR_CC: 1905 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1906 // Ensure that libcalls are emitted before a branch. 1907 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1908 Tmp1 = LegalizeOp(Tmp1); 1909 Tmp2 = Node->getOperand(2); // LHS 1910 Tmp3 = Node->getOperand(3); // RHS 1911 Tmp4 = Node->getOperand(1); // CC 1912 1913 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1914 LastCALLSEQ_END = DAG.getEntryNode(); 1915 1916 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1917 // the LHS is a legal SETCC itself. In this case, we need to compare 1918 // the result against zero to select between true and false values. 1919 if (Tmp3.Val == 0) { 1920 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1921 Tmp4 = DAG.getCondCode(ISD::SETNE); 1922 } 1923 1924 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1925 Node->getOperand(4)); 1926 1927 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1928 default: assert(0 && "Unexpected action for BR_CC!"); 1929 case TargetLowering::Legal: break; 1930 case TargetLowering::Custom: 1931 Tmp4 = TLI.LowerOperation(Result, DAG); 1932 if (Tmp4.Val) Result = Tmp4; 1933 break; 1934 } 1935 break; 1936 case ISD::LOAD: { 1937 LoadSDNode *LD = cast<LoadSDNode>(Node); 1938 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1939 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1940 1941 ISD::LoadExtType ExtType = LD->getExtensionType(); 1942 if (ExtType == ISD::NON_EXTLOAD) { 1943 MVT::ValueType VT = Node->getValueType(0); 1944 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1945 Tmp3 = Result.getValue(0); 1946 Tmp4 = Result.getValue(1); 1947 1948 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1949 default: assert(0 && "This action is not supported yet!"); 1950 case TargetLowering::Legal: 1951 // If this is an unaligned load and the target doesn't support it, 1952 // expand it. 1953 if (!TLI.allowsUnalignedMemoryAccesses()) { 1954 unsigned ABIAlignment = TLI.getTargetData()-> 1955 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); 1956 if (LD->getAlignment() < ABIAlignment){ 1957 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1958 TLI); 1959 Tmp3 = Result.getOperand(0); 1960 Tmp4 = Result.getOperand(1); 1961 Tmp3 = LegalizeOp(Tmp3); 1962 Tmp4 = LegalizeOp(Tmp4); 1963 } 1964 } 1965 break; 1966 case TargetLowering::Custom: 1967 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1968 if (Tmp1.Val) { 1969 Tmp3 = LegalizeOp(Tmp1); 1970 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1971 } 1972 break; 1973 case TargetLowering::Promote: { 1974 // Only promote a load of vector type to another. 1975 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1976 // Change base type to a different vector type. 1977 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1978 1979 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1980 LD->getSrcValueOffset(), 1981 LD->isVolatile(), LD->getAlignment()); 1982 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1983 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1984 break; 1985 } 1986 } 1987 // Since loads produce two values, make sure to remember that we 1988 // legalized both of them. 1989 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1990 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1991 return Op.ResNo ? Tmp4 : Tmp3; 1992 } else { 1993 MVT::ValueType SrcVT = LD->getMemoryVT(); 1994 unsigned SrcWidth = MVT::getSizeInBits(SrcVT); 1995 int SVOffset = LD->getSrcValueOffset(); 1996 unsigned Alignment = LD->getAlignment(); 1997 bool isVolatile = LD->isVolatile(); 1998 1999 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) && 2000 // Some targets pretend to have an i1 loading operation, and actually 2001 // load an i8. This trick is correct for ZEXTLOAD because the top 7 2002 // bits are guaranteed to be zero; it helps the optimizers understand 2003 // that these bits are zero. It is also useful for EXTLOAD, since it 2004 // tells the optimizers that those bits are undefined. It would be 2005 // nice to have an effective generic way of getting these benefits... 2006 // Until such a way is found, don't insist on promoting i1 here. 2007 (SrcVT != MVT::i1 || 2008 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2009 // Promote to a byte-sized load if not loading an integral number of 2010 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2011 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT); 2012 MVT::ValueType NVT = MVT::getIntegerType(NewWidth); 2013 SDOperand Ch; 2014 2015 // The extra bits are guaranteed to be zero, since we stored them that 2016 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2017 2018 ISD::LoadExtType NewExtType = 2019 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2020 2021 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2022 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2023 NVT, isVolatile, Alignment); 2024 2025 Ch = Result.getValue(1); // The chain. 2026 2027 if (ExtType == ISD::SEXTLOAD) 2028 // Having the top bits zero doesn't help when sign extending. 2029 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2030 Result, DAG.getValueType(SrcVT)); 2031 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2032 // All the top bits are guaranteed to be zero - inform the optimizers. 2033 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2034 DAG.getValueType(SrcVT)); 2035 2036 Tmp1 = LegalizeOp(Result); 2037 Tmp2 = LegalizeOp(Ch); 2038 } else if (SrcWidth & (SrcWidth - 1)) { 2039 // If not loading a power-of-2 number of bits, expand as two loads. 2040 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) && 2041 "Unsupported extload!"); 2042 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2043 assert(RoundWidth < SrcWidth); 2044 unsigned ExtraWidth = SrcWidth - RoundWidth; 2045 assert(ExtraWidth < RoundWidth); 2046 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2047 "Load size not an integral number of bytes!"); 2048 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); 2049 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); 2050 SDOperand Lo, Hi, Ch; 2051 unsigned IncrementSize; 2052 2053 if (TLI.isLittleEndian()) { 2054 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2055 // Load the bottom RoundWidth bits. 2056 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2057 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2058 Alignment); 2059 2060 // Load the remaining ExtraWidth bits. 2061 IncrementSize = RoundWidth / 8; 2062 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2063 DAG.getIntPtrConstant(IncrementSize)); 2064 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2065 LD->getSrcValue(), SVOffset + IncrementSize, 2066 ExtraVT, isVolatile, 2067 MinAlign(Alignment, IncrementSize)); 2068 2069 // Build a factor node to remember that this load is independent of the 2070 // other one. 2071 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2072 Hi.getValue(1)); 2073 2074 // Move the top bits to the right place. 2075 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2076 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2077 2078 // Join the hi and lo parts. 2079 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2080 } else { 2081 // Big endian - avoid unaligned loads. 2082 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2083 // Load the top RoundWidth bits. 2084 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2085 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2086 Alignment); 2087 2088 // Load the remaining ExtraWidth bits. 2089 IncrementSize = RoundWidth / 8; 2090 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2091 DAG.getIntPtrConstant(IncrementSize)); 2092 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2093 LD->getSrcValue(), SVOffset + IncrementSize, 2094 ExtraVT, isVolatile, 2095 MinAlign(Alignment, IncrementSize)); 2096 2097 // Build a factor node to remember that this load is independent of the 2098 // other one. 2099 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2100 Hi.getValue(1)); 2101 2102 // Move the top bits to the right place. 2103 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2104 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2105 2106 // Join the hi and lo parts. 2107 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2108 } 2109 2110 Tmp1 = LegalizeOp(Result); 2111 Tmp2 = LegalizeOp(Ch); 2112 } else { 2113 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2114 default: assert(0 && "This action is not supported yet!"); 2115 case TargetLowering::Custom: 2116 isCustom = true; 2117 // FALLTHROUGH 2118 case TargetLowering::Legal: 2119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2120 Tmp1 = Result.getValue(0); 2121 Tmp2 = Result.getValue(1); 2122 2123 if (isCustom) { 2124 Tmp3 = TLI.LowerOperation(Result, DAG); 2125 if (Tmp3.Val) { 2126 Tmp1 = LegalizeOp(Tmp3); 2127 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2128 } 2129 } else { 2130 // If this is an unaligned load and the target doesn't support it, 2131 // expand it. 2132 if (!TLI.allowsUnalignedMemoryAccesses()) { 2133 unsigned ABIAlignment = TLI.getTargetData()-> 2134 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); 2135 if (LD->getAlignment() < ABIAlignment){ 2136 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2137 TLI); 2138 Tmp1 = Result.getOperand(0); 2139 Tmp2 = Result.getOperand(1); 2140 Tmp1 = LegalizeOp(Tmp1); 2141 Tmp2 = LegalizeOp(Tmp2); 2142 } 2143 } 2144 } 2145 break; 2146 case TargetLowering::Expand: 2147 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2148 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2149 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2150 LD->getSrcValueOffset(), 2151 LD->isVolatile(), LD->getAlignment()); 2152 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2153 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2154 Tmp2 = LegalizeOp(Load.getValue(1)); 2155 break; 2156 } 2157 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2158 // Turn the unsupported load into an EXTLOAD followed by an explicit 2159 // zero/sign extend inreg. 2160 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2161 Tmp1, Tmp2, LD->getSrcValue(), 2162 LD->getSrcValueOffset(), SrcVT, 2163 LD->isVolatile(), LD->getAlignment()); 2164 SDOperand ValRes; 2165 if (ExtType == ISD::SEXTLOAD) 2166 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2167 Result, DAG.getValueType(SrcVT)); 2168 else 2169 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2170 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2171 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2172 break; 2173 } 2174 } 2175 2176 // Since loads produce two values, make sure to remember that we legalized 2177 // both of them. 2178 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2179 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2180 return Op.ResNo ? Tmp2 : Tmp1; 2181 } 2182 } 2183 case ISD::EXTRACT_ELEMENT: { 2184 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 2185 switch (getTypeAction(OpTy)) { 2186 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2187 case Legal: 2188 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2189 // 1 -> Hi 2190 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2191 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 2192 TLI.getShiftAmountTy())); 2193 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2194 } else { 2195 // 0 -> Lo 2196 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2197 Node->getOperand(0)); 2198 } 2199 break; 2200 case Expand: 2201 // Get both the low and high parts. 2202 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2203 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2204 Result = Tmp2; // 1 -> Hi 2205 else 2206 Result = Tmp1; // 0 -> Lo 2207 break; 2208 } 2209 break; 2210 } 2211 2212 case ISD::CopyToReg: 2213 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2214 2215 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2216 "Register type must be legal!"); 2217 // Legalize the incoming value (must be a legal type). 2218 Tmp2 = LegalizeOp(Node->getOperand(2)); 2219 if (Node->getNumValues() == 1) { 2220 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2221 } else { 2222 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2223 if (Node->getNumOperands() == 4) { 2224 Tmp3 = LegalizeOp(Node->getOperand(3)); 2225 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2226 Tmp3); 2227 } else { 2228 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2229 } 2230 2231 // Since this produces two values, make sure to remember that we legalized 2232 // both of them. 2233 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2234 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2235 return Result; 2236 } 2237 break; 2238 2239 case ISD::RET: 2240 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2241 2242 // Ensure that libcalls are emitted before a return. 2243 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2244 Tmp1 = LegalizeOp(Tmp1); 2245 LastCALLSEQ_END = DAG.getEntryNode(); 2246 2247 switch (Node->getNumOperands()) { 2248 case 3: // ret val 2249 Tmp2 = Node->getOperand(1); 2250 Tmp3 = Node->getOperand(2); // Signness 2251 switch (getTypeAction(Tmp2.getValueType())) { 2252 case Legal: 2253 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2254 break; 2255 case Expand: 2256 if (!MVT::isVector(Tmp2.getValueType())) { 2257 SDOperand Lo, Hi; 2258 ExpandOp(Tmp2, Lo, Hi); 2259 2260 // Big endian systems want the hi reg first. 2261 if (TLI.isBigEndian()) 2262 std::swap(Lo, Hi); 2263 2264 if (Hi.Val) 2265 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2266 else 2267 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2268 Result = LegalizeOp(Result); 2269 } else { 2270 SDNode *InVal = Tmp2.Val; 2271 int InIx = Tmp2.ResNo; 2272 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 2273 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 2274 2275 // Figure out if there is a simple type corresponding to this Vector 2276 // type. If so, convert to the vector type. 2277 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2278 if (TLI.isTypeLegal(TVT)) { 2279 // Turn this into a return of the vector type. 2280 Tmp2 = LegalizeOp(Tmp2); 2281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2282 } else if (NumElems == 1) { 2283 // Turn this into a return of the scalar type. 2284 Tmp2 = ScalarizeVectorOp(Tmp2); 2285 Tmp2 = LegalizeOp(Tmp2); 2286 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2287 2288 // FIXME: Returns of gcc generic vectors smaller than a legal type 2289 // should be returned in integer registers! 2290 2291 // The scalarized value type may not be legal, e.g. it might require 2292 // promotion or expansion. Relegalize the return. 2293 Result = LegalizeOp(Result); 2294 } else { 2295 // FIXME: Returns of gcc generic vectors larger than a legal vector 2296 // type should be returned by reference! 2297 SDOperand Lo, Hi; 2298 SplitVectorOp(Tmp2, Lo, Hi); 2299 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2300 Result = LegalizeOp(Result); 2301 } 2302 } 2303 break; 2304 case Promote: 2305 Tmp2 = PromoteOp(Node->getOperand(1)); 2306 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2307 Result = LegalizeOp(Result); 2308 break; 2309 } 2310 break; 2311 case 1: // ret void 2312 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2313 break; 2314 default: { // ret <values> 2315 SmallVector<SDOperand, 8> NewValues; 2316 NewValues.push_back(Tmp1); 2317 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2318 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2319 case Legal: 2320 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2321 NewValues.push_back(Node->getOperand(i+1)); 2322 break; 2323 case Expand: { 2324 SDOperand Lo, Hi; 2325 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 2326 "FIXME: TODO: implement returning non-legal vector types!"); 2327 ExpandOp(Node->getOperand(i), Lo, Hi); 2328 NewValues.push_back(Lo); 2329 NewValues.push_back(Node->getOperand(i+1)); 2330 if (Hi.Val) { 2331 NewValues.push_back(Hi); 2332 NewValues.push_back(Node->getOperand(i+1)); 2333 } 2334 break; 2335 } 2336 case Promote: 2337 assert(0 && "Can't promote multiple return value yet!"); 2338 } 2339 2340 if (NewValues.size() == Node->getNumOperands()) 2341 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2342 else 2343 Result = DAG.getNode(ISD::RET, MVT::Other, 2344 &NewValues[0], NewValues.size()); 2345 break; 2346 } 2347 } 2348 2349 if (Result.getOpcode() == ISD::RET) { 2350 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2351 default: assert(0 && "This action is not supported yet!"); 2352 case TargetLowering::Legal: break; 2353 case TargetLowering::Custom: 2354 Tmp1 = TLI.LowerOperation(Result, DAG); 2355 if (Tmp1.Val) Result = Tmp1; 2356 break; 2357 } 2358 } 2359 break; 2360 case ISD::STORE: { 2361 StoreSDNode *ST = cast<StoreSDNode>(Node); 2362 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2363 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2364 int SVOffset = ST->getSrcValueOffset(); 2365 unsigned Alignment = ST->getAlignment(); 2366 bool isVolatile = ST->isVolatile(); 2367 2368 if (!ST->isTruncatingStore()) { 2369 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2370 // FIXME: We shouldn't do this for TargetConstantFP's. 2371 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2372 // to phase ordering between legalized code and the dag combiner. This 2373 // probably means that we need to integrate dag combiner and legalizer 2374 // together. 2375 // We generally can't do this one for long doubles. 2376 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2377 if (CFP->getValueType(0) == MVT::f32 && 2378 getTypeAction(MVT::i32) == Legal) { 2379 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2380 convertToAPInt().zextOrTrunc(32), 2381 MVT::i32); 2382 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2383 SVOffset, isVolatile, Alignment); 2384 break; 2385 } else if (CFP->getValueType(0) == MVT::f64) { 2386 // If this target supports 64-bit registers, do a single 64-bit store. 2387 if (getTypeAction(MVT::i64) == Legal) { 2388 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2389 zextOrTrunc(64), MVT::i64); 2390 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2391 SVOffset, isVolatile, Alignment); 2392 break; 2393 } else if (getTypeAction(MVT::i32) == Legal) { 2394 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2395 // stores. If the target supports neither 32- nor 64-bits, this 2396 // xform is certainly not worth it. 2397 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2398 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2399 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2400 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2401 2402 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2403 SVOffset, isVolatile, Alignment); 2404 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2405 DAG.getIntPtrConstant(4)); 2406 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2407 isVolatile, MinAlign(Alignment, 4U)); 2408 2409 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2410 break; 2411 } 2412 } 2413 } 2414 2415 switch (getTypeAction(ST->getMemoryVT())) { 2416 case Legal: { 2417 Tmp3 = LegalizeOp(ST->getValue()); 2418 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2419 ST->getOffset()); 2420 2421 MVT::ValueType VT = Tmp3.getValueType(); 2422 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2423 default: assert(0 && "This action is not supported yet!"); 2424 case TargetLowering::Legal: 2425 // If this is an unaligned store and the target doesn't support it, 2426 // expand it. 2427 if (!TLI.allowsUnalignedMemoryAccesses()) { 2428 unsigned ABIAlignment = TLI.getTargetData()-> 2429 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); 2430 if (ST->getAlignment() < ABIAlignment) 2431 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2432 TLI); 2433 } 2434 break; 2435 case TargetLowering::Custom: 2436 Tmp1 = TLI.LowerOperation(Result, DAG); 2437 if (Tmp1.Val) Result = Tmp1; 2438 break; 2439 case TargetLowering::Promote: 2440 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2441 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2442 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2443 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2444 ST->getSrcValue(), SVOffset, isVolatile, 2445 Alignment); 2446 break; 2447 } 2448 break; 2449 } 2450 case Promote: 2451 // Truncate the value and store the result. 2452 Tmp3 = PromoteOp(ST->getValue()); 2453 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2454 SVOffset, ST->getMemoryVT(), 2455 isVolatile, Alignment); 2456 break; 2457 2458 case Expand: 2459 unsigned IncrementSize = 0; 2460 SDOperand Lo, Hi; 2461 2462 // If this is a vector type, then we have to calculate the increment as 2463 // the product of the element size in bytes, and the number of elements 2464 // in the high half of the vector. 2465 if (MVT::isVector(ST->getValue().getValueType())) { 2466 SDNode *InVal = ST->getValue().Val; 2467 int InIx = ST->getValue().ResNo; 2468 MVT::ValueType InVT = InVal->getValueType(InIx); 2469 unsigned NumElems = MVT::getVectorNumElements(InVT); 2470 MVT::ValueType EVT = MVT::getVectorElementType(InVT); 2471 2472 // Figure out if there is a simple type corresponding to this Vector 2473 // type. If so, convert to the vector type. 2474 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2475 if (TLI.isTypeLegal(TVT)) { 2476 // Turn this into a normal store of the vector type. 2477 Tmp3 = LegalizeOp(ST->getValue()); 2478 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2479 SVOffset, isVolatile, Alignment); 2480 Result = LegalizeOp(Result); 2481 break; 2482 } else if (NumElems == 1) { 2483 // Turn this into a normal store of the scalar type. 2484 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2485 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2486 SVOffset, isVolatile, Alignment); 2487 // The scalarized value type may not be legal, e.g. it might require 2488 // promotion or expansion. Relegalize the scalar store. 2489 Result = LegalizeOp(Result); 2490 break; 2491 } else { 2492 SplitVectorOp(ST->getValue(), Lo, Hi); 2493 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 2494 MVT::getSizeInBits(EVT)/8; 2495 } 2496 } else { 2497 ExpandOp(ST->getValue(), Lo, Hi); 2498 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2499 2500 if (TLI.isBigEndian()) 2501 std::swap(Lo, Hi); 2502 } 2503 2504 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2505 SVOffset, isVolatile, Alignment); 2506 2507 if (Hi.Val == NULL) { 2508 // Must be int <-> float one-to-one expansion. 2509 Result = Lo; 2510 break; 2511 } 2512 2513 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2514 DAG.getIntPtrConstant(IncrementSize)); 2515 assert(isTypeLegal(Tmp2.getValueType()) && 2516 "Pointers must be legal!"); 2517 SVOffset += IncrementSize; 2518 Alignment = MinAlign(Alignment, IncrementSize); 2519 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2520 SVOffset, isVolatile, Alignment); 2521 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2522 break; 2523 } 2524 } else { 2525 switch (getTypeAction(ST->getValue().getValueType())) { 2526 case Legal: 2527 Tmp3 = LegalizeOp(ST->getValue()); 2528 break; 2529 case Promote: 2530 // We can promote the value, the truncstore will still take care of it. 2531 Tmp3 = PromoteOp(ST->getValue()); 2532 break; 2533 case Expand: 2534 // Just store the low part. This may become a non-trunc store, so make 2535 // sure to use getTruncStore, not UpdateNodeOperands below. 2536 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2537 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2538 SVOffset, MVT::i8, isVolatile, Alignment); 2539 } 2540 2541 MVT::ValueType StVT = ST->getMemoryVT(); 2542 unsigned StWidth = MVT::getSizeInBits(StVT); 2543 2544 if (StWidth != MVT::getStoreSizeInBits(StVT)) { 2545 // Promote to a byte-sized store with upper bits zero if not 2546 // storing an integral number of bytes. For example, promote 2547 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2548 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT)); 2549 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2550 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2551 SVOffset, NVT, isVolatile, Alignment); 2552 } else if (StWidth & (StWidth - 1)) { 2553 // If not storing a power-of-2 number of bits, expand as two stores. 2554 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) && 2555 "Unsupported truncstore!"); 2556 unsigned RoundWidth = 1 << Log2_32(StWidth); 2557 assert(RoundWidth < StWidth); 2558 unsigned ExtraWidth = StWidth - RoundWidth; 2559 assert(ExtraWidth < RoundWidth); 2560 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2561 "Store size not an integral number of bytes!"); 2562 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); 2563 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); 2564 SDOperand Lo, Hi; 2565 unsigned IncrementSize; 2566 2567 if (TLI.isLittleEndian()) { 2568 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2569 // Store the bottom RoundWidth bits. 2570 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2571 SVOffset, RoundVT, 2572 isVolatile, Alignment); 2573 2574 // Store the remaining ExtraWidth bits. 2575 IncrementSize = RoundWidth / 8; 2576 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2577 DAG.getIntPtrConstant(IncrementSize)); 2578 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2579 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2580 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2581 SVOffset + IncrementSize, ExtraVT, isVolatile, 2582 MinAlign(Alignment, IncrementSize)); 2583 } else { 2584 // Big endian - avoid unaligned stores. 2585 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2586 // Store the top RoundWidth bits. 2587 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2588 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2589 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2590 RoundVT, isVolatile, Alignment); 2591 2592 // Store the remaining ExtraWidth bits. 2593 IncrementSize = RoundWidth / 8; 2594 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2595 DAG.getIntPtrConstant(IncrementSize)); 2596 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2597 SVOffset + IncrementSize, ExtraVT, isVolatile, 2598 MinAlign(Alignment, IncrementSize)); 2599 } 2600 2601 // The order of the stores doesn't matter. 2602 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2603 } else { 2604 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2605 Tmp2 != ST->getBasePtr()) 2606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2607 ST->getOffset()); 2608 2609 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2610 default: assert(0 && "This action is not supported yet!"); 2611 case TargetLowering::Legal: 2612 // If this is an unaligned store and the target doesn't support it, 2613 // expand it. 2614 if (!TLI.allowsUnalignedMemoryAccesses()) { 2615 unsigned ABIAlignment = TLI.getTargetData()-> 2616 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); 2617 if (ST->getAlignment() < ABIAlignment) 2618 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2619 TLI); 2620 } 2621 break; 2622 case TargetLowering::Custom: 2623 Result = TLI.LowerOperation(Result, DAG); 2624 break; 2625 case Expand: 2626 // TRUNCSTORE:i16 i32 -> STORE i16 2627 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2628 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2629 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2630 isVolatile, Alignment); 2631 break; 2632 } 2633 } 2634 } 2635 break; 2636 } 2637 case ISD::PCMARKER: 2638 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2640 break; 2641 case ISD::STACKSAVE: 2642 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2643 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2644 Tmp1 = Result.getValue(0); 2645 Tmp2 = Result.getValue(1); 2646 2647 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2648 default: assert(0 && "This action is not supported yet!"); 2649 case TargetLowering::Legal: break; 2650 case TargetLowering::Custom: 2651 Tmp3 = TLI.LowerOperation(Result, DAG); 2652 if (Tmp3.Val) { 2653 Tmp1 = LegalizeOp(Tmp3); 2654 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2655 } 2656 break; 2657 case TargetLowering::Expand: 2658 // Expand to CopyFromReg if the target set 2659 // StackPointerRegisterToSaveRestore. 2660 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2661 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2662 Node->getValueType(0)); 2663 Tmp2 = Tmp1.getValue(1); 2664 } else { 2665 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2666 Tmp2 = Node->getOperand(0); 2667 } 2668 break; 2669 } 2670 2671 // Since stacksave produce two values, make sure to remember that we 2672 // legalized both of them. 2673 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2674 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2675 return Op.ResNo ? Tmp2 : Tmp1; 2676 2677 case ISD::STACKRESTORE: 2678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2680 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2681 2682 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2683 default: assert(0 && "This action is not supported yet!"); 2684 case TargetLowering::Legal: break; 2685 case TargetLowering::Custom: 2686 Tmp1 = TLI.LowerOperation(Result, DAG); 2687 if (Tmp1.Val) Result = Tmp1; 2688 break; 2689 case TargetLowering::Expand: 2690 // Expand to CopyToReg if the target set 2691 // StackPointerRegisterToSaveRestore. 2692 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2693 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2694 } else { 2695 Result = Tmp1; 2696 } 2697 break; 2698 } 2699 break; 2700 2701 case ISD::READCYCLECOUNTER: 2702 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2703 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2704 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2705 Node->getValueType(0))) { 2706 default: assert(0 && "This action is not supported yet!"); 2707 case TargetLowering::Legal: 2708 Tmp1 = Result.getValue(0); 2709 Tmp2 = Result.getValue(1); 2710 break; 2711 case TargetLowering::Custom: 2712 Result = TLI.LowerOperation(Result, DAG); 2713 Tmp1 = LegalizeOp(Result.getValue(0)); 2714 Tmp2 = LegalizeOp(Result.getValue(1)); 2715 break; 2716 } 2717 2718 // Since rdcc produce two values, make sure to remember that we legalized 2719 // both of them. 2720 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2721 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2722 return Result; 2723 2724 case ISD::SELECT: 2725 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2726 case Expand: assert(0 && "It's impossible to expand bools"); 2727 case Legal: 2728 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2729 break; 2730 case Promote: { 2731 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2732 // Make sure the condition is either zero or one. 2733 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2734 if (!DAG.MaskedValueIsZero(Tmp1, 2735 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2736 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2737 break; 2738 } 2739 } 2740 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2741 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2742 2743 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2744 2745 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2746 default: assert(0 && "This action is not supported yet!"); 2747 case TargetLowering::Legal: break; 2748 case TargetLowering::Custom: { 2749 Tmp1 = TLI.LowerOperation(Result, DAG); 2750 if (Tmp1.Val) Result = Tmp1; 2751 break; 2752 } 2753 case TargetLowering::Expand: 2754 if (Tmp1.getOpcode() == ISD::SETCC) { 2755 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2756 Tmp2, Tmp3, 2757 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2758 } else { 2759 Result = DAG.getSelectCC(Tmp1, 2760 DAG.getConstant(0, Tmp1.getValueType()), 2761 Tmp2, Tmp3, ISD::SETNE); 2762 } 2763 break; 2764 case TargetLowering::Promote: { 2765 MVT::ValueType NVT = 2766 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2767 unsigned ExtOp, TruncOp; 2768 if (MVT::isVector(Tmp2.getValueType())) { 2769 ExtOp = ISD::BIT_CONVERT; 2770 TruncOp = ISD::BIT_CONVERT; 2771 } else if (MVT::isInteger(Tmp2.getValueType())) { 2772 ExtOp = ISD::ANY_EXTEND; 2773 TruncOp = ISD::TRUNCATE; 2774 } else { 2775 ExtOp = ISD::FP_EXTEND; 2776 TruncOp = ISD::FP_ROUND; 2777 } 2778 // Promote each of the values to the new type. 2779 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2780 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2781 // Perform the larger operation, then round down. 2782 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2783 if (TruncOp != ISD::FP_ROUND) 2784 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2785 else 2786 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2787 DAG.getIntPtrConstant(0)); 2788 break; 2789 } 2790 } 2791 break; 2792 case ISD::SELECT_CC: { 2793 Tmp1 = Node->getOperand(0); // LHS 2794 Tmp2 = Node->getOperand(1); // RHS 2795 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2796 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2797 SDOperand CC = Node->getOperand(4); 2798 2799 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2800 2801 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2802 // the LHS is a legal SETCC itself. In this case, we need to compare 2803 // the result against zero to select between true and false values. 2804 if (Tmp2.Val == 0) { 2805 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2806 CC = DAG.getCondCode(ISD::SETNE); 2807 } 2808 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2809 2810 // Everything is legal, see if we should expand this op or something. 2811 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2812 default: assert(0 && "This action is not supported yet!"); 2813 case TargetLowering::Legal: break; 2814 case TargetLowering::Custom: 2815 Tmp1 = TLI.LowerOperation(Result, DAG); 2816 if (Tmp1.Val) Result = Tmp1; 2817 break; 2818 } 2819 break; 2820 } 2821 case ISD::SETCC: 2822 Tmp1 = Node->getOperand(0); 2823 Tmp2 = Node->getOperand(1); 2824 Tmp3 = Node->getOperand(2); 2825 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2826 2827 // If we had to Expand the SetCC operands into a SELECT node, then it may 2828 // not always be possible to return a true LHS & RHS. In this case, just 2829 // return the value we legalized, returned in the LHS 2830 if (Tmp2.Val == 0) { 2831 Result = Tmp1; 2832 break; 2833 } 2834 2835 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2836 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2837 case TargetLowering::Custom: 2838 isCustom = true; 2839 // FALLTHROUGH. 2840 case TargetLowering::Legal: 2841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2842 if (isCustom) { 2843 Tmp4 = TLI.LowerOperation(Result, DAG); 2844 if (Tmp4.Val) Result = Tmp4; 2845 } 2846 break; 2847 case TargetLowering::Promote: { 2848 // First step, figure out the appropriate operation to use. 2849 // Allow SETCC to not be supported for all legal data types 2850 // Mostly this targets FP 2851 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2852 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2853 2854 // Scan for the appropriate larger type to use. 2855 while (1) { 2856 NewInTy = (MVT::ValueType)(NewInTy+1); 2857 2858 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2859 "Fell off of the edge of the integer world"); 2860 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2861 "Fell off of the edge of the floating point world"); 2862 2863 // If the target supports SETCC of this type, use it. 2864 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2865 break; 2866 } 2867 if (MVT::isInteger(NewInTy)) 2868 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2869 else { 2870 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2871 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2872 } 2873 Tmp1 = LegalizeOp(Tmp1); 2874 Tmp2 = LegalizeOp(Tmp2); 2875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2876 Result = LegalizeOp(Result); 2877 break; 2878 } 2879 case TargetLowering::Expand: 2880 // Expand a setcc node into a select_cc of the same condition, lhs, and 2881 // rhs that selects between const 1 (true) and const 0 (false). 2882 MVT::ValueType VT = Node->getValueType(0); 2883 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2884 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2885 Tmp3); 2886 break; 2887 } 2888 break; 2889 2890 case ISD::SHL_PARTS: 2891 case ISD::SRA_PARTS: 2892 case ISD::SRL_PARTS: { 2893 SmallVector<SDOperand, 8> Ops; 2894 bool Changed = false; 2895 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2896 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2897 Changed |= Ops.back() != Node->getOperand(i); 2898 } 2899 if (Changed) 2900 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2901 2902 switch (TLI.getOperationAction(Node->getOpcode(), 2903 Node->getValueType(0))) { 2904 default: assert(0 && "This action is not supported yet!"); 2905 case TargetLowering::Legal: break; 2906 case TargetLowering::Custom: 2907 Tmp1 = TLI.LowerOperation(Result, DAG); 2908 if (Tmp1.Val) { 2909 SDOperand Tmp2, RetVal(0, 0); 2910 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2911 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2912 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2913 if (i == Op.ResNo) 2914 RetVal = Tmp2; 2915 } 2916 assert(RetVal.Val && "Illegal result number"); 2917 return RetVal; 2918 } 2919 break; 2920 } 2921 2922 // Since these produce multiple values, make sure to remember that we 2923 // legalized all of them. 2924 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2925 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2926 return Result.getValue(Op.ResNo); 2927 } 2928 2929 // Binary operators 2930 case ISD::ADD: 2931 case ISD::SUB: 2932 case ISD::MUL: 2933 case ISD::MULHS: 2934 case ISD::MULHU: 2935 case ISD::UDIV: 2936 case ISD::SDIV: 2937 case ISD::AND: 2938 case ISD::OR: 2939 case ISD::XOR: 2940 case ISD::SHL: 2941 case ISD::SRL: 2942 case ISD::SRA: 2943 case ISD::FADD: 2944 case ISD::FSUB: 2945 case ISD::FMUL: 2946 case ISD::FDIV: 2947 case ISD::FPOW: 2948 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2949 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2950 case Expand: assert(0 && "Not possible"); 2951 case Legal: 2952 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2953 break; 2954 case Promote: 2955 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2956 break; 2957 } 2958 2959 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2960 2961 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2962 default: assert(0 && "BinOp legalize operation not supported"); 2963 case TargetLowering::Legal: break; 2964 case TargetLowering::Custom: 2965 Tmp1 = TLI.LowerOperation(Result, DAG); 2966 if (Tmp1.Val) Result = Tmp1; 2967 break; 2968 case TargetLowering::Expand: { 2969 MVT::ValueType VT = Op.getValueType(); 2970 2971 // See if multiply or divide can be lowered using two-result operations. 2972 SDVTList VTs = DAG.getVTList(VT, VT); 2973 if (Node->getOpcode() == ISD::MUL) { 2974 // We just need the low half of the multiply; try both the signed 2975 // and unsigned forms. If the target supports both SMUL_LOHI and 2976 // UMUL_LOHI, form a preference by checking which forms of plain 2977 // MULH it supports. 2978 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2979 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2980 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2981 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2982 unsigned OpToUse = 0; 2983 if (HasSMUL_LOHI && !HasMULHS) { 2984 OpToUse = ISD::SMUL_LOHI; 2985 } else if (HasUMUL_LOHI && !HasMULHU) { 2986 OpToUse = ISD::UMUL_LOHI; 2987 } else if (HasSMUL_LOHI) { 2988 OpToUse = ISD::SMUL_LOHI; 2989 } else if (HasUMUL_LOHI) { 2990 OpToUse = ISD::UMUL_LOHI; 2991 } 2992 if (OpToUse) { 2993 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2994 break; 2995 } 2996 } 2997 if (Node->getOpcode() == ISD::MULHS && 2998 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2999 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3000 break; 3001 } 3002 if (Node->getOpcode() == ISD::MULHU && 3003 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3004 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3005 break; 3006 } 3007 if (Node->getOpcode() == ISD::SDIV && 3008 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3009 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3010 break; 3011 } 3012 if (Node->getOpcode() == ISD::UDIV && 3013 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3014 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3015 break; 3016 } 3017 3018 // Check to see if we have a libcall for this operator. 3019 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3020 bool isSigned = false; 3021 switch (Node->getOpcode()) { 3022 case ISD::UDIV: 3023 case ISD::SDIV: 3024 if (VT == MVT::i32) { 3025 LC = Node->getOpcode() == ISD::UDIV 3026 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3027 isSigned = Node->getOpcode() == ISD::SDIV; 3028 } 3029 break; 3030 case ISD::FPOW: 3031 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3032 RTLIB::POW_PPCF128); 3033 break; 3034 default: break; 3035 } 3036 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3037 SDOperand Dummy; 3038 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3039 break; 3040 } 3041 3042 assert(MVT::isVector(Node->getValueType(0)) && 3043 "Cannot expand this binary operator!"); 3044 // Expand the operation into a bunch of nasty scalar code. 3045 Result = LegalizeOp(UnrollVectorOp(Op)); 3046 break; 3047 } 3048 case TargetLowering::Promote: { 3049 switch (Node->getOpcode()) { 3050 default: assert(0 && "Do not know how to promote this BinOp!"); 3051 case ISD::AND: 3052 case ISD::OR: 3053 case ISD::XOR: { 3054 MVT::ValueType OVT = Node->getValueType(0); 3055 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3056 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 3057 // Bit convert each of the values to the new type. 3058 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3059 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3060 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3061 // Bit convert the result back the original type. 3062 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3063 break; 3064 } 3065 } 3066 } 3067 } 3068 break; 3069 3070 case ISD::SMUL_LOHI: 3071 case ISD::UMUL_LOHI: 3072 case ISD::SDIVREM: 3073 case ISD::UDIVREM: 3074 // These nodes will only be produced by target-specific lowering, so 3075 // they shouldn't be here if they aren't legal. 3076 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3077 "This must be legal!"); 3078 3079 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3080 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3081 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3082 break; 3083 3084 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3085 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3086 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3087 case Expand: assert(0 && "Not possible"); 3088 case Legal: 3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3090 break; 3091 case Promote: 3092 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3093 break; 3094 } 3095 3096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3097 3098 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3099 default: assert(0 && "Operation not supported"); 3100 case TargetLowering::Custom: 3101 Tmp1 = TLI.LowerOperation(Result, DAG); 3102 if (Tmp1.Val) Result = Tmp1; 3103 break; 3104 case TargetLowering::Legal: break; 3105 case TargetLowering::Expand: { 3106 // If this target supports fabs/fneg natively and select is cheap, 3107 // do this efficiently. 3108 if (!TLI.isSelectExpensive() && 3109 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3110 TargetLowering::Legal && 3111 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3112 TargetLowering::Legal) { 3113 // Get the sign bit of the RHS. 3114 MVT::ValueType IVT = 3115 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3116 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3117 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3118 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3119 // Get the absolute value of the result. 3120 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3121 // Select between the nabs and abs value based on the sign bit of 3122 // the input. 3123 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3124 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3125 AbsVal), 3126 AbsVal); 3127 Result = LegalizeOp(Result); 3128 break; 3129 } 3130 3131 // Otherwise, do bitwise ops! 3132 MVT::ValueType NVT = 3133 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3134 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3135 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3136 Result = LegalizeOp(Result); 3137 break; 3138 } 3139 } 3140 break; 3141 3142 case ISD::ADDC: 3143 case ISD::SUBC: 3144 Tmp1 = LegalizeOp(Node->getOperand(0)); 3145 Tmp2 = LegalizeOp(Node->getOperand(1)); 3146 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3147 // Since this produces two values, make sure to remember that we legalized 3148 // both of them. 3149 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3150 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3151 return Result; 3152 3153 case ISD::ADDE: 3154 case ISD::SUBE: 3155 Tmp1 = LegalizeOp(Node->getOperand(0)); 3156 Tmp2 = LegalizeOp(Node->getOperand(1)); 3157 Tmp3 = LegalizeOp(Node->getOperand(2)); 3158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3159 // Since this produces two values, make sure to remember that we legalized 3160 // both of them. 3161 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3162 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3163 return Result; 3164 3165 case ISD::BUILD_PAIR: { 3166 MVT::ValueType PairTy = Node->getValueType(0); 3167 // TODO: handle the case where the Lo and Hi operands are not of legal type 3168 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3169 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3170 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3171 case TargetLowering::Promote: 3172 case TargetLowering::Custom: 3173 assert(0 && "Cannot promote/custom this yet!"); 3174 case TargetLowering::Legal: 3175 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3176 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3177 break; 3178 case TargetLowering::Expand: 3179 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3180 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3181 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3182 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 3183 TLI.getShiftAmountTy())); 3184 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3185 break; 3186 } 3187 break; 3188 } 3189 3190 case ISD::UREM: 3191 case ISD::SREM: 3192 case ISD::FREM: 3193 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3194 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3195 3196 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3197 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3198 case TargetLowering::Custom: 3199 isCustom = true; 3200 // FALLTHROUGH 3201 case TargetLowering::Legal: 3202 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3203 if (isCustom) { 3204 Tmp1 = TLI.LowerOperation(Result, DAG); 3205 if (Tmp1.Val) Result = Tmp1; 3206 } 3207 break; 3208 case TargetLowering::Expand: { 3209 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3210 bool isSigned = DivOpc == ISD::SDIV; 3211 MVT::ValueType VT = Node->getValueType(0); 3212 3213 // See if remainder can be lowered using two-result operations. 3214 SDVTList VTs = DAG.getVTList(VT, VT); 3215 if (Node->getOpcode() == ISD::SREM && 3216 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3217 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3218 break; 3219 } 3220 if (Node->getOpcode() == ISD::UREM && 3221 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3222 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3223 break; 3224 } 3225 3226 if (MVT::isInteger(VT)) { 3227 if (TLI.getOperationAction(DivOpc, VT) == 3228 TargetLowering::Legal) { 3229 // X % Y -> X-X/Y*Y 3230 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3231 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3232 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3233 } else if (MVT::isVector(VT)) { 3234 Result = LegalizeOp(UnrollVectorOp(Op)); 3235 } else { 3236 assert(VT == MVT::i32 && 3237 "Cannot expand this binary operator!"); 3238 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3239 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3240 SDOperand Dummy; 3241 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3242 } 3243 } else { 3244 assert(MVT::isFloatingPoint(VT) && 3245 "remainder op must have integer or floating-point type"); 3246 if (MVT::isVector(VT)) { 3247 Result = LegalizeOp(UnrollVectorOp(Op)); 3248 } else { 3249 // Floating point mod -> fmod libcall. 3250 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3251 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3252 SDOperand Dummy; 3253 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3254 } 3255 } 3256 break; 3257 } 3258 } 3259 break; 3260 case ISD::VAARG: { 3261 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3262 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3263 3264 MVT::ValueType VT = Node->getValueType(0); 3265 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3266 default: assert(0 && "This action is not supported yet!"); 3267 case TargetLowering::Custom: 3268 isCustom = true; 3269 // FALLTHROUGH 3270 case TargetLowering::Legal: 3271 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3272 Result = Result.getValue(0); 3273 Tmp1 = Result.getValue(1); 3274 3275 if (isCustom) { 3276 Tmp2 = TLI.LowerOperation(Result, DAG); 3277 if (Tmp2.Val) { 3278 Result = LegalizeOp(Tmp2); 3279 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3280 } 3281 } 3282 break; 3283 case TargetLowering::Expand: { 3284 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3285 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3286 // Increment the pointer, VAList, to the next vaarg 3287 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3288 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3289 TLI.getPointerTy())); 3290 // Store the incremented VAList to the legalized pointer 3291 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3292 // Load the actual argument out of the pointer VAList 3293 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3294 Tmp1 = LegalizeOp(Result.getValue(1)); 3295 Result = LegalizeOp(Result); 3296 break; 3297 } 3298 } 3299 // Since VAARG produces two values, make sure to remember that we 3300 // legalized both of them. 3301 AddLegalizedOperand(SDOperand(Node, 0), Result); 3302 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3303 return Op.ResNo ? Tmp1 : Result; 3304 } 3305 3306 case ISD::VACOPY: 3307 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3308 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3309 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3310 3311 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3312 default: assert(0 && "This action is not supported yet!"); 3313 case TargetLowering::Custom: 3314 isCustom = true; 3315 // FALLTHROUGH 3316 case TargetLowering::Legal: 3317 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3318 Node->getOperand(3), Node->getOperand(4)); 3319 if (isCustom) { 3320 Tmp1 = TLI.LowerOperation(Result, DAG); 3321 if (Tmp1.Val) Result = Tmp1; 3322 } 3323 break; 3324 case TargetLowering::Expand: 3325 // This defaults to loading a pointer from the input and storing it to the 3326 // output, returning the chain. 3327 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3328 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3329 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3330 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3331 break; 3332 } 3333 break; 3334 3335 case ISD::VAEND: 3336 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3337 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3338 3339 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3340 default: assert(0 && "This action is not supported yet!"); 3341 case TargetLowering::Custom: 3342 isCustom = true; 3343 // FALLTHROUGH 3344 case TargetLowering::Legal: 3345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3346 if (isCustom) { 3347 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3348 if (Tmp1.Val) Result = Tmp1; 3349 } 3350 break; 3351 case TargetLowering::Expand: 3352 Result = Tmp1; // Default to a no-op, return the chain 3353 break; 3354 } 3355 break; 3356 3357 case ISD::VASTART: 3358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3359 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3360 3361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3362 3363 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3364 default: assert(0 && "This action is not supported yet!"); 3365 case TargetLowering::Legal: break; 3366 case TargetLowering::Custom: 3367 Tmp1 = TLI.LowerOperation(Result, DAG); 3368 if (Tmp1.Val) Result = Tmp1; 3369 break; 3370 } 3371 break; 3372 3373 case ISD::ROTL: 3374 case ISD::ROTR: 3375 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3376 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3378 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3379 default: 3380 assert(0 && "ROTL/ROTR legalize operation not supported"); 3381 break; 3382 case TargetLowering::Legal: 3383 break; 3384 case TargetLowering::Custom: 3385 Tmp1 = TLI.LowerOperation(Result, DAG); 3386 if (Tmp1.Val) Result = Tmp1; 3387 break; 3388 case TargetLowering::Promote: 3389 assert(0 && "Do not know how to promote ROTL/ROTR"); 3390 break; 3391 case TargetLowering::Expand: 3392 assert(0 && "Do not know how to expand ROTL/ROTR"); 3393 break; 3394 } 3395 break; 3396 3397 case ISD::BSWAP: 3398 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3399 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3400 case TargetLowering::Custom: 3401 assert(0 && "Cannot custom legalize this yet!"); 3402 case TargetLowering::Legal: 3403 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3404 break; 3405 case TargetLowering::Promote: { 3406 MVT::ValueType OVT = Tmp1.getValueType(); 3407 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3408 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3409 3410 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3411 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3412 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3413 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3414 break; 3415 } 3416 case TargetLowering::Expand: 3417 Result = ExpandBSWAP(Tmp1); 3418 break; 3419 } 3420 break; 3421 3422 case ISD::CTPOP: 3423 case ISD::CTTZ: 3424 case ISD::CTLZ: 3425 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3426 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3427 case TargetLowering::Custom: 3428 case TargetLowering::Legal: 3429 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3430 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3431 TargetLowering::Custom) { 3432 Tmp1 = TLI.LowerOperation(Result, DAG); 3433 if (Tmp1.Val) { 3434 Result = Tmp1; 3435 } 3436 } 3437 break; 3438 case TargetLowering::Promote: { 3439 MVT::ValueType OVT = Tmp1.getValueType(); 3440 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3441 3442 // Zero extend the argument. 3443 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3444 // Perform the larger operation, then subtract if needed. 3445 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3446 switch (Node->getOpcode()) { 3447 case ISD::CTPOP: 3448 Result = Tmp1; 3449 break; 3450 case ISD::CTTZ: 3451 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3452 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3453 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3454 ISD::SETEQ); 3455 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3456 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3457 break; 3458 case ISD::CTLZ: 3459 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3460 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3461 DAG.getConstant(MVT::getSizeInBits(NVT) - 3462 MVT::getSizeInBits(OVT), NVT)); 3463 break; 3464 } 3465 break; 3466 } 3467 case TargetLowering::Expand: 3468 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3469 break; 3470 } 3471 break; 3472 3473 // Unary operators 3474 case ISD::FABS: 3475 case ISD::FNEG: 3476 case ISD::FSQRT: 3477 case ISD::FSIN: 3478 case ISD::FCOS: 3479 Tmp1 = LegalizeOp(Node->getOperand(0)); 3480 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3481 case TargetLowering::Promote: 3482 case TargetLowering::Custom: 3483 isCustom = true; 3484 // FALLTHROUGH 3485 case TargetLowering::Legal: 3486 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3487 if (isCustom) { 3488 Tmp1 = TLI.LowerOperation(Result, DAG); 3489 if (Tmp1.Val) Result = Tmp1; 3490 } 3491 break; 3492 case TargetLowering::Expand: 3493 switch (Node->getOpcode()) { 3494 default: assert(0 && "Unreachable!"); 3495 case ISD::FNEG: 3496 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3497 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3498 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3499 break; 3500 case ISD::FABS: { 3501 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3502 MVT::ValueType VT = Node->getValueType(0); 3503 Tmp2 = DAG.getConstantFP(0.0, VT); 3504 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3505 ISD::SETUGT); 3506 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3507 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3508 break; 3509 } 3510 case ISD::FSQRT: 3511 case ISD::FSIN: 3512 case ISD::FCOS: { 3513 MVT::ValueType VT = Node->getValueType(0); 3514 3515 // Expand unsupported unary vector operators by unrolling them. 3516 if (MVT::isVector(VT)) { 3517 Result = LegalizeOp(UnrollVectorOp(Op)); 3518 break; 3519 } 3520 3521 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3522 switch(Node->getOpcode()) { 3523 case ISD::FSQRT: 3524 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3525 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3526 break; 3527 case ISD::FSIN: 3528 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3529 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3530 break; 3531 case ISD::FCOS: 3532 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3533 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3534 break; 3535 default: assert(0 && "Unreachable!"); 3536 } 3537 SDOperand Dummy; 3538 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3539 break; 3540 } 3541 } 3542 break; 3543 } 3544 break; 3545 case ISD::FPOWI: { 3546 MVT::ValueType VT = Node->getValueType(0); 3547 3548 // Expand unsupported unary vector operators by unrolling them. 3549 if (MVT::isVector(VT)) { 3550 Result = LegalizeOp(UnrollVectorOp(Op)); 3551 break; 3552 } 3553 3554 // We always lower FPOWI into a libcall. No target support for it yet. 3555 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3556 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3557 SDOperand Dummy; 3558 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3559 break; 3560 } 3561 case ISD::BIT_CONVERT: 3562 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3563 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3564 Node->getValueType(0)); 3565 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3566 // The input has to be a vector type, we have to either scalarize it, pack 3567 // it, or convert it based on whether the input vector type is legal. 3568 SDNode *InVal = Node->getOperand(0).Val; 3569 int InIx = Node->getOperand(0).ResNo; 3570 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3571 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3572 3573 // Figure out if there is a simple type corresponding to this Vector 3574 // type. If so, convert to the vector type. 3575 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3576 if (TLI.isTypeLegal(TVT)) { 3577 // Turn this into a bit convert of the vector input. 3578 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3579 LegalizeOp(Node->getOperand(0))); 3580 break; 3581 } else if (NumElems == 1) { 3582 // Turn this into a bit convert of the scalar input. 3583 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3584 ScalarizeVectorOp(Node->getOperand(0))); 3585 break; 3586 } else { 3587 // FIXME: UNIMP! Store then reload 3588 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3589 } 3590 } else { 3591 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3592 Node->getOperand(0).getValueType())) { 3593 default: assert(0 && "Unknown operation action!"); 3594 case TargetLowering::Expand: 3595 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3596 Node->getValueType(0)); 3597 break; 3598 case TargetLowering::Legal: 3599 Tmp1 = LegalizeOp(Node->getOperand(0)); 3600 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3601 break; 3602 } 3603 } 3604 break; 3605 3606 // Conversion operators. The source and destination have different types. 3607 case ISD::SINT_TO_FP: 3608 case ISD::UINT_TO_FP: { 3609 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3610 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3611 case Legal: 3612 switch (TLI.getOperationAction(Node->getOpcode(), 3613 Node->getOperand(0).getValueType())) { 3614 default: assert(0 && "Unknown operation action!"); 3615 case TargetLowering::Custom: 3616 isCustom = true; 3617 // FALLTHROUGH 3618 case TargetLowering::Legal: 3619 Tmp1 = LegalizeOp(Node->getOperand(0)); 3620 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3621 if (isCustom) { 3622 Tmp1 = TLI.LowerOperation(Result, DAG); 3623 if (Tmp1.Val) Result = Tmp1; 3624 } 3625 break; 3626 case TargetLowering::Expand: 3627 Result = ExpandLegalINT_TO_FP(isSigned, 3628 LegalizeOp(Node->getOperand(0)), 3629 Node->getValueType(0)); 3630 break; 3631 case TargetLowering::Promote: 3632 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3633 Node->getValueType(0), 3634 isSigned); 3635 break; 3636 } 3637 break; 3638 case Expand: 3639 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3640 Node->getValueType(0), Node->getOperand(0)); 3641 break; 3642 case Promote: 3643 Tmp1 = PromoteOp(Node->getOperand(0)); 3644 if (isSigned) { 3645 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3646 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3647 } else { 3648 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3649 Node->getOperand(0).getValueType()); 3650 } 3651 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3652 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3653 break; 3654 } 3655 break; 3656 } 3657 case ISD::TRUNCATE: 3658 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3659 case Legal: 3660 Tmp1 = LegalizeOp(Node->getOperand(0)); 3661 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3662 break; 3663 case Expand: 3664 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3665 3666 // Since the result is legal, we should just be able to truncate the low 3667 // part of the source. 3668 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3669 break; 3670 case Promote: 3671 Result = PromoteOp(Node->getOperand(0)); 3672 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3673 break; 3674 } 3675 break; 3676 3677 case ISD::FP_TO_SINT: 3678 case ISD::FP_TO_UINT: 3679 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3680 case Legal: 3681 Tmp1 = LegalizeOp(Node->getOperand(0)); 3682 3683 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3684 default: assert(0 && "Unknown operation action!"); 3685 case TargetLowering::Custom: 3686 isCustom = true; 3687 // FALLTHROUGH 3688 case TargetLowering::Legal: 3689 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3690 if (isCustom) { 3691 Tmp1 = TLI.LowerOperation(Result, DAG); 3692 if (Tmp1.Val) Result = Tmp1; 3693 } 3694 break; 3695 case TargetLowering::Promote: 3696 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3697 Node->getOpcode() == ISD::FP_TO_SINT); 3698 break; 3699 case TargetLowering::Expand: 3700 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3701 SDOperand True, False; 3702 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3703 MVT::ValueType NVT = Node->getValueType(0); 3704 const uint64_t zero[] = {0, 0}; 3705 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3706 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT)); 3707 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3708 Tmp2 = DAG.getConstantFP(apf, VT); 3709 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3710 Node->getOperand(0), Tmp2, ISD::SETLT); 3711 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3712 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3713 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3714 Tmp2)); 3715 False = DAG.getNode(ISD::XOR, NVT, False, 3716 DAG.getConstant(x, NVT)); 3717 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3718 break; 3719 } else { 3720 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3721 } 3722 break; 3723 } 3724 break; 3725 case Expand: { 3726 MVT::ValueType VT = Op.getValueType(); 3727 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3728 // Convert ppcf128 to i32 3729 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3730 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3731 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3732 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3733 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3734 DAG.getIntPtrConstant(1)); 3735 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3736 } else { 3737 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3738 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3739 Tmp2 = DAG.getConstantFP(apf, OVT); 3740 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3741 // FIXME: generated code sucks. 3742 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3743 DAG.getNode(ISD::ADD, MVT::i32, 3744 DAG.getNode(ISD::FP_TO_SINT, VT, 3745 DAG.getNode(ISD::FSUB, OVT, 3746 Node->getOperand(0), Tmp2)), 3747 DAG.getConstant(0x80000000, MVT::i32)), 3748 DAG.getNode(ISD::FP_TO_SINT, VT, 3749 Node->getOperand(0)), 3750 DAG.getCondCode(ISD::SETGE)); 3751 } 3752 break; 3753 } 3754 // Convert f32 / f64 to i32 / i64 / i128. 3755 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3756 switch (Node->getOpcode()) { 3757 case ISD::FP_TO_SINT: { 3758 if (VT == MVT::i32) { 3759 if (OVT == MVT::f32) 3760 LC = RTLIB::FPTOSINT_F32_I32; 3761 else if (OVT == MVT::f64) 3762 LC = RTLIB::FPTOSINT_F64_I32; 3763 else 3764 assert(0 && "Unexpected i32-to-fp conversion!"); 3765 } else if (VT == MVT::i64) { 3766 if (OVT == MVT::f32) 3767 LC = RTLIB::FPTOSINT_F32_I64; 3768 else if (OVT == MVT::f64) 3769 LC = RTLIB::FPTOSINT_F64_I64; 3770 else if (OVT == MVT::f80) 3771 LC = RTLIB::FPTOSINT_F80_I64; 3772 else if (OVT == MVT::ppcf128) 3773 LC = RTLIB::FPTOSINT_PPCF128_I64; 3774 else 3775 assert(0 && "Unexpected i64-to-fp conversion!"); 3776 } else if (VT == MVT::i128) { 3777 if (OVT == MVT::f32) 3778 LC = RTLIB::FPTOSINT_F32_I128; 3779 else if (OVT == MVT::f64) 3780 LC = RTLIB::FPTOSINT_F64_I128; 3781 else if (OVT == MVT::f80) 3782 LC = RTLIB::FPTOSINT_F80_I128; 3783 else if (OVT == MVT::ppcf128) 3784 LC = RTLIB::FPTOSINT_PPCF128_I128; 3785 else 3786 assert(0 && "Unexpected i128-to-fp conversion!"); 3787 } else { 3788 assert(0 && "Unexpectd int-to-fp conversion!"); 3789 } 3790 break; 3791 } 3792 case ISD::FP_TO_UINT: { 3793 if (VT == MVT::i32) { 3794 if (OVT == MVT::f32) 3795 LC = RTLIB::FPTOUINT_F32_I32; 3796 else if (OVT == MVT::f64) 3797 LC = RTLIB::FPTOUINT_F64_I32; 3798 else if (OVT == MVT::f80) 3799 LC = RTLIB::FPTOUINT_F80_I32; 3800 else 3801 assert(0 && "Unexpected i32-to-fp conversion!"); 3802 } else if (VT == MVT::i64) { 3803 if (OVT == MVT::f32) 3804 LC = RTLIB::FPTOUINT_F32_I64; 3805 else if (OVT == MVT::f64) 3806 LC = RTLIB::FPTOUINT_F64_I64; 3807 else if (OVT == MVT::f80) 3808 LC = RTLIB::FPTOUINT_F80_I64; 3809 else if (OVT == MVT::ppcf128) 3810 LC = RTLIB::FPTOUINT_PPCF128_I64; 3811 else 3812 assert(0 && "Unexpected i64-to-fp conversion!"); 3813 } else if (VT == MVT::i128) { 3814 if (OVT == MVT::f32) 3815 LC = RTLIB::FPTOUINT_F32_I128; 3816 else if (OVT == MVT::f64) 3817 LC = RTLIB::FPTOUINT_F64_I128; 3818 else if (OVT == MVT::f80) 3819 LC = RTLIB::FPTOUINT_F80_I128; 3820 else if (OVT == MVT::ppcf128) 3821 LC = RTLIB::FPTOUINT_PPCF128_I128; 3822 else 3823 assert(0 && "Unexpected i128-to-fp conversion!"); 3824 } else { 3825 assert(0 && "Unexpectd int-to-fp conversion!"); 3826 } 3827 break; 3828 } 3829 default: assert(0 && "Unreachable!"); 3830 } 3831 SDOperand Dummy; 3832 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3833 break; 3834 } 3835 case Promote: 3836 Tmp1 = PromoteOp(Node->getOperand(0)); 3837 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3838 Result = LegalizeOp(Result); 3839 break; 3840 } 3841 break; 3842 3843 case ISD::FP_EXTEND: { 3844 MVT::ValueType DstVT = Op.getValueType(); 3845 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3846 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3847 // The only other way we can lower this is to turn it into a STORE, 3848 // LOAD pair, targetting a temporary location (a stack slot). 3849 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3850 break; 3851 } 3852 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3853 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3854 case Legal: 3855 Tmp1 = LegalizeOp(Node->getOperand(0)); 3856 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3857 break; 3858 case Promote: 3859 Tmp1 = PromoteOp(Node->getOperand(0)); 3860 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3861 break; 3862 } 3863 break; 3864 } 3865 case ISD::FP_ROUND: { 3866 MVT::ValueType DstVT = Op.getValueType(); 3867 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3868 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3869 if (SrcVT == MVT::ppcf128) { 3870 SDOperand Lo; 3871 ExpandOp(Node->getOperand(0), Lo, Result); 3872 // Round it the rest of the way (e.g. to f32) if needed. 3873 if (DstVT!=MVT::f64) 3874 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3875 break; 3876 } 3877 // The only other way we can lower this is to turn it into a STORE, 3878 // LOAD pair, targetting a temporary location (a stack slot). 3879 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3880 break; 3881 } 3882 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3883 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3884 case Legal: 3885 Tmp1 = LegalizeOp(Node->getOperand(0)); 3886 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3887 break; 3888 case Promote: 3889 Tmp1 = PromoteOp(Node->getOperand(0)); 3890 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3891 Node->getOperand(1)); 3892 break; 3893 } 3894 break; 3895 } 3896 case ISD::ANY_EXTEND: 3897 case ISD::ZERO_EXTEND: 3898 case ISD::SIGN_EXTEND: 3899 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3900 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3901 case Legal: 3902 Tmp1 = LegalizeOp(Node->getOperand(0)); 3903 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3904 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3905 TargetLowering::Custom) { 3906 Tmp1 = TLI.LowerOperation(Result, DAG); 3907 if (Tmp1.Val) Result = Tmp1; 3908 } 3909 break; 3910 case Promote: 3911 switch (Node->getOpcode()) { 3912 case ISD::ANY_EXTEND: 3913 Tmp1 = PromoteOp(Node->getOperand(0)); 3914 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3915 break; 3916 case ISD::ZERO_EXTEND: 3917 Result = PromoteOp(Node->getOperand(0)); 3918 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3919 Result = DAG.getZeroExtendInReg(Result, 3920 Node->getOperand(0).getValueType()); 3921 break; 3922 case ISD::SIGN_EXTEND: 3923 Result = PromoteOp(Node->getOperand(0)); 3924 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3925 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3926 Result, 3927 DAG.getValueType(Node->getOperand(0).getValueType())); 3928 break; 3929 } 3930 } 3931 break; 3932 case ISD::FP_ROUND_INREG: 3933 case ISD::SIGN_EXTEND_INREG: { 3934 Tmp1 = LegalizeOp(Node->getOperand(0)); 3935 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3936 3937 // If this operation is not supported, convert it to a shl/shr or load/store 3938 // pair. 3939 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3940 default: assert(0 && "This action not supported for this op yet!"); 3941 case TargetLowering::Legal: 3942 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3943 break; 3944 case TargetLowering::Expand: 3945 // If this is an integer extend and shifts are supported, do that. 3946 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3947 // NOTE: we could fall back on load/store here too for targets without 3948 // SAR. However, it is doubtful that any exist. 3949 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3950 MVT::getSizeInBits(ExtraVT); 3951 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3952 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3953 Node->getOperand(0), ShiftCst); 3954 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3955 Result, ShiftCst); 3956 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3957 // The only way we can lower this is to turn it into a TRUNCSTORE, 3958 // EXTLOAD pair, targetting a temporary location (a stack slot). 3959 3960 // NOTE: there is a choice here between constantly creating new stack 3961 // slots and always reusing the same one. We currently always create 3962 // new ones, as reuse may inhibit scheduling. 3963 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3964 Node->getValueType(0)); 3965 } else { 3966 assert(0 && "Unknown op"); 3967 } 3968 break; 3969 } 3970 break; 3971 } 3972 case ISD::TRAMPOLINE: { 3973 SDOperand Ops[6]; 3974 for (unsigned i = 0; i != 6; ++i) 3975 Ops[i] = LegalizeOp(Node->getOperand(i)); 3976 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3977 // The only option for this node is to custom lower it. 3978 Result = TLI.LowerOperation(Result, DAG); 3979 assert(Result.Val && "Should always custom lower!"); 3980 3981 // Since trampoline produces two values, make sure to remember that we 3982 // legalized both of them. 3983 Tmp1 = LegalizeOp(Result.getValue(1)); 3984 Result = LegalizeOp(Result); 3985 AddLegalizedOperand(SDOperand(Node, 0), Result); 3986 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3987 return Op.ResNo ? Tmp1 : Result; 3988 } 3989 case ISD::FLT_ROUNDS_: { 3990 MVT::ValueType VT = Node->getValueType(0); 3991 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3992 default: assert(0 && "This action not supported for this op yet!"); 3993 case TargetLowering::Custom: 3994 Result = TLI.LowerOperation(Op, DAG); 3995 if (Result.Val) break; 3996 // Fall Thru 3997 case TargetLowering::Legal: 3998 // If this operation is not supported, lower it to constant 1 3999 Result = DAG.getConstant(1, VT); 4000 break; 4001 } 4002 break; 4003 } 4004 case ISD::TRAP: { 4005 MVT::ValueType VT = Node->getValueType(0); 4006 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4007 default: assert(0 && "This action not supported for this op yet!"); 4008 case TargetLowering::Legal: 4009 Tmp1 = LegalizeOp(Node->getOperand(0)); 4010 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4011 break; 4012 case TargetLowering::Custom: 4013 Result = TLI.LowerOperation(Op, DAG); 4014 if (Result.Val) break; 4015 // Fall Thru 4016 case TargetLowering::Expand: 4017 // If this operation is not supported, lower it to 'abort()' call 4018 Tmp1 = LegalizeOp(Node->getOperand(0)); 4019 TargetLowering::ArgListTy Args; 4020 std::pair<SDOperand,SDOperand> CallResult = 4021 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4022 false, false, false, CallingConv::C, false, 4023 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4024 Args, DAG); 4025 Result = CallResult.second; 4026 break; 4027 } 4028 break; 4029 } 4030 } 4031 4032 assert(Result.getValueType() == Op.getValueType() && 4033 "Bad legalization!"); 4034 4035 // Make sure that the generated code is itself legal. 4036 if (Result != Op) 4037 Result = LegalizeOp(Result); 4038 4039 // Note that LegalizeOp may be reentered even from single-use nodes, which 4040 // means that we always must cache transformed nodes. 4041 AddLegalizedOperand(Op, Result); 4042 return Result; 4043} 4044 4045/// PromoteOp - Given an operation that produces a value in an invalid type, 4046/// promote it to compute the value into a larger type. The produced value will 4047/// have the correct bits for the low portion of the register, but no guarantee 4048/// is made about the top bits: it may be zero, sign-extended, or garbage. 4049SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 4050 MVT::ValueType VT = Op.getValueType(); 4051 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4052 assert(getTypeAction(VT) == Promote && 4053 "Caller should expand or legalize operands that are not promotable!"); 4054 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 4055 "Cannot promote to smaller type!"); 4056 4057 SDOperand Tmp1, Tmp2, Tmp3; 4058 SDOperand Result; 4059 SDNode *Node = Op.Val; 4060 4061 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 4062 if (I != PromotedNodes.end()) return I->second; 4063 4064 switch (Node->getOpcode()) { 4065 case ISD::CopyFromReg: 4066 assert(0 && "CopyFromReg must be legal!"); 4067 default: 4068#ifndef NDEBUG 4069 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4070#endif 4071 assert(0 && "Do not know how to promote this operator!"); 4072 abort(); 4073 case ISD::UNDEF: 4074 Result = DAG.getNode(ISD::UNDEF, NVT); 4075 break; 4076 case ISD::Constant: 4077 if (VT != MVT::i1) 4078 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4079 else 4080 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4081 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4082 break; 4083 case ISD::ConstantFP: 4084 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4085 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4086 break; 4087 4088 case ISD::SETCC: 4089 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4090 && "SetCC type is not legal??"); 4091 Result = DAG.getNode(ISD::SETCC, 4092 TLI.getSetCCResultType(Node->getOperand(0)), 4093 Node->getOperand(0), Node->getOperand(1), 4094 Node->getOperand(2)); 4095 break; 4096 4097 case ISD::TRUNCATE: 4098 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4099 case Legal: 4100 Result = LegalizeOp(Node->getOperand(0)); 4101 assert(Result.getValueType() >= NVT && 4102 "This truncation doesn't make sense!"); 4103 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 4104 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4105 break; 4106 case Promote: 4107 // The truncation is not required, because we don't guarantee anything 4108 // about high bits anyway. 4109 Result = PromoteOp(Node->getOperand(0)); 4110 break; 4111 case Expand: 4112 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4113 // Truncate the low part of the expanded value to the result type 4114 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4115 } 4116 break; 4117 case ISD::SIGN_EXTEND: 4118 case ISD::ZERO_EXTEND: 4119 case ISD::ANY_EXTEND: 4120 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4121 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4122 case Legal: 4123 // Input is legal? Just do extend all the way to the larger type. 4124 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4125 break; 4126 case Promote: 4127 // Promote the reg if it's smaller. 4128 Result = PromoteOp(Node->getOperand(0)); 4129 // The high bits are not guaranteed to be anything. Insert an extend. 4130 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4131 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4132 DAG.getValueType(Node->getOperand(0).getValueType())); 4133 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4134 Result = DAG.getZeroExtendInReg(Result, 4135 Node->getOperand(0).getValueType()); 4136 break; 4137 } 4138 break; 4139 case ISD::BIT_CONVERT: 4140 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4141 Node->getValueType(0)); 4142 Result = PromoteOp(Result); 4143 break; 4144 4145 case ISD::FP_EXTEND: 4146 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4147 case ISD::FP_ROUND: 4148 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4149 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4150 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4151 case Legal: 4152 if (Node->getConstantOperandVal(1) == 0) { 4153 // Input is legal? Do an FP_ROUND_INREG. 4154 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4155 DAG.getValueType(VT)); 4156 } else { 4157 // Just remove the truncate, it isn't affecting the value. 4158 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4159 Node->getOperand(1)); 4160 } 4161 break; 4162 } 4163 break; 4164 case ISD::SINT_TO_FP: 4165 case ISD::UINT_TO_FP: 4166 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4167 case Legal: 4168 // No extra round required here. 4169 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4170 break; 4171 4172 case Promote: 4173 Result = PromoteOp(Node->getOperand(0)); 4174 if (Node->getOpcode() == ISD::SINT_TO_FP) 4175 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4176 Result, 4177 DAG.getValueType(Node->getOperand(0).getValueType())); 4178 else 4179 Result = DAG.getZeroExtendInReg(Result, 4180 Node->getOperand(0).getValueType()); 4181 // No extra round required here. 4182 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4183 break; 4184 case Expand: 4185 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4186 Node->getOperand(0)); 4187 // Round if we cannot tolerate excess precision. 4188 if (NoExcessFPPrecision) 4189 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4190 DAG.getValueType(VT)); 4191 break; 4192 } 4193 break; 4194 4195 case ISD::SIGN_EXTEND_INREG: 4196 Result = PromoteOp(Node->getOperand(0)); 4197 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4198 Node->getOperand(1)); 4199 break; 4200 case ISD::FP_TO_SINT: 4201 case ISD::FP_TO_UINT: 4202 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4203 case Legal: 4204 case Expand: 4205 Tmp1 = Node->getOperand(0); 4206 break; 4207 case Promote: 4208 // The input result is prerounded, so we don't have to do anything 4209 // special. 4210 Tmp1 = PromoteOp(Node->getOperand(0)); 4211 break; 4212 } 4213 // If we're promoting a UINT to a larger size, check to see if the new node 4214 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4215 // we can use that instead. This allows us to generate better code for 4216 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4217 // legal, such as PowerPC. 4218 if (Node->getOpcode() == ISD::FP_TO_UINT && 4219 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4220 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4221 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4222 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4223 } else { 4224 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4225 } 4226 break; 4227 4228 case ISD::FABS: 4229 case ISD::FNEG: 4230 Tmp1 = PromoteOp(Node->getOperand(0)); 4231 assert(Tmp1.getValueType() == NVT); 4232 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4233 // NOTE: we do not have to do any extra rounding here for 4234 // NoExcessFPPrecision, because we know the input will have the appropriate 4235 // precision, and these operations don't modify precision at all. 4236 break; 4237 4238 case ISD::FSQRT: 4239 case ISD::FSIN: 4240 case ISD::FCOS: 4241 Tmp1 = PromoteOp(Node->getOperand(0)); 4242 assert(Tmp1.getValueType() == NVT); 4243 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4244 if (NoExcessFPPrecision) 4245 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4246 DAG.getValueType(VT)); 4247 break; 4248 4249 case ISD::FPOWI: { 4250 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4251 // directly as well, which may be better. 4252 Tmp1 = PromoteOp(Node->getOperand(0)); 4253 assert(Tmp1.getValueType() == NVT); 4254 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4255 if (NoExcessFPPrecision) 4256 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4257 DAG.getValueType(VT)); 4258 break; 4259 } 4260 4261 case ISD::ATOMIC_LCS: { 4262 Tmp2 = PromoteOp(Node->getOperand(2)); 4263 Tmp3 = PromoteOp(Node->getOperand(3)); 4264 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4265 Node->getOperand(1), Tmp2, Tmp3, 4266 cast<AtomicSDNode>(Node)->getVT()); 4267 // Remember that we legalized the chain. 4268 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4269 break; 4270 } 4271 case ISD::ATOMIC_LAS: 4272 case ISD::ATOMIC_LSS: 4273 case ISD::ATOMIC_LOAD_AND: 4274 case ISD::ATOMIC_LOAD_OR: 4275 case ISD::ATOMIC_LOAD_XOR: 4276 case ISD::ATOMIC_LOAD_MIN: 4277 case ISD::ATOMIC_LOAD_MAX: 4278 case ISD::ATOMIC_LOAD_UMIN: 4279 case ISD::ATOMIC_LOAD_UMAX: 4280 case ISD::ATOMIC_SWAP: { 4281 Tmp2 = PromoteOp(Node->getOperand(2)); 4282 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4283 Node->getOperand(1), Tmp2, 4284 cast<AtomicSDNode>(Node)->getVT()); 4285 // Remember that we legalized the chain. 4286 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4287 break; 4288 } 4289 4290 case ISD::AND: 4291 case ISD::OR: 4292 case ISD::XOR: 4293 case ISD::ADD: 4294 case ISD::SUB: 4295 case ISD::MUL: 4296 // The input may have strange things in the top bits of the registers, but 4297 // these operations don't care. They may have weird bits going out, but 4298 // that too is okay if they are integer operations. 4299 Tmp1 = PromoteOp(Node->getOperand(0)); 4300 Tmp2 = PromoteOp(Node->getOperand(1)); 4301 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4302 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4303 break; 4304 case ISD::FADD: 4305 case ISD::FSUB: 4306 case ISD::FMUL: 4307 Tmp1 = PromoteOp(Node->getOperand(0)); 4308 Tmp2 = PromoteOp(Node->getOperand(1)); 4309 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4310 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4311 4312 // Floating point operations will give excess precision that we may not be 4313 // able to tolerate. If we DO allow excess precision, just leave it, 4314 // otherwise excise it. 4315 // FIXME: Why would we need to round FP ops more than integer ones? 4316 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4317 if (NoExcessFPPrecision) 4318 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4319 DAG.getValueType(VT)); 4320 break; 4321 4322 case ISD::SDIV: 4323 case ISD::SREM: 4324 // These operators require that their input be sign extended. 4325 Tmp1 = PromoteOp(Node->getOperand(0)); 4326 Tmp2 = PromoteOp(Node->getOperand(1)); 4327 if (MVT::isInteger(NVT)) { 4328 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4329 DAG.getValueType(VT)); 4330 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4331 DAG.getValueType(VT)); 4332 } 4333 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4334 4335 // Perform FP_ROUND: this is probably overly pessimistic. 4336 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 4337 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4338 DAG.getValueType(VT)); 4339 break; 4340 case ISD::FDIV: 4341 case ISD::FREM: 4342 case ISD::FCOPYSIGN: 4343 // These operators require that their input be fp extended. 4344 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4345 case Expand: assert(0 && "not implemented"); 4346 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4347 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4348 } 4349 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4350 case Expand: assert(0 && "not implemented"); 4351 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4352 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4353 } 4354 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4355 4356 // Perform FP_ROUND: this is probably overly pessimistic. 4357 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4358 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4359 DAG.getValueType(VT)); 4360 break; 4361 4362 case ISD::UDIV: 4363 case ISD::UREM: 4364 // These operators require that their input be zero extended. 4365 Tmp1 = PromoteOp(Node->getOperand(0)); 4366 Tmp2 = PromoteOp(Node->getOperand(1)); 4367 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 4368 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4369 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4370 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4371 break; 4372 4373 case ISD::SHL: 4374 Tmp1 = PromoteOp(Node->getOperand(0)); 4375 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4376 break; 4377 case ISD::SRA: 4378 // The input value must be properly sign extended. 4379 Tmp1 = PromoteOp(Node->getOperand(0)); 4380 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4381 DAG.getValueType(VT)); 4382 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4383 break; 4384 case ISD::SRL: 4385 // The input value must be properly zero extended. 4386 Tmp1 = PromoteOp(Node->getOperand(0)); 4387 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4388 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4389 break; 4390 4391 case ISD::VAARG: 4392 Tmp1 = Node->getOperand(0); // Get the chain. 4393 Tmp2 = Node->getOperand(1); // Get the pointer. 4394 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4395 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4396 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4397 } else { 4398 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4399 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4400 // Increment the pointer, VAList, to the next vaarg 4401 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4402 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4403 TLI.getPointerTy())); 4404 // Store the incremented VAList to the legalized pointer 4405 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4406 // Load the actual argument out of the pointer VAList 4407 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4408 } 4409 // Remember that we legalized the chain. 4410 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4411 break; 4412 4413 case ISD::LOAD: { 4414 LoadSDNode *LD = cast<LoadSDNode>(Node); 4415 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4416 ? ISD::EXTLOAD : LD->getExtensionType(); 4417 Result = DAG.getExtLoad(ExtType, NVT, 4418 LD->getChain(), LD->getBasePtr(), 4419 LD->getSrcValue(), LD->getSrcValueOffset(), 4420 LD->getMemoryVT(), 4421 LD->isVolatile(), 4422 LD->getAlignment()); 4423 // Remember that we legalized the chain. 4424 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4425 break; 4426 } 4427 case ISD::SELECT: 4428 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4429 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4430 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4431 break; 4432 case ISD::SELECT_CC: 4433 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4434 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4435 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4436 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4437 break; 4438 case ISD::BSWAP: 4439 Tmp1 = Node->getOperand(0); 4440 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4441 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4442 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4443 DAG.getConstant(MVT::getSizeInBits(NVT) - 4444 MVT::getSizeInBits(VT), 4445 TLI.getShiftAmountTy())); 4446 break; 4447 case ISD::CTPOP: 4448 case ISD::CTTZ: 4449 case ISD::CTLZ: 4450 // Zero extend the argument 4451 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4452 // Perform the larger operation, then subtract if needed. 4453 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4454 switch(Node->getOpcode()) { 4455 case ISD::CTPOP: 4456 Result = Tmp1; 4457 break; 4458 case ISD::CTTZ: 4459 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4460 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4461 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4462 ISD::SETEQ); 4463 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4464 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4465 break; 4466 case ISD::CTLZ: 4467 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4468 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4469 DAG.getConstant(MVT::getSizeInBits(NVT) - 4470 MVT::getSizeInBits(VT), NVT)); 4471 break; 4472 } 4473 break; 4474 case ISD::EXTRACT_SUBVECTOR: 4475 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4476 break; 4477 case ISD::EXTRACT_VECTOR_ELT: 4478 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4479 break; 4480 } 4481 4482 assert(Result.Val && "Didn't set a result!"); 4483 4484 // Make sure the result is itself legal. 4485 Result = LegalizeOp(Result); 4486 4487 // Remember that we promoted this! 4488 AddPromotedOperand(Op, Result); 4489 return Result; 4490} 4491 4492/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4493/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4494/// based on the vector type. The return type of this matches the element type 4495/// of the vector, which may not be legal for the target. 4496SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4497 // We know that operand #0 is the Vec vector. If the index is a constant 4498 // or if the invec is a supported hardware type, we can use it. Otherwise, 4499 // lower to a store then an indexed load. 4500 SDOperand Vec = Op.getOperand(0); 4501 SDOperand Idx = Op.getOperand(1); 4502 4503 MVT::ValueType TVT = Vec.getValueType(); 4504 unsigned NumElems = MVT::getVectorNumElements(TVT); 4505 4506 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4507 default: assert(0 && "This action is not supported yet!"); 4508 case TargetLowering::Custom: { 4509 Vec = LegalizeOp(Vec); 4510 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4511 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4512 if (Tmp3.Val) 4513 return Tmp3; 4514 break; 4515 } 4516 case TargetLowering::Legal: 4517 if (isTypeLegal(TVT)) { 4518 Vec = LegalizeOp(Vec); 4519 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4520 return Op; 4521 } 4522 break; 4523 case TargetLowering::Expand: 4524 break; 4525 } 4526 4527 if (NumElems == 1) { 4528 // This must be an access of the only element. Return it. 4529 Op = ScalarizeVectorOp(Vec); 4530 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4531 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4532 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4533 SDOperand Lo, Hi; 4534 SplitVectorOp(Vec, Lo, Hi); 4535 if (CIdx->getValue() < NumLoElts) { 4536 Vec = Lo; 4537 } else { 4538 Vec = Hi; 4539 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4540 Idx.getValueType()); 4541 } 4542 4543 // It's now an extract from the appropriate high or low part. Recurse. 4544 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4545 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4546 } else { 4547 // Store the value to a temporary stack slot, then LOAD the scalar 4548 // element back out. 4549 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4550 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4551 4552 // Add the offset to the index. 4553 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4554 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4555 DAG.getConstant(EltSize, Idx.getValueType())); 4556 4557 if (MVT::getSizeInBits(Idx.getValueType()) > 4558 MVT::getSizeInBits(TLI.getPointerTy())) 4559 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4560 else 4561 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4562 4563 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4564 4565 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4566 } 4567 return Op; 4568} 4569 4570/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4571/// we assume the operation can be split if it is not already legal. 4572SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4573 // We know that operand #0 is the Vec vector. For now we assume the index 4574 // is a constant and that the extracted result is a supported hardware type. 4575 SDOperand Vec = Op.getOperand(0); 4576 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4577 4578 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4579 4580 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4581 // This must be an access of the desired vector length. Return it. 4582 return Vec; 4583 } 4584 4585 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4586 SDOperand Lo, Hi; 4587 SplitVectorOp(Vec, Lo, Hi); 4588 if (CIdx->getValue() < NumElems/2) { 4589 Vec = Lo; 4590 } else { 4591 Vec = Hi; 4592 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4593 } 4594 4595 // It's now an extract from the appropriate high or low part. Recurse. 4596 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4597 return ExpandEXTRACT_SUBVECTOR(Op); 4598} 4599 4600/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4601/// with condition CC on the current target. This usually involves legalizing 4602/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4603/// there may be no choice but to create a new SetCC node to represent the 4604/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4605/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4606void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4607 SDOperand &RHS, 4608 SDOperand &CC) { 4609 SDOperand Tmp1, Tmp2, Tmp3, Result; 4610 4611 switch (getTypeAction(LHS.getValueType())) { 4612 case Legal: 4613 Tmp1 = LegalizeOp(LHS); // LHS 4614 Tmp2 = LegalizeOp(RHS); // RHS 4615 break; 4616 case Promote: 4617 Tmp1 = PromoteOp(LHS); // LHS 4618 Tmp2 = PromoteOp(RHS); // RHS 4619 4620 // If this is an FP compare, the operands have already been extended. 4621 if (MVT::isInteger(LHS.getValueType())) { 4622 MVT::ValueType VT = LHS.getValueType(); 4623 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4624 4625 // Otherwise, we have to insert explicit sign or zero extends. Note 4626 // that we could insert sign extends for ALL conditions, but zero extend 4627 // is cheaper on many machines (an AND instead of two shifts), so prefer 4628 // it. 4629 switch (cast<CondCodeSDNode>(CC)->get()) { 4630 default: assert(0 && "Unknown integer comparison!"); 4631 case ISD::SETEQ: 4632 case ISD::SETNE: 4633 case ISD::SETUGE: 4634 case ISD::SETUGT: 4635 case ISD::SETULE: 4636 case ISD::SETULT: 4637 // ALL of these operations will work if we either sign or zero extend 4638 // the operands (including the unsigned comparisons!). Zero extend is 4639 // usually a simpler/cheaper operation, so prefer it. 4640 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4641 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4642 break; 4643 case ISD::SETGE: 4644 case ISD::SETGT: 4645 case ISD::SETLT: 4646 case ISD::SETLE: 4647 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4648 DAG.getValueType(VT)); 4649 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4650 DAG.getValueType(VT)); 4651 break; 4652 } 4653 } 4654 break; 4655 case Expand: { 4656 MVT::ValueType VT = LHS.getValueType(); 4657 if (VT == MVT::f32 || VT == MVT::f64) { 4658 // Expand into one or more soft-fp libcall(s). 4659 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4660 switch (cast<CondCodeSDNode>(CC)->get()) { 4661 case ISD::SETEQ: 4662 case ISD::SETOEQ: 4663 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4664 break; 4665 case ISD::SETNE: 4666 case ISD::SETUNE: 4667 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4668 break; 4669 case ISD::SETGE: 4670 case ISD::SETOGE: 4671 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4672 break; 4673 case ISD::SETLT: 4674 case ISD::SETOLT: 4675 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4676 break; 4677 case ISD::SETLE: 4678 case ISD::SETOLE: 4679 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4680 break; 4681 case ISD::SETGT: 4682 case ISD::SETOGT: 4683 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4684 break; 4685 case ISD::SETUO: 4686 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4687 break; 4688 case ISD::SETO: 4689 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4690 break; 4691 default: 4692 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4693 switch (cast<CondCodeSDNode>(CC)->get()) { 4694 case ISD::SETONE: 4695 // SETONE = SETOLT | SETOGT 4696 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4697 // Fallthrough 4698 case ISD::SETUGT: 4699 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4700 break; 4701 case ISD::SETUGE: 4702 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4703 break; 4704 case ISD::SETULT: 4705 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4706 break; 4707 case ISD::SETULE: 4708 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4709 break; 4710 case ISD::SETUEQ: 4711 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4712 break; 4713 default: assert(0 && "Unsupported FP setcc!"); 4714 } 4715 } 4716 4717 SDOperand Dummy; 4718 Tmp1 = ExpandLibCall(LC1, 4719 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4720 false /*sign irrelevant*/, Dummy); 4721 Tmp2 = DAG.getConstant(0, MVT::i32); 4722 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4723 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4724 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4725 CC); 4726 LHS = ExpandLibCall(LC2, 4727 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4728 false /*sign irrelevant*/, Dummy); 4729 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4730 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4731 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4732 Tmp2 = SDOperand(); 4733 } 4734 LHS = Tmp1; 4735 RHS = Tmp2; 4736 return; 4737 } 4738 4739 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4740 ExpandOp(LHS, LHSLo, LHSHi); 4741 ExpandOp(RHS, RHSLo, RHSHi); 4742 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4743 4744 if (VT==MVT::ppcf128) { 4745 // FIXME: This generated code sucks. We want to generate 4746 // FCMP crN, hi1, hi2 4747 // BNE crN, L: 4748 // FCMP crN, lo1, lo2 4749 // The following can be improved, but not that much. 4750 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4751 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4752 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4753 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4754 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4755 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4756 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4757 Tmp2 = SDOperand(); 4758 break; 4759 } 4760 4761 switch (CCCode) { 4762 case ISD::SETEQ: 4763 case ISD::SETNE: 4764 if (RHSLo == RHSHi) 4765 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4766 if (RHSCST->isAllOnesValue()) { 4767 // Comparison to -1. 4768 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4769 Tmp2 = RHSLo; 4770 break; 4771 } 4772 4773 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4774 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4775 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4776 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4777 break; 4778 default: 4779 // If this is a comparison of the sign bit, just look at the top part. 4780 // X > -1, x < 0 4781 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4782 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4783 CST->isNullValue()) || // X < 0 4784 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4785 CST->isAllOnesValue())) { // X > -1 4786 Tmp1 = LHSHi; 4787 Tmp2 = RHSHi; 4788 break; 4789 } 4790 4791 // FIXME: This generated code sucks. 4792 ISD::CondCode LowCC; 4793 switch (CCCode) { 4794 default: assert(0 && "Unknown integer setcc!"); 4795 case ISD::SETLT: 4796 case ISD::SETULT: LowCC = ISD::SETULT; break; 4797 case ISD::SETGT: 4798 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4799 case ISD::SETLE: 4800 case ISD::SETULE: LowCC = ISD::SETULE; break; 4801 case ISD::SETGE: 4802 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4803 } 4804 4805 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4806 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4807 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4808 4809 // NOTE: on targets without efficient SELECT of bools, we can always use 4810 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4811 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4812 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4813 LowCC, false, DagCombineInfo); 4814 if (!Tmp1.Val) 4815 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4816 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4817 CCCode, false, DagCombineInfo); 4818 if (!Tmp2.Val) 4819 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4820 RHSHi,CC); 4821 4822 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4823 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4824 if ((Tmp1C && Tmp1C->isNullValue()) || 4825 (Tmp2C && Tmp2C->isNullValue() && 4826 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4827 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4828 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4829 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4830 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4831 // low part is known false, returns high part. 4832 // For LE / GE, if high part is known false, ignore the low part. 4833 // For LT / GT, if high part is known true, ignore the low part. 4834 Tmp1 = Tmp2; 4835 Tmp2 = SDOperand(); 4836 } else { 4837 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4838 ISD::SETEQ, false, DagCombineInfo); 4839 if (!Result.Val) 4840 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4841 ISD::SETEQ); 4842 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4843 Result, Tmp1, Tmp2)); 4844 Tmp1 = Result; 4845 Tmp2 = SDOperand(); 4846 } 4847 } 4848 } 4849 } 4850 LHS = Tmp1; 4851 RHS = Tmp2; 4852} 4853 4854/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4855/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4856/// a load from the stack slot to DestVT, extending it if needed. 4857/// The resultant code need not be legal. 4858SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4859 MVT::ValueType SlotVT, 4860 MVT::ValueType DestVT) { 4861 // Create the stack frame object. 4862 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4863 4864 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4865 int SPFI = StackPtrFI->getIndex(); 4866 4867 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); 4868 unsigned SlotSize = MVT::getSizeInBits(SlotVT); 4869 unsigned DestSize = MVT::getSizeInBits(DestVT); 4870 4871 // Emit a store to the stack slot. Use a truncstore if the input value is 4872 // later than DestVT. 4873 SDOperand Store; 4874 if (SrcSize > SlotSize) 4875 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4876 PseudoSourceValue::getFixedStack(), 4877 SPFI, SlotVT); 4878 else { 4879 assert(SrcSize == SlotSize && "Invalid store"); 4880 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4881 PseudoSourceValue::getFixedStack(), 4882 SPFI, SlotVT); 4883 } 4884 4885 // Result is a load from the stack slot. 4886 if (SlotSize == DestSize) 4887 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4888 4889 assert(SlotSize < DestSize && "Unknown extension!"); 4890 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4891} 4892 4893SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4894 // Create a vector sized/aligned stack slot, store the value to element #0, 4895 // then load the whole vector back out. 4896 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4897 4898 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4899 int SPFI = StackPtrFI->getIndex(); 4900 4901 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4902 PseudoSourceValue::getFixedStack(), SPFI); 4903 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4904 PseudoSourceValue::getFixedStack(), SPFI); 4905} 4906 4907 4908/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4909/// support the operation, but do support the resultant vector type. 4910SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4911 4912 // If the only non-undef value is the low element, turn this into a 4913 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4914 unsigned NumElems = Node->getNumOperands(); 4915 bool isOnlyLowElement = true; 4916 SDOperand SplatValue = Node->getOperand(0); 4917 4918 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t> 4919 // and use a bitmask instead of a list of elements. 4920 std::map<SDOperand, std::vector<unsigned> > Values; 4921 Values[SplatValue].push_back(0); 4922 bool isConstant = true; 4923 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4924 SplatValue.getOpcode() != ISD::UNDEF) 4925 isConstant = false; 4926 4927 for (unsigned i = 1; i < NumElems; ++i) { 4928 SDOperand V = Node->getOperand(i); 4929 Values[V].push_back(i); 4930 if (V.getOpcode() != ISD::UNDEF) 4931 isOnlyLowElement = false; 4932 if (SplatValue != V) 4933 SplatValue = SDOperand(0,0); 4934 4935 // If this isn't a constant element or an undef, we can't use a constant 4936 // pool load. 4937 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4938 V.getOpcode() != ISD::UNDEF) 4939 isConstant = false; 4940 } 4941 4942 if (isOnlyLowElement) { 4943 // If the low element is an undef too, then this whole things is an undef. 4944 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4945 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4946 // Otherwise, turn this into a scalar_to_vector node. 4947 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4948 Node->getOperand(0)); 4949 } 4950 4951 // If all elements are constants, create a load from the constant pool. 4952 if (isConstant) { 4953 MVT::ValueType VT = Node->getValueType(0); 4954 std::vector<Constant*> CV; 4955 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4956 if (ConstantFPSDNode *V = 4957 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4958 CV.push_back(ConstantFP::get(V->getValueAPF())); 4959 } else if (ConstantSDNode *V = 4960 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4961 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4962 } else { 4963 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4964 const Type *OpNTy = 4965 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4966 CV.push_back(UndefValue::get(OpNTy)); 4967 } 4968 } 4969 Constant *CP = ConstantVector::get(CV); 4970 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4971 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4972 PseudoSourceValue::getConstantPool(), 0); 4973 } 4974 4975 if (SplatValue.Val) { // Splat of one value? 4976 // Build the shuffle constant vector: <0, 0, 0, 0> 4977 MVT::ValueType MaskVT = 4978 MVT::getIntVectorWithNumElements(NumElems); 4979 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4980 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4981 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4982 &ZeroVec[0], ZeroVec.size()); 4983 4984 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4985 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4986 // Get the splatted value into the low element of a vector register. 4987 SDOperand LowValVec = 4988 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4989 4990 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4991 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4992 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4993 SplatMask); 4994 } 4995 } 4996 4997 // If there are only two unique elements, we may be able to turn this into a 4998 // vector shuffle. 4999 if (Values.size() == 2) { 5000 // Get the two values in deterministic order. 5001 SDOperand Val1 = Node->getOperand(1); 5002 SDOperand Val2; 5003 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin(); 5004 if (MI->first != Val1) 5005 Val2 = MI->first; 5006 else 5007 Val2 = (++MI)->first; 5008 5009 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5010 // vector shuffle has the undef vector on the RHS. 5011 if (Val1.getOpcode() == ISD::UNDEF) 5012 std::swap(Val1, Val2); 5013 5014 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5015 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5016 MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT); 5017 std::vector<SDOperand> MaskVec(NumElems); 5018 5019 // Set elements of the shuffle mask for Val1. 5020 std::vector<unsigned> &Val1Elts = Values[Val1]; 5021 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5022 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5023 5024 // Set elements of the shuffle mask for Val2. 5025 std::vector<unsigned> &Val2Elts = Values[Val2]; 5026 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5027 if (Val2.getOpcode() != ISD::UNDEF) 5028 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5029 else 5030 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5031 5032 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5033 &MaskVec[0], MaskVec.size()); 5034 5035 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5036 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5037 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5038 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5039 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5040 SDOperand Ops[] = { Val1, Val2, ShuffleMask }; 5041 5042 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5043 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5044 } 5045 } 5046 5047 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5048 // aligned object on the stack, store each element into it, then load 5049 // the result as a vector. 5050 MVT::ValueType VT = Node->getValueType(0); 5051 // Create the stack frame object. 5052 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 5053 5054 // Emit a store of each element to the stack slot. 5055 SmallVector<SDOperand, 8> Stores; 5056 unsigned TypeByteSize = 5057 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 5058 // Store (in the right endianness) the elements to memory. 5059 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5060 // Ignore undef elements. 5061 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5062 5063 unsigned Offset = TypeByteSize*i; 5064 5065 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5066 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5067 5068 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5069 NULL, 0)); 5070 } 5071 5072 SDOperand StoreChain; 5073 if (!Stores.empty()) // Not all undef elements? 5074 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5075 &Stores[0], Stores.size()); 5076 else 5077 StoreChain = DAG.getEntryNode(); 5078 5079 // Result is a load from the stack slot. 5080 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5081} 5082 5083void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5084 SDOperand Op, SDOperand Amt, 5085 SDOperand &Lo, SDOperand &Hi) { 5086 // Expand the subcomponents. 5087 SDOperand LHSL, LHSH; 5088 ExpandOp(Op, LHSL, LHSH); 5089 5090 SDOperand Ops[] = { LHSL, LHSH, Amt }; 5091 MVT::ValueType VT = LHSL.getValueType(); 5092 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5093 Hi = Lo.getValue(1); 5094} 5095 5096 5097/// ExpandShift - Try to find a clever way to expand this shift operation out to 5098/// smaller elements. If we can't find a way that is more efficient than a 5099/// libcall on this target, return false. Otherwise, return true with the 5100/// low-parts expanded into Lo and Hi. 5101bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 5102 SDOperand &Lo, SDOperand &Hi) { 5103 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5104 "This is not a shift!"); 5105 5106 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5107 SDOperand ShAmt = LegalizeOp(Amt); 5108 MVT::ValueType ShTy = ShAmt.getValueType(); 5109 unsigned ShBits = MVT::getSizeInBits(ShTy); 5110 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 5111 unsigned NVTBits = MVT::getSizeInBits(NVT); 5112 5113 // Handle the case when Amt is an immediate. 5114 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5115 unsigned Cst = CN->getValue(); 5116 // Expand the incoming operand to be shifted, so that we have its parts 5117 SDOperand InL, InH; 5118 ExpandOp(Op, InL, InH); 5119 switch(Opc) { 5120 case ISD::SHL: 5121 if (Cst > VTBits) { 5122 Lo = DAG.getConstant(0, NVT); 5123 Hi = DAG.getConstant(0, NVT); 5124 } else if (Cst > NVTBits) { 5125 Lo = DAG.getConstant(0, NVT); 5126 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5127 } else if (Cst == NVTBits) { 5128 Lo = DAG.getConstant(0, NVT); 5129 Hi = InL; 5130 } else { 5131 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5132 Hi = DAG.getNode(ISD::OR, NVT, 5133 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5134 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5135 } 5136 return true; 5137 case ISD::SRL: 5138 if (Cst > VTBits) { 5139 Lo = DAG.getConstant(0, NVT); 5140 Hi = DAG.getConstant(0, NVT); 5141 } else if (Cst > NVTBits) { 5142 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5143 Hi = DAG.getConstant(0, NVT); 5144 } else if (Cst == NVTBits) { 5145 Lo = InH; 5146 Hi = DAG.getConstant(0, NVT); 5147 } else { 5148 Lo = DAG.getNode(ISD::OR, NVT, 5149 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5150 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5151 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5152 } 5153 return true; 5154 case ISD::SRA: 5155 if (Cst > VTBits) { 5156 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5157 DAG.getConstant(NVTBits-1, ShTy)); 5158 } else if (Cst > NVTBits) { 5159 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5160 DAG.getConstant(Cst-NVTBits, ShTy)); 5161 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5162 DAG.getConstant(NVTBits-1, ShTy)); 5163 } else if (Cst == NVTBits) { 5164 Lo = InH; 5165 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5166 DAG.getConstant(NVTBits-1, ShTy)); 5167 } else { 5168 Lo = DAG.getNode(ISD::OR, NVT, 5169 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5170 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5171 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5172 } 5173 return true; 5174 } 5175 } 5176 5177 // Okay, the shift amount isn't constant. However, if we can tell that it is 5178 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5179 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5180 APInt KnownZero, KnownOne; 5181 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5182 5183 // If we know that if any of the high bits of the shift amount are one, then 5184 // we can do this as a couple of simple shifts. 5185 if (KnownOne.intersects(Mask)) { 5186 // Mask out the high bit, which we know is set. 5187 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5188 DAG.getConstant(~Mask, Amt.getValueType())); 5189 5190 // Expand the incoming operand to be shifted, so that we have its parts 5191 SDOperand InL, InH; 5192 ExpandOp(Op, InL, InH); 5193 switch(Opc) { 5194 case ISD::SHL: 5195 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5196 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5197 return true; 5198 case ISD::SRL: 5199 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5200 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5201 return true; 5202 case ISD::SRA: 5203 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5204 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5205 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5206 return true; 5207 } 5208 } 5209 5210 // If we know that the high bits of the shift amount are all zero, then we can 5211 // do this as a couple of simple shifts. 5212 if ((KnownZero & Mask) == Mask) { 5213 // Compute 32-amt. 5214 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5215 DAG.getConstant(NVTBits, Amt.getValueType()), 5216 Amt); 5217 5218 // Expand the incoming operand to be shifted, so that we have its parts 5219 SDOperand InL, InH; 5220 ExpandOp(Op, InL, InH); 5221 switch(Opc) { 5222 case ISD::SHL: 5223 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5224 Hi = DAG.getNode(ISD::OR, NVT, 5225 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5226 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5227 return true; 5228 case ISD::SRL: 5229 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5230 Lo = DAG.getNode(ISD::OR, NVT, 5231 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5232 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5233 return true; 5234 case ISD::SRA: 5235 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5236 Lo = DAG.getNode(ISD::OR, NVT, 5237 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5238 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5239 return true; 5240 } 5241 } 5242 5243 return false; 5244} 5245 5246 5247// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5248// does not fit into a register, return the lo part and set the hi part to the 5249// by-reg argument. If it does fit into a single register, return the result 5250// and leave the Hi part unset. 5251SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5252 bool isSigned, SDOperand &Hi) { 5253 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5254 // The input chain to this libcall is the entry node of the function. 5255 // Legalizing the call will automatically add the previous call to the 5256 // dependence. 5257 SDOperand InChain = DAG.getEntryNode(); 5258 5259 TargetLowering::ArgListTy Args; 5260 TargetLowering::ArgListEntry Entry; 5261 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5262 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 5263 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 5264 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5265 Entry.isSExt = isSigned; 5266 Entry.isZExt = !isSigned; 5267 Args.push_back(Entry); 5268 } 5269 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5270 TLI.getPointerTy()); 5271 5272 // Splice the libcall in wherever FindInputOutputChains tells us to. 5273 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 5274 std::pair<SDOperand,SDOperand> CallInfo = 5275 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5276 false, Callee, Args, DAG); 5277 5278 // Legalize the call sequence, starting with the chain. This will advance 5279 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5280 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5281 LegalizeOp(CallInfo.second); 5282 SDOperand Result; 5283 switch (getTypeAction(CallInfo.first.getValueType())) { 5284 default: assert(0 && "Unknown thing"); 5285 case Legal: 5286 Result = CallInfo.first; 5287 break; 5288 case Expand: 5289 ExpandOp(CallInfo.first, Result, Hi); 5290 break; 5291 } 5292 return Result; 5293} 5294 5295 5296/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5297/// 5298SDOperand SelectionDAGLegalize:: 5299ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 5300 MVT::ValueType SourceVT = Source.getValueType(); 5301 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5302 5303 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5304 if (!isSigned && SourceVT != MVT::i32) { 5305 // The integer value loaded will be incorrectly if the 'sign bit' of the 5306 // incoming integer is set. To handle this, we dynamically test to see if 5307 // it is set, and, if so, add a fudge factor. 5308 SDOperand Hi; 5309 if (ExpandSource) { 5310 SDOperand Lo; 5311 ExpandOp(Source, Lo, Hi); 5312 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5313 } else { 5314 // The comparison for the sign bit will use the entire operand. 5315 Hi = Source; 5316 } 5317 5318 // If this is unsigned, and not supported, first perform the conversion to 5319 // signed, then adjust the result if the sign bit is set. 5320 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); 5321 5322 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5323 DAG.getConstant(0, Hi.getValueType()), 5324 ISD::SETLT); 5325 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5326 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5327 SignSet, Four, Zero); 5328 uint64_t FF = 0x5f800000ULL; 5329 if (TLI.isLittleEndian()) FF <<= 32; 5330 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5331 5332 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5333 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5334 SDOperand FudgeInReg; 5335 if (DestTy == MVT::f32) 5336 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5337 PseudoSourceValue::getConstantPool(), 0); 5338 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 5339 // FIXME: Avoid the extend by construction the right constantpool? 5340 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5341 CPIdx, 5342 PseudoSourceValue::getConstantPool(), 0, 5343 MVT::f32); 5344 else 5345 assert(0 && "Unexpected conversion"); 5346 5347 MVT::ValueType SCVT = SignedConv.getValueType(); 5348 if (SCVT != DestTy) { 5349 // Destination type needs to be expanded as well. The FADD now we are 5350 // constructing will be expanded into a libcall. 5351 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 5352 assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy)); 5353 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5354 SignedConv, SignedConv.getValue(1)); 5355 } 5356 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5357 } 5358 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5359 } 5360 5361 // Check to see if the target has a custom way to lower this. If so, use it. 5362 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5363 default: assert(0 && "This action not implemented for this operation!"); 5364 case TargetLowering::Legal: 5365 case TargetLowering::Expand: 5366 break; // This case is handled below. 5367 case TargetLowering::Custom: { 5368 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5369 Source), DAG); 5370 if (NV.Val) 5371 return LegalizeOp(NV); 5372 break; // The target decided this was legal after all 5373 } 5374 } 5375 5376 // Expand the source, then glue it back together for the call. We must expand 5377 // the source in case it is shared (this pass of legalize must traverse it). 5378 if (ExpandSource) { 5379 SDOperand SrcLo, SrcHi; 5380 ExpandOp(Source, SrcLo, SrcHi); 5381 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5382 } 5383 5384 RTLIB::Libcall LC; 5385 if (SourceVT == MVT::i32) { 5386 if (DestTy == MVT::f32) 5387 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5388 else { 5389 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5390 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5391 } 5392 } else if (SourceVT == MVT::i64) { 5393 if (DestTy == MVT::f32) 5394 LC = RTLIB::SINTTOFP_I64_F32; 5395 else if (DestTy == MVT::f64) 5396 LC = RTLIB::SINTTOFP_I64_F64; 5397 else if (DestTy == MVT::f80) 5398 LC = RTLIB::SINTTOFP_I64_F80; 5399 else { 5400 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5401 LC = RTLIB::SINTTOFP_I64_PPCF128; 5402 } 5403 } else if (SourceVT == MVT::i128) { 5404 if (DestTy == MVT::f32) 5405 LC = RTLIB::SINTTOFP_I128_F32; 5406 else if (DestTy == MVT::f64) 5407 LC = RTLIB::SINTTOFP_I128_F64; 5408 else if (DestTy == MVT::f80) 5409 LC = RTLIB::SINTTOFP_I128_F80; 5410 else { 5411 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5412 LC = RTLIB::SINTTOFP_I128_PPCF128; 5413 } 5414 } else { 5415 assert(0 && "Unknown int value type"); 5416 } 5417 5418 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5419 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5420 SDOperand HiPart; 5421 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart); 5422 if (Result.getValueType() != DestTy && HiPart.Val) 5423 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5424 return Result; 5425} 5426 5427/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5428/// INT_TO_FP operation of the specified operand when the target requests that 5429/// we expand it. At this point, we know that the result and operand types are 5430/// legal for the target. 5431SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5432 SDOperand Op0, 5433 MVT::ValueType DestVT) { 5434 if (Op0.getValueType() == MVT::i32) { 5435 // simple 32-bit [signed|unsigned] integer to float/double expansion 5436 5437 // Get the stack frame index of a 8 byte buffer. 5438 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5439 5440 // word offset constant for Hi/Lo address computation 5441 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5442 // set up Hi and Lo (into buffer) address based on endian 5443 SDOperand Hi = StackSlot; 5444 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5445 if (TLI.isLittleEndian()) 5446 std::swap(Hi, Lo); 5447 5448 // if signed map to unsigned space 5449 SDOperand Op0Mapped; 5450 if (isSigned) { 5451 // constant used to invert sign bit (signed to unsigned mapping) 5452 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5453 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5454 } else { 5455 Op0Mapped = Op0; 5456 } 5457 // store the lo of the constructed double - based on integer input 5458 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5459 Op0Mapped, Lo, NULL, 0); 5460 // initial hi portion of constructed double 5461 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5462 // store the hi of the constructed double - biased exponent 5463 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5464 // load the constructed double 5465 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5466 // FP constant to bias correct the final result 5467 SDOperand Bias = DAG.getConstantFP(isSigned ? 5468 BitsToDouble(0x4330000080000000ULL) 5469 : BitsToDouble(0x4330000000000000ULL), 5470 MVT::f64); 5471 // subtract the bias 5472 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5473 // final result 5474 SDOperand Result; 5475 // handle final rounding 5476 if (DestVT == MVT::f64) { 5477 // do nothing 5478 Result = Sub; 5479 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5480 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5481 DAG.getIntPtrConstant(0)); 5482 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5483 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5484 } 5485 return Result; 5486 } 5487 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5488 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5489 5490 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5491 DAG.getConstant(0, Op0.getValueType()), 5492 ISD::SETLT); 5493 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5494 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5495 SignSet, Four, Zero); 5496 5497 // If the sign bit of the integer is set, the large number will be treated 5498 // as a negative number. To counteract this, the dynamic code adds an 5499 // offset depending on the data type. 5500 uint64_t FF; 5501 switch (Op0.getValueType()) { 5502 default: assert(0 && "Unsupported integer type!"); 5503 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5504 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5505 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5506 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5507 } 5508 if (TLI.isLittleEndian()) FF <<= 32; 5509 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5510 5511 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5512 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5513 SDOperand FudgeInReg; 5514 if (DestVT == MVT::f32) 5515 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5516 PseudoSourceValue::getConstantPool(), 0); 5517 else { 5518 FudgeInReg = 5519 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5520 DAG.getEntryNode(), CPIdx, 5521 PseudoSourceValue::getConstantPool(), 0, 5522 MVT::f32)); 5523 } 5524 5525 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5526} 5527 5528/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5529/// *INT_TO_FP operation of the specified operand when the target requests that 5530/// we promote it. At this point, we know that the result and operand types are 5531/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5532/// operation that takes a larger input. 5533SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5534 MVT::ValueType DestVT, 5535 bool isSigned) { 5536 // First step, figure out the appropriate *INT_TO_FP operation to use. 5537 MVT::ValueType NewInTy = LegalOp.getValueType(); 5538 5539 unsigned OpToUse = 0; 5540 5541 // Scan for the appropriate larger type to use. 5542 while (1) { 5543 NewInTy = (MVT::ValueType)(NewInTy+1); 5544 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5545 5546 // If the target supports SINT_TO_FP of this type, use it. 5547 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5548 default: break; 5549 case TargetLowering::Legal: 5550 if (!TLI.isTypeLegal(NewInTy)) 5551 break; // Can't use this datatype. 5552 // FALL THROUGH. 5553 case TargetLowering::Custom: 5554 OpToUse = ISD::SINT_TO_FP; 5555 break; 5556 } 5557 if (OpToUse) break; 5558 if (isSigned) continue; 5559 5560 // If the target supports UINT_TO_FP of this type, use it. 5561 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5562 default: break; 5563 case TargetLowering::Legal: 5564 if (!TLI.isTypeLegal(NewInTy)) 5565 break; // Can't use this datatype. 5566 // FALL THROUGH. 5567 case TargetLowering::Custom: 5568 OpToUse = ISD::UINT_TO_FP; 5569 break; 5570 } 5571 if (OpToUse) break; 5572 5573 // Otherwise, try a larger type. 5574 } 5575 5576 // Okay, we found the operation and type to use. Zero extend our input to the 5577 // desired type then run the operation on it. 5578 return DAG.getNode(OpToUse, DestVT, 5579 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5580 NewInTy, LegalOp)); 5581} 5582 5583/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5584/// FP_TO_*INT operation of the specified operand when the target requests that 5585/// we promote it. At this point, we know that the result and operand types are 5586/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5587/// operation that returns a larger result. 5588SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5589 MVT::ValueType DestVT, 5590 bool isSigned) { 5591 // First step, figure out the appropriate FP_TO*INT operation to use. 5592 MVT::ValueType NewOutTy = DestVT; 5593 5594 unsigned OpToUse = 0; 5595 5596 // Scan for the appropriate larger type to use. 5597 while (1) { 5598 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5599 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5600 5601 // If the target supports FP_TO_SINT returning this type, use it. 5602 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5603 default: break; 5604 case TargetLowering::Legal: 5605 if (!TLI.isTypeLegal(NewOutTy)) 5606 break; // Can't use this datatype. 5607 // FALL THROUGH. 5608 case TargetLowering::Custom: 5609 OpToUse = ISD::FP_TO_SINT; 5610 break; 5611 } 5612 if (OpToUse) break; 5613 5614 // If the target supports FP_TO_UINT of this type, use it. 5615 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5616 default: break; 5617 case TargetLowering::Legal: 5618 if (!TLI.isTypeLegal(NewOutTy)) 5619 break; // Can't use this datatype. 5620 // FALL THROUGH. 5621 case TargetLowering::Custom: 5622 OpToUse = ISD::FP_TO_UINT; 5623 break; 5624 } 5625 if (OpToUse) break; 5626 5627 // Otherwise, try a larger type. 5628 } 5629 5630 5631 // Okay, we found the operation and type to use. 5632 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5633 5634 // If the operation produces an invalid type, it must be custom lowered. Use 5635 // the target lowering hooks to expand it. Just keep the low part of the 5636 // expanded operation, we know that we're truncating anyway. 5637 if (getTypeAction(NewOutTy) == Expand) { 5638 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5639 assert(Operation.Val && "Didn't return anything"); 5640 } 5641 5642 // Truncate the result of the extended FP_TO_*INT operation to the desired 5643 // size. 5644 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5645} 5646 5647/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5648/// 5649SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5650 MVT::ValueType VT = Op.getValueType(); 5651 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5652 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5653 switch (VT) { 5654 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5655 case MVT::i16: 5656 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5657 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5658 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5659 case MVT::i32: 5660 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5661 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5662 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5663 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5664 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5665 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5666 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5667 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5668 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5669 case MVT::i64: 5670 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5671 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5672 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5673 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5674 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5675 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5676 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5677 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5678 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5679 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5680 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5681 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5682 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5683 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5684 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5685 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5686 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5687 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5688 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5689 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5690 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5691 } 5692} 5693 5694/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5695/// 5696SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5697 switch (Opc) { 5698 default: assert(0 && "Cannot expand this yet!"); 5699 case ISD::CTPOP: { 5700 static const uint64_t mask[6] = { 5701 0x5555555555555555ULL, 0x3333333333333333ULL, 5702 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5703 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5704 }; 5705 MVT::ValueType VT = Op.getValueType(); 5706 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5707 unsigned len = MVT::getSizeInBits(VT); 5708 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5709 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5710 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5711 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5712 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5713 DAG.getNode(ISD::AND, VT, 5714 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5715 } 5716 return Op; 5717 } 5718 case ISD::CTLZ: { 5719 // for now, we do this: 5720 // x = x | (x >> 1); 5721 // x = x | (x >> 2); 5722 // ... 5723 // x = x | (x >>16); 5724 // x = x | (x >>32); // for 64-bit input 5725 // return popcount(~x); 5726 // 5727 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5728 MVT::ValueType VT = Op.getValueType(); 5729 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5730 unsigned len = MVT::getSizeInBits(VT); 5731 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5732 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5733 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5734 } 5735 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5736 return DAG.getNode(ISD::CTPOP, VT, Op); 5737 } 5738 case ISD::CTTZ: { 5739 // for now, we use: { return popcount(~x & (x - 1)); } 5740 // unless the target has ctlz but not ctpop, in which case we use: 5741 // { return 32 - nlz(~x & (x-1)); } 5742 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5743 MVT::ValueType VT = Op.getValueType(); 5744 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5745 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5746 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5747 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5748 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5749 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5750 TLI.isOperationLegal(ISD::CTLZ, VT)) 5751 return DAG.getNode(ISD::SUB, VT, 5752 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5753 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5754 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5755 } 5756 } 5757} 5758 5759/// ExpandOp - Expand the specified SDOperand into its two component pieces 5760/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5761/// LegalizeNodes map is filled in for any results that are not expanded, the 5762/// ExpandedNodes map is filled in for any results that are expanded, and the 5763/// Lo/Hi values are returned. 5764void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5765 MVT::ValueType VT = Op.getValueType(); 5766 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5767 SDNode *Node = Op.Val; 5768 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5769 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5770 MVT::isVector(VT)) && 5771 "Cannot expand to FP value or to larger int value!"); 5772 5773 // See if we already expanded it. 5774 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5775 = ExpandedNodes.find(Op); 5776 if (I != ExpandedNodes.end()) { 5777 Lo = I->second.first; 5778 Hi = I->second.second; 5779 return; 5780 } 5781 5782 switch (Node->getOpcode()) { 5783 case ISD::CopyFromReg: 5784 assert(0 && "CopyFromReg must be legal!"); 5785 case ISD::FP_ROUND_INREG: 5786 if (VT == MVT::ppcf128 && 5787 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5788 TargetLowering::Custom) { 5789 SDOperand SrcLo, SrcHi, Src; 5790 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5791 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5792 SDOperand Result = TLI.LowerOperation( 5793 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5794 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5795 Lo = Result.Val->getOperand(0); 5796 Hi = Result.Val->getOperand(1); 5797 break; 5798 } 5799 // fall through 5800 default: 5801#ifndef NDEBUG 5802 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5803#endif 5804 assert(0 && "Do not know how to expand this operator!"); 5805 abort(); 5806 case ISD::EXTRACT_ELEMENT: 5807 ExpandOp(Node->getOperand(0), Lo, Hi); 5808 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5809 return ExpandOp(Hi, Lo, Hi); 5810 return ExpandOp(Lo, Lo, Hi); 5811 case ISD::EXTRACT_VECTOR_ELT: 5812 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5813 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5814 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5815 return ExpandOp(Lo, Lo, Hi); 5816 case ISD::UNDEF: 5817 NVT = TLI.getTypeToExpandTo(VT); 5818 Lo = DAG.getNode(ISD::UNDEF, NVT); 5819 Hi = DAG.getNode(ISD::UNDEF, NVT); 5820 break; 5821 case ISD::Constant: { 5822 unsigned NVTBits = MVT::getSizeInBits(NVT); 5823 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5824 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5825 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5826 break; 5827 } 5828 case ISD::ConstantFP: { 5829 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5830 if (CFP->getValueType(0) == MVT::ppcf128) { 5831 APInt api = CFP->getValueAPF().convertToAPInt(); 5832 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5833 MVT::f64); 5834 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5835 MVT::f64); 5836 break; 5837 } 5838 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5839 if (getTypeAction(Lo.getValueType()) == Expand) 5840 ExpandOp(Lo, Lo, Hi); 5841 break; 5842 } 5843 case ISD::BUILD_PAIR: 5844 // Return the operands. 5845 Lo = Node->getOperand(0); 5846 Hi = Node->getOperand(1); 5847 break; 5848 5849 case ISD::MERGE_VALUES: 5850 if (Node->getNumValues() == 1) { 5851 ExpandOp(Op.getOperand(0), Lo, Hi); 5852 break; 5853 } 5854 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5855 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5856 Op.getValue(1).getValueType() == MVT::Other && 5857 "unhandled MERGE_VALUES"); 5858 ExpandOp(Op.getOperand(0), Lo, Hi); 5859 // Remember that we legalized the chain. 5860 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5861 break; 5862 5863 case ISD::SIGN_EXTEND_INREG: 5864 ExpandOp(Node->getOperand(0), Lo, Hi); 5865 // sext_inreg the low part if needed. 5866 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5867 5868 // The high part gets the sign extension from the lo-part. This handles 5869 // things like sextinreg V:i64 from i8. 5870 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5871 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5872 TLI.getShiftAmountTy())); 5873 break; 5874 5875 case ISD::BSWAP: { 5876 ExpandOp(Node->getOperand(0), Lo, Hi); 5877 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5878 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5879 Lo = TempLo; 5880 break; 5881 } 5882 5883 case ISD::CTPOP: 5884 ExpandOp(Node->getOperand(0), Lo, Hi); 5885 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5886 DAG.getNode(ISD::CTPOP, NVT, Lo), 5887 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5888 Hi = DAG.getConstant(0, NVT); 5889 break; 5890 5891 case ISD::CTLZ: { 5892 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5893 ExpandOp(Node->getOperand(0), Lo, Hi); 5894 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5895 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5896 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5897 ISD::SETNE); 5898 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5899 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5900 5901 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5902 Hi = DAG.getConstant(0, NVT); 5903 break; 5904 } 5905 5906 case ISD::CTTZ: { 5907 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5908 ExpandOp(Node->getOperand(0), Lo, Hi); 5909 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5910 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5911 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5912 ISD::SETNE); 5913 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5914 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5915 5916 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5917 Hi = DAG.getConstant(0, NVT); 5918 break; 5919 } 5920 5921 case ISD::VAARG: { 5922 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5923 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5924 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5925 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5926 5927 // Remember that we legalized the chain. 5928 Hi = LegalizeOp(Hi); 5929 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5930 if (TLI.isBigEndian()) 5931 std::swap(Lo, Hi); 5932 break; 5933 } 5934 5935 case ISD::LOAD: { 5936 LoadSDNode *LD = cast<LoadSDNode>(Node); 5937 SDOperand Ch = LD->getChain(); // Legalize the chain. 5938 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5939 ISD::LoadExtType ExtType = LD->getExtensionType(); 5940 int SVOffset = LD->getSrcValueOffset(); 5941 unsigned Alignment = LD->getAlignment(); 5942 bool isVolatile = LD->isVolatile(); 5943 5944 if (ExtType == ISD::NON_EXTLOAD) { 5945 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5946 isVolatile, Alignment); 5947 if (VT == MVT::f32 || VT == MVT::f64) { 5948 // f32->i32 or f64->i64 one to one expansion. 5949 // Remember that we legalized the chain. 5950 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5951 // Recursively expand the new load. 5952 if (getTypeAction(NVT) == Expand) 5953 ExpandOp(Lo, Lo, Hi); 5954 break; 5955 } 5956 5957 // Increment the pointer to the other half. 5958 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5959 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5960 DAG.getIntPtrConstant(IncrementSize)); 5961 SVOffset += IncrementSize; 5962 Alignment = MinAlign(Alignment, IncrementSize); 5963 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5964 isVolatile, Alignment); 5965 5966 // Build a factor node to remember that this load is independent of the 5967 // other one. 5968 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5969 Hi.getValue(1)); 5970 5971 // Remember that we legalized the chain. 5972 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5973 if (TLI.isBigEndian()) 5974 std::swap(Lo, Hi); 5975 } else { 5976 MVT::ValueType EVT = LD->getMemoryVT(); 5977 5978 if ((VT == MVT::f64 && EVT == MVT::f32) || 5979 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5980 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5981 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5982 SVOffset, isVolatile, Alignment); 5983 // Remember that we legalized the chain. 5984 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5985 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5986 break; 5987 } 5988 5989 if (EVT == NVT) 5990 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5991 SVOffset, isVolatile, Alignment); 5992 else 5993 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5994 SVOffset, EVT, isVolatile, 5995 Alignment); 5996 5997 // Remember that we legalized the chain. 5998 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5999 6000 if (ExtType == ISD::SEXTLOAD) { 6001 // The high part is obtained by SRA'ing all but one of the bits of the 6002 // lo part. 6003 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 6004 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6005 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6006 } else if (ExtType == ISD::ZEXTLOAD) { 6007 // The high part is just a zero. 6008 Hi = DAG.getConstant(0, NVT); 6009 } else /* if (ExtType == ISD::EXTLOAD) */ { 6010 // The high part is undefined. 6011 Hi = DAG.getNode(ISD::UNDEF, NVT); 6012 } 6013 } 6014 break; 6015 } 6016 case ISD::AND: 6017 case ISD::OR: 6018 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6019 SDOperand LL, LH, RL, RH; 6020 ExpandOp(Node->getOperand(0), LL, LH); 6021 ExpandOp(Node->getOperand(1), RL, RH); 6022 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6023 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6024 break; 6025 } 6026 case ISD::SELECT: { 6027 SDOperand LL, LH, RL, RH; 6028 ExpandOp(Node->getOperand(1), LL, LH); 6029 ExpandOp(Node->getOperand(2), RL, RH); 6030 if (getTypeAction(NVT) == Expand) 6031 NVT = TLI.getTypeToExpandTo(NVT); 6032 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6033 if (VT != MVT::f32) 6034 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6035 break; 6036 } 6037 case ISD::SELECT_CC: { 6038 SDOperand TL, TH, FL, FH; 6039 ExpandOp(Node->getOperand(2), TL, TH); 6040 ExpandOp(Node->getOperand(3), FL, FH); 6041 if (getTypeAction(NVT) == Expand) 6042 NVT = TLI.getTypeToExpandTo(NVT); 6043 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6044 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6045 if (VT != MVT::f32) 6046 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6047 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6048 break; 6049 } 6050 case ISD::ANY_EXTEND: 6051 // The low part is any extension of the input (which degenerates to a copy). 6052 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6053 // The high part is undefined. 6054 Hi = DAG.getNode(ISD::UNDEF, NVT); 6055 break; 6056 case ISD::SIGN_EXTEND: { 6057 // The low part is just a sign extension of the input (which degenerates to 6058 // a copy). 6059 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6060 6061 // The high part is obtained by SRA'ing all but one of the bits of the lo 6062 // part. 6063 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 6064 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6065 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6066 break; 6067 } 6068 case ISD::ZERO_EXTEND: 6069 // The low part is just a zero extension of the input (which degenerates to 6070 // a copy). 6071 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6072 6073 // The high part is just a zero. 6074 Hi = DAG.getConstant(0, NVT); 6075 break; 6076 6077 case ISD::TRUNCATE: { 6078 // The input value must be larger than this value. Expand *it*. 6079 SDOperand NewLo; 6080 ExpandOp(Node->getOperand(0), NewLo, Hi); 6081 6082 // The low part is now either the right size, or it is closer. If not the 6083 // right size, make an illegal truncate so we recursively expand it. 6084 if (NewLo.getValueType() != Node->getValueType(0)) 6085 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6086 ExpandOp(NewLo, Lo, Hi); 6087 break; 6088 } 6089 6090 case ISD::BIT_CONVERT: { 6091 SDOperand Tmp; 6092 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6093 // If the target wants to, allow it to lower this itself. 6094 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6095 case Expand: assert(0 && "cannot expand FP!"); 6096 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6097 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6098 } 6099 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6100 } 6101 6102 // f32 / f64 must be expanded to i32 / i64. 6103 if (VT == MVT::f32 || VT == MVT::f64) { 6104 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6105 if (getTypeAction(NVT) == Expand) 6106 ExpandOp(Lo, Lo, Hi); 6107 break; 6108 } 6109 6110 // If source operand will be expanded to the same type as VT, i.e. 6111 // i64 <- f64, i32 <- f32, expand the source operand instead. 6112 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 6113 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6114 ExpandOp(Node->getOperand(0), Lo, Hi); 6115 break; 6116 } 6117 6118 // Turn this into a load/store pair by default. 6119 if (Tmp.Val == 0) 6120 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6121 6122 ExpandOp(Tmp, Lo, Hi); 6123 break; 6124 } 6125 6126 case ISD::READCYCLECOUNTER: { 6127 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6128 TargetLowering::Custom && 6129 "Must custom expand ReadCycleCounter"); 6130 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6131 assert(Tmp.Val && "Node must be custom expanded!"); 6132 ExpandOp(Tmp.getValue(0), Lo, Hi); 6133 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6134 LegalizeOp(Tmp.getValue(1))); 6135 break; 6136 } 6137 6138 case ISD::ATOMIC_LCS: { 6139 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6140 assert(Tmp.Val && "Node must be custom expanded!"); 6141 ExpandOp(Tmp.getValue(0), Lo, Hi); 6142 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6143 LegalizeOp(Tmp.getValue(1))); 6144 break; 6145 } 6146 6147 6148 6149 // These operators cannot be expanded directly, emit them as calls to 6150 // library functions. 6151 case ISD::FP_TO_SINT: { 6152 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6153 SDOperand Op; 6154 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6155 case Expand: assert(0 && "cannot expand FP!"); 6156 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6157 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6158 } 6159 6160 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6161 6162 // Now that the custom expander is done, expand the result, which is still 6163 // VT. 6164 if (Op.Val) { 6165 ExpandOp(Op, Lo, Hi); 6166 break; 6167 } 6168 } 6169 6170 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6171 if (VT == MVT::i64) { 6172 if (Node->getOperand(0).getValueType() == MVT::f32) 6173 LC = RTLIB::FPTOSINT_F32_I64; 6174 else if (Node->getOperand(0).getValueType() == MVT::f64) 6175 LC = RTLIB::FPTOSINT_F64_I64; 6176 else if (Node->getOperand(0).getValueType() == MVT::f80) 6177 LC = RTLIB::FPTOSINT_F80_I64; 6178 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6179 LC = RTLIB::FPTOSINT_PPCF128_I64; 6180 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6181 } else if (VT == MVT::i128) { 6182 if (Node->getOperand(0).getValueType() == MVT::f32) 6183 LC = RTLIB::FPTOSINT_F32_I128; 6184 else if (Node->getOperand(0).getValueType() == MVT::f64) 6185 LC = RTLIB::FPTOSINT_F64_I128; 6186 else if (Node->getOperand(0).getValueType() == MVT::f80) 6187 LC = RTLIB::FPTOSINT_F80_I128; 6188 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6189 LC = RTLIB::FPTOSINT_PPCF128_I128; 6190 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6191 } else { 6192 assert(0 && "Unexpected uint-to-fp conversion!"); 6193 } 6194 break; 6195 } 6196 6197 case ISD::FP_TO_UINT: { 6198 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6199 SDOperand Op; 6200 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6201 case Expand: assert(0 && "cannot expand FP!"); 6202 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6203 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6204 } 6205 6206 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6207 6208 // Now that the custom expander is done, expand the result. 6209 if (Op.Val) { 6210 ExpandOp(Op, Lo, Hi); 6211 break; 6212 } 6213 } 6214 6215 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6216 if (VT == MVT::i64) { 6217 if (Node->getOperand(0).getValueType() == MVT::f32) 6218 LC = RTLIB::FPTOUINT_F32_I64; 6219 else if (Node->getOperand(0).getValueType() == MVT::f64) 6220 LC = RTLIB::FPTOUINT_F64_I64; 6221 else if (Node->getOperand(0).getValueType() == MVT::f80) 6222 LC = RTLIB::FPTOUINT_F80_I64; 6223 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6224 LC = RTLIB::FPTOUINT_PPCF128_I64; 6225 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6226 } else if (VT == MVT::i128) { 6227 if (Node->getOperand(0).getValueType() == MVT::f32) 6228 LC = RTLIB::FPTOUINT_F32_I128; 6229 else if (Node->getOperand(0).getValueType() == MVT::f64) 6230 LC = RTLIB::FPTOUINT_F64_I128; 6231 else if (Node->getOperand(0).getValueType() == MVT::f80) 6232 LC = RTLIB::FPTOUINT_F80_I128; 6233 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6234 LC = RTLIB::FPTOUINT_PPCF128_I128; 6235 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6236 } else { 6237 assert(0 && "Unexpected uint-to-fp conversion!"); 6238 } 6239 break; 6240 } 6241 6242 case ISD::SHL: { 6243 // If the target wants custom lowering, do so. 6244 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6245 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6246 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6247 Op = TLI.LowerOperation(Op, DAG); 6248 if (Op.Val) { 6249 // Now that the custom expander is done, expand the result, which is 6250 // still VT. 6251 ExpandOp(Op, Lo, Hi); 6252 break; 6253 } 6254 } 6255 6256 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6257 // this X << 1 as X+X. 6258 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6259 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6260 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6261 SDOperand LoOps[2], HiOps[3]; 6262 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6263 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6264 LoOps[1] = LoOps[0]; 6265 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6266 6267 HiOps[1] = HiOps[0]; 6268 HiOps[2] = Lo.getValue(1); 6269 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6270 break; 6271 } 6272 } 6273 6274 // If we can emit an efficient shift operation, do so now. 6275 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6276 break; 6277 6278 // If this target supports SHL_PARTS, use it. 6279 TargetLowering::LegalizeAction Action = 6280 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6281 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6282 Action == TargetLowering::Custom) { 6283 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6284 break; 6285 } 6286 6287 // Otherwise, emit a libcall. 6288 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6289 break; 6290 } 6291 6292 case ISD::SRA: { 6293 // If the target wants custom lowering, do so. 6294 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6295 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6296 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6297 Op = TLI.LowerOperation(Op, DAG); 6298 if (Op.Val) { 6299 // Now that the custom expander is done, expand the result, which is 6300 // still VT. 6301 ExpandOp(Op, Lo, Hi); 6302 break; 6303 } 6304 } 6305 6306 // If we can emit an efficient shift operation, do so now. 6307 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6308 break; 6309 6310 // If this target supports SRA_PARTS, use it. 6311 TargetLowering::LegalizeAction Action = 6312 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6313 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6314 Action == TargetLowering::Custom) { 6315 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6316 break; 6317 } 6318 6319 // Otherwise, emit a libcall. 6320 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6321 break; 6322 } 6323 6324 case ISD::SRL: { 6325 // If the target wants custom lowering, do so. 6326 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6327 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6328 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6329 Op = TLI.LowerOperation(Op, DAG); 6330 if (Op.Val) { 6331 // Now that the custom expander is done, expand the result, which is 6332 // still VT. 6333 ExpandOp(Op, Lo, Hi); 6334 break; 6335 } 6336 } 6337 6338 // If we can emit an efficient shift operation, do so now. 6339 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6340 break; 6341 6342 // If this target supports SRL_PARTS, use it. 6343 TargetLowering::LegalizeAction Action = 6344 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6345 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6346 Action == TargetLowering::Custom) { 6347 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6348 break; 6349 } 6350 6351 // Otherwise, emit a libcall. 6352 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6353 break; 6354 } 6355 6356 case ISD::ADD: 6357 case ISD::SUB: { 6358 // If the target wants to custom expand this, let them. 6359 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6360 TargetLowering::Custom) { 6361 Op = TLI.LowerOperation(Op, DAG); 6362 if (Op.Val) { 6363 ExpandOp(Op, Lo, Hi); 6364 break; 6365 } 6366 } 6367 6368 // Expand the subcomponents. 6369 SDOperand LHSL, LHSH, RHSL, RHSH; 6370 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6371 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6372 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6373 SDOperand LoOps[2], HiOps[3]; 6374 LoOps[0] = LHSL; 6375 LoOps[1] = RHSL; 6376 HiOps[0] = LHSH; 6377 HiOps[1] = RHSH; 6378 if (Node->getOpcode() == ISD::ADD) { 6379 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6380 HiOps[2] = Lo.getValue(1); 6381 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6382 } else { 6383 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6384 HiOps[2] = Lo.getValue(1); 6385 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6386 } 6387 break; 6388 } 6389 6390 case ISD::ADDC: 6391 case ISD::SUBC: { 6392 // Expand the subcomponents. 6393 SDOperand LHSL, LHSH, RHSL, RHSH; 6394 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6395 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6396 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6397 SDOperand LoOps[2] = { LHSL, RHSL }; 6398 SDOperand HiOps[3] = { LHSH, RHSH }; 6399 6400 if (Node->getOpcode() == ISD::ADDC) { 6401 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6402 HiOps[2] = Lo.getValue(1); 6403 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6404 } else { 6405 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6406 HiOps[2] = Lo.getValue(1); 6407 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6408 } 6409 // Remember that we legalized the flag. 6410 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6411 break; 6412 } 6413 case ISD::ADDE: 6414 case ISD::SUBE: { 6415 // Expand the subcomponents. 6416 SDOperand LHSL, LHSH, RHSL, RHSH; 6417 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6418 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6419 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6420 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6421 SDOperand HiOps[3] = { LHSH, RHSH }; 6422 6423 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6424 HiOps[2] = Lo.getValue(1); 6425 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6426 6427 // Remember that we legalized the flag. 6428 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6429 break; 6430 } 6431 case ISD::MUL: { 6432 // If the target wants to custom expand this, let them. 6433 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6434 SDOperand New = TLI.LowerOperation(Op, DAG); 6435 if (New.Val) { 6436 ExpandOp(New, Lo, Hi); 6437 break; 6438 } 6439 } 6440 6441 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6442 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6443 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6444 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6445 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6446 SDOperand LL, LH, RL, RH; 6447 ExpandOp(Node->getOperand(0), LL, LH); 6448 ExpandOp(Node->getOperand(1), RL, RH); 6449 unsigned OuterBitSize = Op.getValueSizeInBits(); 6450 unsigned InnerBitSize = RH.getValueSizeInBits(); 6451 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6452 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6453 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6454 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6455 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6456 // The inputs are both zero-extended. 6457 if (HasUMUL_LOHI) { 6458 // We can emit a umul_lohi. 6459 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6460 Hi = SDOperand(Lo.Val, 1); 6461 break; 6462 } 6463 if (HasMULHU) { 6464 // We can emit a mulhu+mul. 6465 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6466 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6467 break; 6468 } 6469 } 6470 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6471 // The input values are both sign-extended. 6472 if (HasSMUL_LOHI) { 6473 // We can emit a smul_lohi. 6474 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6475 Hi = SDOperand(Lo.Val, 1); 6476 break; 6477 } 6478 if (HasMULHS) { 6479 // We can emit a mulhs+mul. 6480 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6481 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6482 break; 6483 } 6484 } 6485 if (HasUMUL_LOHI) { 6486 // Lo,Hi = umul LHS, RHS. 6487 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6488 DAG.getVTList(NVT, NVT), LL, RL); 6489 Lo = UMulLOHI; 6490 Hi = UMulLOHI.getValue(1); 6491 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6492 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6493 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6494 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6495 break; 6496 } 6497 if (HasMULHU) { 6498 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6499 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6500 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6501 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6502 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6503 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6504 break; 6505 } 6506 } 6507 6508 // If nothing else, we can make a libcall. 6509 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6510 break; 6511 } 6512 case ISD::SDIV: 6513 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6514 break; 6515 case ISD::UDIV: 6516 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6517 break; 6518 case ISD::SREM: 6519 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6520 break; 6521 case ISD::UREM: 6522 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6523 break; 6524 6525 case ISD::FADD: 6526 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6527 RTLIB::ADD_F64, 6528 RTLIB::ADD_F80, 6529 RTLIB::ADD_PPCF128), 6530 Node, false, Hi); 6531 break; 6532 case ISD::FSUB: 6533 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6534 RTLIB::SUB_F64, 6535 RTLIB::SUB_F80, 6536 RTLIB::SUB_PPCF128), 6537 Node, false, Hi); 6538 break; 6539 case ISD::FMUL: 6540 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6541 RTLIB::MUL_F64, 6542 RTLIB::MUL_F80, 6543 RTLIB::MUL_PPCF128), 6544 Node, false, Hi); 6545 break; 6546 case ISD::FDIV: 6547 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6548 RTLIB::DIV_F64, 6549 RTLIB::DIV_F80, 6550 RTLIB::DIV_PPCF128), 6551 Node, false, Hi); 6552 break; 6553 case ISD::FP_EXTEND: 6554 if (VT == MVT::ppcf128) { 6555 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6556 Node->getOperand(0).getValueType()==MVT::f64); 6557 const uint64_t zero = 0; 6558 if (Node->getOperand(0).getValueType()==MVT::f32) 6559 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6560 else 6561 Hi = Node->getOperand(0); 6562 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6563 break; 6564 } 6565 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi); 6566 break; 6567 case ISD::FP_ROUND: 6568 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi); 6569 break; 6570 case ISD::FPOWI: 6571 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32, 6572 RTLIB::POWI_F64, 6573 RTLIB::POWI_F80, 6574 RTLIB::POWI_PPCF128), 6575 Node, false, Hi); 6576 break; 6577 case ISD::FSQRT: 6578 case ISD::FSIN: 6579 case ISD::FCOS: { 6580 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6581 switch(Node->getOpcode()) { 6582 case ISD::FSQRT: 6583 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6584 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6585 break; 6586 case ISD::FSIN: 6587 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6588 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6589 break; 6590 case ISD::FCOS: 6591 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6592 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6593 break; 6594 default: assert(0 && "Unreachable!"); 6595 } 6596 Lo = ExpandLibCall(LC, Node, false, Hi); 6597 break; 6598 } 6599 case ISD::FABS: { 6600 if (VT == MVT::ppcf128) { 6601 SDOperand Tmp; 6602 ExpandOp(Node->getOperand(0), Lo, Tmp); 6603 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6604 // lo = hi==fabs(hi) ? lo : -lo; 6605 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6606 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6607 DAG.getCondCode(ISD::SETEQ)); 6608 break; 6609 } 6610 SDOperand Mask = (VT == MVT::f64) 6611 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6612 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6613 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6614 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6615 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6616 if (getTypeAction(NVT) == Expand) 6617 ExpandOp(Lo, Lo, Hi); 6618 break; 6619 } 6620 case ISD::FNEG: { 6621 if (VT == MVT::ppcf128) { 6622 ExpandOp(Node->getOperand(0), Lo, Hi); 6623 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6624 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6625 break; 6626 } 6627 SDOperand Mask = (VT == MVT::f64) 6628 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6629 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6630 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6631 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6632 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6633 if (getTypeAction(NVT) == Expand) 6634 ExpandOp(Lo, Lo, Hi); 6635 break; 6636 } 6637 case ISD::FCOPYSIGN: { 6638 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6639 if (getTypeAction(NVT) == Expand) 6640 ExpandOp(Lo, Lo, Hi); 6641 break; 6642 } 6643 case ISD::SINT_TO_FP: 6644 case ISD::UINT_TO_FP: { 6645 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6646 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6647 6648 // Promote the operand if needed. Do this before checking for 6649 // ppcf128 so conversions of i16 and i8 work. 6650 if (getTypeAction(SrcVT) == Promote) { 6651 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6652 Tmp = isSigned 6653 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6654 DAG.getValueType(SrcVT)) 6655 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6656 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6657 SrcVT = Node->getOperand(0).getValueType(); 6658 } 6659 6660 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6661 static const uint64_t zero = 0; 6662 if (isSigned) { 6663 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6664 Node->getOperand(0))); 6665 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6666 } else { 6667 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6668 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6669 Node->getOperand(0))); 6670 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6671 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6672 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6673 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6674 DAG.getConstant(0, MVT::i32), 6675 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6676 DAG.getConstantFP( 6677 APFloat(APInt(128, 2, TwoE32)), 6678 MVT::ppcf128)), 6679 Hi, 6680 DAG.getCondCode(ISD::SETLT)), 6681 Lo, Hi); 6682 } 6683 break; 6684 } 6685 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6686 // si64->ppcf128 done by libcall, below 6687 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6688 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6689 Lo, Hi); 6690 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6691 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6692 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6693 DAG.getConstant(0, MVT::i64), 6694 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6695 DAG.getConstantFP( 6696 APFloat(APInt(128, 2, TwoE64)), 6697 MVT::ppcf128)), 6698 Hi, 6699 DAG.getCondCode(ISD::SETLT)), 6700 Lo, Hi); 6701 break; 6702 } 6703 6704 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6705 Node->getOperand(0)); 6706 if (getTypeAction(Lo.getValueType()) == Expand) 6707 // float to i32 etc. can be 'expanded' to a single node. 6708 ExpandOp(Lo, Lo, Hi); 6709 break; 6710 } 6711 } 6712 6713 // Make sure the resultant values have been legalized themselves, unless this 6714 // is a type that requires multi-step expansion. 6715 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6716 Lo = LegalizeOp(Lo); 6717 if (Hi.Val) 6718 // Don't legalize the high part if it is expanded to a single node. 6719 Hi = LegalizeOp(Hi); 6720 } 6721 6722 // Remember in a map if the values will be reused later. 6723 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6724 assert(isNew && "Value already expanded?!?"); 6725} 6726 6727/// SplitVectorOp - Given an operand of vector type, break it down into 6728/// two smaller values, still of vector type. 6729void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6730 SDOperand &Hi) { 6731 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6732 SDNode *Node = Op.Val; 6733 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6734 assert(NumElements > 1 && "Cannot split a single element vector!"); 6735 6736 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6737 6738 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6739 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6740 6741 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); 6742 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); 6743 6744 // See if we already split it. 6745 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6746 = SplitNodes.find(Op); 6747 if (I != SplitNodes.end()) { 6748 Lo = I->second.first; 6749 Hi = I->second.second; 6750 return; 6751 } 6752 6753 switch (Node->getOpcode()) { 6754 default: 6755#ifndef NDEBUG 6756 Node->dump(&DAG); 6757#endif 6758 assert(0 && "Unhandled operation in SplitVectorOp!"); 6759 case ISD::UNDEF: 6760 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6761 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6762 break; 6763 case ISD::BUILD_PAIR: 6764 Lo = Node->getOperand(0); 6765 Hi = Node->getOperand(1); 6766 break; 6767 case ISD::INSERT_VECTOR_ELT: { 6768 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6769 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6770 unsigned Index = Idx->getValue(); 6771 SDOperand ScalarOp = Node->getOperand(1); 6772 if (Index < NewNumElts_Lo) 6773 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6774 DAG.getIntPtrConstant(Index)); 6775 else 6776 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6777 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6778 break; 6779 } 6780 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6781 Node->getOperand(1), 6782 Node->getOperand(2)); 6783 SplitVectorOp(Tmp, Lo, Hi); 6784 break; 6785 } 6786 case ISD::VECTOR_SHUFFLE: { 6787 // Build the low part. 6788 SDOperand Mask = Node->getOperand(2); 6789 SmallVector<SDOperand, 8> Ops; 6790 MVT::ValueType PtrVT = TLI.getPointerTy(); 6791 6792 // Insert all of the elements from the input that are needed. We use 6793 // buildvector of extractelement here because the input vectors will have 6794 // to be legalized, so this makes the code simpler. 6795 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6796 SDOperand IdxNode = Mask.getOperand(i); 6797 if (IdxNode.getOpcode() == ISD::UNDEF) { 6798 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6799 continue; 6800 } 6801 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6802 SDOperand InVec = Node->getOperand(0); 6803 if (Idx >= NumElements) { 6804 InVec = Node->getOperand(1); 6805 Idx -= NumElements; 6806 } 6807 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6808 DAG.getConstant(Idx, PtrVT))); 6809 } 6810 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6811 Ops.clear(); 6812 6813 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6814 SDOperand IdxNode = Mask.getOperand(i); 6815 if (IdxNode.getOpcode() == ISD::UNDEF) { 6816 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6817 continue; 6818 } 6819 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6820 SDOperand InVec = Node->getOperand(0); 6821 if (Idx >= NumElements) { 6822 InVec = Node->getOperand(1); 6823 Idx -= NumElements; 6824 } 6825 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6826 DAG.getConstant(Idx, PtrVT))); 6827 } 6828 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6829 break; 6830 } 6831 case ISD::BUILD_VECTOR: { 6832 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6833 Node->op_begin()+NewNumElts_Lo); 6834 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6835 6836 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6837 Node->op_end()); 6838 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6839 break; 6840 } 6841 case ISD::CONCAT_VECTORS: { 6842 // FIXME: Handle non-power-of-two vectors? 6843 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6844 if (NewNumSubvectors == 1) { 6845 Lo = Node->getOperand(0); 6846 Hi = Node->getOperand(1); 6847 } else { 6848 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6849 Node->op_begin()+NewNumSubvectors); 6850 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6851 6852 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6853 Node->op_end()); 6854 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6855 } 6856 break; 6857 } 6858 case ISD::SELECT: { 6859 SDOperand Cond = Node->getOperand(0); 6860 6861 SDOperand LL, LH, RL, RH; 6862 SplitVectorOp(Node->getOperand(1), LL, LH); 6863 SplitVectorOp(Node->getOperand(2), RL, RH); 6864 6865 if (MVT::isVector(Cond.getValueType())) { 6866 // Handle a vector merge. 6867 SDOperand CL, CH; 6868 SplitVectorOp(Cond, CL, CH); 6869 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6870 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6871 } else { 6872 // Handle a simple select with vector operands. 6873 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6874 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6875 } 6876 break; 6877 } 6878 case ISD::ADD: 6879 case ISD::SUB: 6880 case ISD::MUL: 6881 case ISD::FADD: 6882 case ISD::FSUB: 6883 case ISD::FMUL: 6884 case ISD::SDIV: 6885 case ISD::UDIV: 6886 case ISD::FDIV: 6887 case ISD::FPOW: 6888 case ISD::AND: 6889 case ISD::OR: 6890 case ISD::XOR: 6891 case ISD::UREM: 6892 case ISD::SREM: 6893 case ISD::FREM: { 6894 SDOperand LL, LH, RL, RH; 6895 SplitVectorOp(Node->getOperand(0), LL, LH); 6896 SplitVectorOp(Node->getOperand(1), RL, RH); 6897 6898 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6899 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6900 break; 6901 } 6902 case ISD::FPOWI: { 6903 SDOperand L, H; 6904 SplitVectorOp(Node->getOperand(0), L, H); 6905 6906 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6907 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6908 break; 6909 } 6910 case ISD::CTTZ: 6911 case ISD::CTLZ: 6912 case ISD::CTPOP: 6913 case ISD::FNEG: 6914 case ISD::FABS: 6915 case ISD::FSQRT: 6916 case ISD::FSIN: 6917 case ISD::FCOS: 6918 case ISD::FP_TO_SINT: 6919 case ISD::FP_TO_UINT: 6920 case ISD::SINT_TO_FP: 6921 case ISD::UINT_TO_FP: { 6922 SDOperand L, H; 6923 SplitVectorOp(Node->getOperand(0), L, H); 6924 6925 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6926 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6927 break; 6928 } 6929 case ISD::LOAD: { 6930 LoadSDNode *LD = cast<LoadSDNode>(Node); 6931 SDOperand Ch = LD->getChain(); 6932 SDOperand Ptr = LD->getBasePtr(); 6933 const Value *SV = LD->getSrcValue(); 6934 int SVOffset = LD->getSrcValueOffset(); 6935 unsigned Alignment = LD->getAlignment(); 6936 bool isVolatile = LD->isVolatile(); 6937 6938 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6939 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; 6940 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6941 DAG.getIntPtrConstant(IncrementSize)); 6942 SVOffset += IncrementSize; 6943 Alignment = MinAlign(Alignment, IncrementSize); 6944 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6945 6946 // Build a factor node to remember that this load is independent of the 6947 // other one. 6948 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6949 Hi.getValue(1)); 6950 6951 // Remember that we legalized the chain. 6952 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6953 break; 6954 } 6955 case ISD::BIT_CONVERT: { 6956 // We know the result is a vector. The input may be either a vector or a 6957 // scalar value. 6958 SDOperand InOp = Node->getOperand(0); 6959 if (!MVT::isVector(InOp.getValueType()) || 6960 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6961 // The input is a scalar or single-element vector. 6962 // Lower to a store/load so that it can be split. 6963 // FIXME: this could be improved probably. 6964 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6965 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val); 6966 6967 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6968 InOp, Ptr, 6969 PseudoSourceValue::getFixedStack(), 6970 FI->getIndex()); 6971 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 6972 PseudoSourceValue::getFixedStack(), 6973 FI->getIndex()); 6974 } 6975 // Split the vector and convert each of the pieces now. 6976 SplitVectorOp(InOp, Lo, Hi); 6977 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 6978 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 6979 break; 6980 } 6981 } 6982 6983 // Remember in a map if the values will be reused later. 6984 bool isNew = 6985 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6986 assert(isNew && "Value already split?!?"); 6987} 6988 6989 6990/// ScalarizeVectorOp - Given an operand of single-element vector type 6991/// (e.g. v1f32), convert it into the equivalent operation that returns a 6992/// scalar (e.g. f32) value. 6993SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6994 assert(MVT::isVector(Op.getValueType()) && 6995 "Bad ScalarizeVectorOp invocation!"); 6996 SDNode *Node = Op.Val; 6997 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6998 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6999 7000 // See if we already scalarized it. 7001 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 7002 if (I != ScalarizedNodes.end()) return I->second; 7003 7004 SDOperand Result; 7005 switch (Node->getOpcode()) { 7006 default: 7007#ifndef NDEBUG 7008 Node->dump(&DAG); cerr << "\n"; 7009#endif 7010 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7011 case ISD::ADD: 7012 case ISD::FADD: 7013 case ISD::SUB: 7014 case ISD::FSUB: 7015 case ISD::MUL: 7016 case ISD::FMUL: 7017 case ISD::SDIV: 7018 case ISD::UDIV: 7019 case ISD::FDIV: 7020 case ISD::SREM: 7021 case ISD::UREM: 7022 case ISD::FREM: 7023 case ISD::FPOW: 7024 case ISD::AND: 7025 case ISD::OR: 7026 case ISD::XOR: 7027 Result = DAG.getNode(Node->getOpcode(), 7028 NewVT, 7029 ScalarizeVectorOp(Node->getOperand(0)), 7030 ScalarizeVectorOp(Node->getOperand(1))); 7031 break; 7032 case ISD::FNEG: 7033 case ISD::FABS: 7034 case ISD::FSQRT: 7035 case ISD::FSIN: 7036 case ISD::FCOS: 7037 Result = DAG.getNode(Node->getOpcode(), 7038 NewVT, 7039 ScalarizeVectorOp(Node->getOperand(0))); 7040 break; 7041 case ISD::FPOWI: 7042 Result = DAG.getNode(Node->getOpcode(), 7043 NewVT, 7044 ScalarizeVectorOp(Node->getOperand(0)), 7045 Node->getOperand(1)); 7046 break; 7047 case ISD::LOAD: { 7048 LoadSDNode *LD = cast<LoadSDNode>(Node); 7049 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7050 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7051 7052 const Value *SV = LD->getSrcValue(); 7053 int SVOffset = LD->getSrcValueOffset(); 7054 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 7055 LD->isVolatile(), LD->getAlignment()); 7056 7057 // Remember that we legalized the chain. 7058 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7059 break; 7060 } 7061 case ISD::BUILD_VECTOR: 7062 Result = Node->getOperand(0); 7063 break; 7064 case ISD::INSERT_VECTOR_ELT: 7065 // Returning the inserted scalar element. 7066 Result = Node->getOperand(1); 7067 break; 7068 case ISD::CONCAT_VECTORS: 7069 assert(Node->getOperand(0).getValueType() == NewVT && 7070 "Concat of non-legal vectors not yet supported!"); 7071 Result = Node->getOperand(0); 7072 break; 7073 case ISD::VECTOR_SHUFFLE: { 7074 // Figure out if the scalar is the LHS or RHS and return it. 7075 SDOperand EltNum = Node->getOperand(2).getOperand(0); 7076 if (cast<ConstantSDNode>(EltNum)->getValue()) 7077 Result = ScalarizeVectorOp(Node->getOperand(1)); 7078 else 7079 Result = ScalarizeVectorOp(Node->getOperand(0)); 7080 break; 7081 } 7082 case ISD::EXTRACT_SUBVECTOR: 7083 Result = Node->getOperand(0); 7084 assert(Result.getValueType() == NewVT); 7085 break; 7086 case ISD::BIT_CONVERT: 7087 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 7088 break; 7089 case ISD::SELECT: 7090 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7091 ScalarizeVectorOp(Op.getOperand(1)), 7092 ScalarizeVectorOp(Op.getOperand(2))); 7093 break; 7094 } 7095 7096 if (TLI.isTypeLegal(NewVT)) 7097 Result = LegalizeOp(Result); 7098 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7099 assert(isNew && "Value already scalarized?"); 7100 return Result; 7101} 7102 7103 7104// SelectionDAG::Legalize - This is the entry point for the file. 7105// 7106void SelectionDAG::Legalize() { 7107 if (ViewLegalizeDAGs) viewGraph(); 7108 7109 /// run - This is the main entry point to this class. 7110 /// 7111 SelectionDAGLegalize(*this).LegalizeDAG(); 7112} 7113 7114