1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This class prints an ARM MCInst to a .s file. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMInstPrinter.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/MCAsmInfo.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/MC/MCInstrInfo.h" 21#include "llvm/MC/MCRegisterInfo.h" 22#include "llvm/Support/raw_ostream.h" 23using namespace llvm; 24 25#define DEBUG_TYPE "asm-printer" 26 27#include "ARMGenAsmWriter.inc" 28 29/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. 30/// 31/// getSORegOffset returns an integer from 0-31, representing '32' as 0. 32static unsigned translateShiftImm(unsigned imm) { 33 // lsr #32 and asr #32 exist, but should be encoded as a 0. 34 assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); 35 36 if (imm == 0) 37 return 32; 38 return imm; 39} 40 41/// Prints the shift value with an immediate value. 42static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, 43 unsigned ShImm, bool UseMarkup) { 44 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) 45 return; 46 O << ", "; 47 48 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); 49 O << getShiftOpcStr(ShOpc); 50 51 if (ShOpc != ARM_AM::rrx) { 52 O << " "; 53 if (UseMarkup) 54 O << "<imm:"; 55 O << "#" << translateShiftImm(ShImm); 56 if (UseMarkup) 57 O << ">"; 58 } 59} 60 61ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, 62 const MCInstrInfo &MII, 63 const MCRegisterInfo &MRI, 64 const MCSubtargetInfo &STI) : 65 MCInstPrinter(MAI, MII, MRI) { 66 // Initialize the set of available features. 67 setAvailableFeatures(STI.getFeatureBits()); 68} 69 70void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 71 OS << markup("<reg:") 72 << getRegisterName(RegNo) 73 << markup(">"); 74} 75 76void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 77 StringRef Annot) { 78 unsigned Opcode = MI->getOpcode(); 79 80 switch(Opcode) { 81 82 // Check for HINT instructions w/ canonical names. 83 case ARM::HINT: 84 case ARM::tHINT: 85 case ARM::t2HINT: 86 switch (MI->getOperand(0).getImm()) { 87 case 0: O << "\tnop"; break; 88 case 1: O << "\tyield"; break; 89 case 2: O << "\twfe"; break; 90 case 3: O << "\twfi"; break; 91 case 4: O << "\tsev"; break; 92 case 5: 93 if ((getAvailableFeatures() & ARM::HasV8Ops)) { 94 O << "\tsevl"; 95 break; 96 } // Fallthrough for non-v8 97 default: 98 // Anything else should just print normally. 99 printInstruction(MI, O); 100 printAnnotation(O, Annot); 101 return; 102 } 103 printPredicateOperand(MI, 1, O); 104 if (Opcode == ARM::t2HINT) 105 O << ".w"; 106 printAnnotation(O, Annot); 107 return; 108 109 // Check for MOVs and print canonical forms, instead. 110 case ARM::MOVsr: { 111 // FIXME: Thumb variants? 112 const MCOperand &Dst = MI->getOperand(0); 113 const MCOperand &MO1 = MI->getOperand(1); 114 const MCOperand &MO2 = MI->getOperand(2); 115 const MCOperand &MO3 = MI->getOperand(3); 116 117 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 118 printSBitModifierOperand(MI, 6, O); 119 printPredicateOperand(MI, 4, O); 120 121 O << '\t'; 122 printRegName(O, Dst.getReg()); 123 O << ", "; 124 printRegName(O, MO1.getReg()); 125 126 O << ", "; 127 printRegName(O, MO2.getReg()); 128 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 129 printAnnotation(O, Annot); 130 return; 131 } 132 133 case ARM::MOVsi: { 134 // FIXME: Thumb variants? 135 const MCOperand &Dst = MI->getOperand(0); 136 const MCOperand &MO1 = MI->getOperand(1); 137 const MCOperand &MO2 = MI->getOperand(2); 138 139 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 140 printSBitModifierOperand(MI, 5, O); 141 printPredicateOperand(MI, 3, O); 142 143 O << '\t'; 144 printRegName(O, Dst.getReg()); 145 O << ", "; 146 printRegName(O, MO1.getReg()); 147 148 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 149 printAnnotation(O, Annot); 150 return; 151 } 152 153 O << ", " 154 << markup("<imm:") 155 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) 156 << markup(">"); 157 printAnnotation(O, Annot); 158 return; 159 } 160 161 // A8.6.123 PUSH 162 case ARM::STMDB_UPD: 163 case ARM::t2STMDB_UPD: 164 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 165 // Should only print PUSH if there are at least two registers in the list. 166 O << '\t' << "push"; 167 printPredicateOperand(MI, 2, O); 168 if (Opcode == ARM::t2STMDB_UPD) 169 O << ".w"; 170 O << '\t'; 171 printRegisterList(MI, 4, O); 172 printAnnotation(O, Annot); 173 return; 174 } else 175 break; 176 177 case ARM::STR_PRE_IMM: 178 if (MI->getOperand(2).getReg() == ARM::SP && 179 MI->getOperand(3).getImm() == -4) { 180 O << '\t' << "push"; 181 printPredicateOperand(MI, 4, O); 182 O << "\t{"; 183 printRegName(O, MI->getOperand(1).getReg()); 184 O << "}"; 185 printAnnotation(O, Annot); 186 return; 187 } else 188 break; 189 190 // A8.6.122 POP 191 case ARM::LDMIA_UPD: 192 case ARM::t2LDMIA_UPD: 193 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 194 // Should only print POP if there are at least two registers in the list. 195 O << '\t' << "pop"; 196 printPredicateOperand(MI, 2, O); 197 if (Opcode == ARM::t2LDMIA_UPD) 198 O << ".w"; 199 O << '\t'; 200 printRegisterList(MI, 4, O); 201 printAnnotation(O, Annot); 202 return; 203 } else 204 break; 205 206 case ARM::LDR_POST_IMM: 207 if (MI->getOperand(2).getReg() == ARM::SP && 208 MI->getOperand(4).getImm() == 4) { 209 O << '\t' << "pop"; 210 printPredicateOperand(MI, 5, O); 211 O << "\t{"; 212 printRegName(O, MI->getOperand(0).getReg()); 213 O << "}"; 214 printAnnotation(O, Annot); 215 return; 216 } else 217 break; 218 219 // A8.6.355 VPUSH 220 case ARM::VSTMSDB_UPD: 221 case ARM::VSTMDDB_UPD: 222 if (MI->getOperand(0).getReg() == ARM::SP) { 223 O << '\t' << "vpush"; 224 printPredicateOperand(MI, 2, O); 225 O << '\t'; 226 printRegisterList(MI, 4, O); 227 printAnnotation(O, Annot); 228 return; 229 } else 230 break; 231 232 // A8.6.354 VPOP 233 case ARM::VLDMSIA_UPD: 234 case ARM::VLDMDIA_UPD: 235 if (MI->getOperand(0).getReg() == ARM::SP) { 236 O << '\t' << "vpop"; 237 printPredicateOperand(MI, 2, O); 238 O << '\t'; 239 printRegisterList(MI, 4, O); 240 printAnnotation(O, Annot); 241 return; 242 } else 243 break; 244 245 case ARM::tLDMIA: { 246 bool Writeback = true; 247 unsigned BaseReg = MI->getOperand(0).getReg(); 248 for (unsigned i = 3; i < MI->getNumOperands(); ++i) { 249 if (MI->getOperand(i).getReg() == BaseReg) 250 Writeback = false; 251 } 252 253 O << "\tldm"; 254 255 printPredicateOperand(MI, 1, O); 256 O << '\t'; 257 printRegName(O, BaseReg); 258 if (Writeback) O << "!"; 259 O << ", "; 260 printRegisterList(MI, 3, O); 261 printAnnotation(O, Annot); 262 return; 263 } 264 265 // Combine 2 GPRs from disassember into a GPRPair to match with instr def. 266 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 267 // a single GPRPair reg operand is used in the .td file to replace the two 268 // GPRs. However, when decoding them, the two GRPs cannot be automatically 269 // expressed as a GPRPair, so we have to manually merge them. 270 // FIXME: We would really like to be able to tablegen'erate this. 271 case ARM::LDREXD: case ARM::STREXD: 272 case ARM::LDAEXD: case ARM::STLEXD: 273 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID); 274 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD; 275 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); 276 if (MRC.contains(Reg)) { 277 MCInst NewMI; 278 MCOperand NewReg; 279 NewMI.setOpcode(Opcode); 280 281 if (isStore) 282 NewMI.addOperand(MI->getOperand(0)); 283 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0, 284 &MRI.getRegClass(ARM::GPRPairRegClassID))); 285 NewMI.addOperand(NewReg); 286 287 // Copy the rest operands into NewMI. 288 for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i) 289 NewMI.addOperand(MI->getOperand(i)); 290 printInstruction(&NewMI, O); 291 return; 292 } 293 } 294 295 printInstruction(MI, O); 296 printAnnotation(O, Annot); 297} 298 299void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 300 raw_ostream &O) { 301 const MCOperand &Op = MI->getOperand(OpNo); 302 if (Op.isReg()) { 303 unsigned Reg = Op.getReg(); 304 printRegName(O, Reg); 305 } else if (Op.isImm()) { 306 O << markup("<imm:") 307 << '#' << formatImm(Op.getImm()) 308 << markup(">"); 309 } else { 310 assert(Op.isExpr() && "unknown operand kind in printOperand"); 311 const MCExpr *Expr = Op.getExpr(); 312 switch (Expr->getKind()) { 313 case MCExpr::Binary: 314 O << '#' << *Expr; 315 break; 316 case MCExpr::Constant: { 317 // If a symbolic branch target was added as a constant expression then 318 // print that address in hex. And only print 32 unsigned bits for the 319 // address. 320 const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr); 321 int64_t TargetAddress; 322 if (!Constant->EvaluateAsAbsolute(TargetAddress)) { 323 O << '#' << *Expr; 324 } else { 325 O << "0x"; 326 O.write_hex(static_cast<uint32_t>(TargetAddress)); 327 } 328 break; 329 } 330 default: 331 // FIXME: Should we always treat this as if it is a constant literal and 332 // prefix it with '#'? 333 O << *Expr; 334 break; 335 } 336 } 337} 338 339void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, 340 raw_ostream &O) { 341 const MCOperand &MO1 = MI->getOperand(OpNum); 342 if (MO1.isExpr()) { 343 O << *MO1.getExpr(); 344 return; 345 } 346 347 O << markup("<mem:") << "[pc, "; 348 349 int32_t OffImm = (int32_t)MO1.getImm(); 350 bool isSub = OffImm < 0; 351 352 // Special value for #-0. All others are normal. 353 if (OffImm == INT32_MIN) 354 OffImm = 0; 355 if (isSub) { 356 O << markup("<imm:") 357 << "#-" << formatImm(-OffImm) 358 << markup(">"); 359 } else { 360 O << markup("<imm:") 361 << "#" << formatImm(OffImm) 362 << markup(">"); 363 } 364 O << "]" << markup(">"); 365} 366 367// so_reg is a 4-operand unit corresponding to register forms of the A5.1 368// "Addressing Mode 1 - Data-processing operands" forms. This includes: 369// REG 0 0 - e.g. R5 370// REG REG 0,SH_OPC - e.g. R5, ROR R3 371// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 372void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, 373 raw_ostream &O) { 374 const MCOperand &MO1 = MI->getOperand(OpNum); 375 const MCOperand &MO2 = MI->getOperand(OpNum+1); 376 const MCOperand &MO3 = MI->getOperand(OpNum+2); 377 378 printRegName(O, MO1.getReg()); 379 380 // Print the shift opc. 381 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); 382 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 383 if (ShOpc == ARM_AM::rrx) 384 return; 385 386 O << ' '; 387 printRegName(O, MO2.getReg()); 388 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 389} 390 391void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, 392 raw_ostream &O) { 393 const MCOperand &MO1 = MI->getOperand(OpNum); 394 const MCOperand &MO2 = MI->getOperand(OpNum+1); 395 396 printRegName(O, MO1.getReg()); 397 398 // Print the shift opc. 399 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), 400 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup); 401} 402 403 404//===--------------------------------------------------------------------===// 405// Addressing Mode #2 406//===--------------------------------------------------------------------===// 407 408void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 409 raw_ostream &O) { 410 const MCOperand &MO1 = MI->getOperand(Op); 411 const MCOperand &MO2 = MI->getOperand(Op+1); 412 const MCOperand &MO3 = MI->getOperand(Op+2); 413 414 O << markup("<mem:") << "["; 415 printRegName(O, MO1.getReg()); 416 417 if (!MO2.getReg()) { 418 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0. 419 O << ", " 420 << markup("<imm:") 421 << "#" 422 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 423 << ARM_AM::getAM2Offset(MO3.getImm()) 424 << markup(">"); 425 } 426 O << "]" << markup(">"); 427 return; 428 } 429 430 O << ", "; 431 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())); 432 printRegName(O, MO2.getReg()); 433 434 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()), 435 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup); 436 O << "]" << markup(">"); 437} 438 439void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, 440 raw_ostream &O) { 441 const MCOperand &MO1 = MI->getOperand(Op); 442 const MCOperand &MO2 = MI->getOperand(Op+1); 443 O << markup("<mem:") << "["; 444 printRegName(O, MO1.getReg()); 445 O << ", "; 446 printRegName(O, MO2.getReg()); 447 O << "]" << markup(">"); 448} 449 450void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op, 451 raw_ostream &O) { 452 const MCOperand &MO1 = MI->getOperand(Op); 453 const MCOperand &MO2 = MI->getOperand(Op+1); 454 O << markup("<mem:") << "["; 455 printRegName(O, MO1.getReg()); 456 O << ", "; 457 printRegName(O, MO2.getReg()); 458 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">"); 459} 460 461void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, 462 raw_ostream &O) { 463 const MCOperand &MO1 = MI->getOperand(Op); 464 465 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 466 printOperand(MI, Op, O); 467 return; 468 } 469 470#ifndef NDEBUG 471 const MCOperand &MO3 = MI->getOperand(Op+2); 472 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); 473 assert(IdxMode != ARMII::IndexModePost && 474 "Should be pre or offset index op"); 475#endif 476 477 printAM2PreOrOffsetIndexOp(MI, Op, O); 478} 479 480void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, 481 unsigned OpNum, 482 raw_ostream &O) { 483 const MCOperand &MO1 = MI->getOperand(OpNum); 484 const MCOperand &MO2 = MI->getOperand(OpNum+1); 485 486 if (!MO1.getReg()) { 487 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); 488 O << markup("<imm:") 489 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) 490 << ImmOffs 491 << markup(">"); 492 return; 493 } 494 495 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())); 496 printRegName(O, MO1.getReg()); 497 498 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()), 499 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup); 500} 501 502//===--------------------------------------------------------------------===// 503// Addressing Mode #3 504//===--------------------------------------------------------------------===// 505 506void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op, 507 raw_ostream &O) { 508 const MCOperand &MO1 = MI->getOperand(Op); 509 const MCOperand &MO2 = MI->getOperand(Op+1); 510 const MCOperand &MO3 = MI->getOperand(Op+2); 511 512 O << markup("<mem:") << "["; 513 printRegName(O, MO1.getReg()); 514 O << "], " << markup(">"); 515 516 if (MO2.getReg()) { 517 O << (char)ARM_AM::getAM3Op(MO3.getImm()); 518 printRegName(O, MO2.getReg()); 519 return; 520 } 521 522 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 523 O << markup("<imm:") 524 << '#' 525 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) 526 << ImmOffs 527 << markup(">"); 528} 529 530void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 531 raw_ostream &O, 532 bool AlwaysPrintImm0) { 533 const MCOperand &MO1 = MI->getOperand(Op); 534 const MCOperand &MO2 = MI->getOperand(Op+1); 535 const MCOperand &MO3 = MI->getOperand(Op+2); 536 537 O << markup("<mem:") << '['; 538 printRegName(O, MO1.getReg()); 539 540 if (MO2.getReg()) { 541 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())); 542 printRegName(O, MO2.getReg()); 543 O << ']' << markup(">"); 544 return; 545 } 546 547 //If the op is sub we have to print the immediate even if it is 0 548 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 549 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm()); 550 551 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) { 552 O << ", " 553 << markup("<imm:") 554 << "#" 555 << ARM_AM::getAddrOpcStr(op) 556 << ImmOffs 557 << markup(">"); 558 } 559 O << ']' << markup(">"); 560} 561 562template <bool AlwaysPrintImm0> 563void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op, 564 raw_ostream &O) { 565 const MCOperand &MO1 = MI->getOperand(Op); 566 if (!MO1.isReg()) { // For label symbolic references. 567 printOperand(MI, Op, O); 568 return; 569 } 570 571 const MCOperand &MO3 = MI->getOperand(Op+2); 572 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm()); 573 574 if (IdxMode == ARMII::IndexModePost) { 575 printAM3PostIndexOp(MI, Op, O); 576 return; 577 } 578 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); 579} 580 581void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, 582 unsigned OpNum, 583 raw_ostream &O) { 584 const MCOperand &MO1 = MI->getOperand(OpNum); 585 const MCOperand &MO2 = MI->getOperand(OpNum+1); 586 587 if (MO1.getReg()) { 588 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())); 589 printRegName(O, MO1.getReg()); 590 return; 591 } 592 593 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); 594 O << markup("<imm:") 595 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs 596 << markup(">"); 597} 598 599void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, 600 unsigned OpNum, 601 raw_ostream &O) { 602 const MCOperand &MO = MI->getOperand(OpNum); 603 unsigned Imm = MO.getImm(); 604 O << markup("<imm:") 605 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff) 606 << markup(">"); 607} 608 609void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, 610 raw_ostream &O) { 611 const MCOperand &MO1 = MI->getOperand(OpNum); 612 const MCOperand &MO2 = MI->getOperand(OpNum+1); 613 614 O << (MO2.getImm() ? "" : "-"); 615 printRegName(O, MO1.getReg()); 616} 617 618void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, 619 unsigned OpNum, 620 raw_ostream &O) { 621 const MCOperand &MO = MI->getOperand(OpNum); 622 unsigned Imm = MO.getImm(); 623 O << markup("<imm:") 624 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2) 625 << markup(">"); 626} 627 628 629void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, 630 raw_ostream &O) { 631 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum) 632 .getImm()); 633 O << ARM_AM::getAMSubModeStr(Mode); 634} 635 636template <bool AlwaysPrintImm0> 637void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, 638 raw_ostream &O) { 639 const MCOperand &MO1 = MI->getOperand(OpNum); 640 const MCOperand &MO2 = MI->getOperand(OpNum+1); 641 642 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 643 printOperand(MI, OpNum, O); 644 return; 645 } 646 647 O << markup("<mem:") << "["; 648 printRegName(O, MO1.getReg()); 649 650 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); 651 unsigned Op = ARM_AM::getAM5Op(MO2.getImm()); 652 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) { 653 O << ", " 654 << markup("<imm:") 655 << "#" 656 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm())) 657 << ImmOffs * 4 658 << markup(">"); 659 } 660 O << "]" << markup(">"); 661} 662 663void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, 664 raw_ostream &O) { 665 const MCOperand &MO1 = MI->getOperand(OpNum); 666 const MCOperand &MO2 = MI->getOperand(OpNum+1); 667 668 O << markup("<mem:") << "["; 669 printRegName(O, MO1.getReg()); 670 if (MO2.getImm()) { 671 O << ":" << (MO2.getImm() << 3); 672 } 673 O << "]" << markup(">"); 674} 675 676void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum, 677 raw_ostream &O) { 678 const MCOperand &MO1 = MI->getOperand(OpNum); 679 O << markup("<mem:") << "["; 680 printRegName(O, MO1.getReg()); 681 O << "]" << markup(">"); 682} 683 684void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, 685 unsigned OpNum, 686 raw_ostream &O) { 687 const MCOperand &MO = MI->getOperand(OpNum); 688 if (MO.getReg() == 0) 689 O << "!"; 690 else { 691 O << ", "; 692 printRegName(O, MO.getReg()); 693 } 694} 695 696void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, 697 unsigned OpNum, 698 raw_ostream &O) { 699 const MCOperand &MO = MI->getOperand(OpNum); 700 uint32_t v = ~MO.getImm(); 701 int32_t lsb = countTrailingZeros(v); 702 int32_t width = (32 - countLeadingZeros (v)) - lsb; 703 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); 704 O << markup("<imm:") << '#' << lsb << markup(">") 705 << ", " 706 << markup("<imm:") << '#' << width << markup(">"); 707} 708 709void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, 710 raw_ostream &O) { 711 unsigned val = MI->getOperand(OpNum).getImm(); 712 O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops)); 713} 714 715void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum, 716 raw_ostream &O) { 717 unsigned val = MI->getOperand(OpNum).getImm(); 718 O << ARM_ISB::InstSyncBOptToString(val); 719} 720 721void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum, 722 raw_ostream &O) { 723 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); 724 bool isASR = (ShiftOp & (1 << 5)) != 0; 725 unsigned Amt = ShiftOp & 0x1f; 726 if (isASR) { 727 O << ", asr " 728 << markup("<imm:") 729 << "#" << (Amt == 0 ? 32 : Amt) 730 << markup(">"); 731 } 732 else if (Amt) { 733 O << ", lsl " 734 << markup("<imm:") 735 << "#" << Amt 736 << markup(">"); 737 } 738} 739 740void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, 741 raw_ostream &O) { 742 unsigned Imm = MI->getOperand(OpNum).getImm(); 743 if (Imm == 0) 744 return; 745 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); 746 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">"); 747} 748 749void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, 750 raw_ostream &O) { 751 unsigned Imm = MI->getOperand(OpNum).getImm(); 752 // A shift amount of 32 is encoded as 0. 753 if (Imm == 0) 754 Imm = 32; 755 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); 756 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">"); 757} 758 759void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, 760 raw_ostream &O) { 761 O << "{"; 762 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { 763 if (i != OpNum) O << ", "; 764 printRegName(O, MI->getOperand(i).getReg()); 765 } 766 O << "}"; 767} 768 769void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum, 770 raw_ostream &O) { 771 unsigned Reg = MI->getOperand(OpNum).getReg(); 772 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0)); 773 O << ", "; 774 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1)); 775} 776 777 778void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, 779 raw_ostream &O) { 780 const MCOperand &Op = MI->getOperand(OpNum); 781 if (Op.getImm()) 782 O << "be"; 783 else 784 O << "le"; 785} 786 787void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum, 788 raw_ostream &O) { 789 const MCOperand &Op = MI->getOperand(OpNum); 790 O << ARM_PROC::IModToString(Op.getImm()); 791} 792 793void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum, 794 raw_ostream &O) { 795 const MCOperand &Op = MI->getOperand(OpNum); 796 unsigned IFlags = Op.getImm(); 797 for (int i=2; i >= 0; --i) 798 if (IFlags & (1 << i)) 799 O << ARM_PROC::IFlagsToString(1 << i); 800 801 if (IFlags == 0) 802 O << "none"; 803} 804 805void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, 806 raw_ostream &O) { 807 const MCOperand &Op = MI->getOperand(OpNum); 808 unsigned SpecRegRBit = Op.getImm() >> 4; 809 unsigned Mask = Op.getImm() & 0xf; 810 811 if (getAvailableFeatures() & ARM::FeatureMClass) { 812 unsigned SYSm = Op.getImm(); 813 unsigned Opcode = MI->getOpcode(); 814 // For reads of the special registers ignore the "mask encoding" bits 815 // which are only for writes. 816 if (Opcode == ARM::t2MRS_M) 817 SYSm &= 0xff; 818 switch (SYSm) { 819 default: llvm_unreachable("Unexpected mask value!"); 820 case 0: 821 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr 822 case 0x400: O << "apsr_g"; return; 823 case 0xc00: O << "apsr_nzcvqg"; return; 824 case 1: 825 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr 826 case 0x401: O << "iapsr_g"; return; 827 case 0xc01: O << "iapsr_nzcvqg"; return; 828 case 2: 829 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr 830 case 0x402: O << "eapsr_g"; return; 831 case 0xc02: O << "eapsr_nzcvqg"; return; 832 case 3: 833 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr 834 case 0x403: O << "xpsr_g"; return; 835 case 0xc03: O << "xpsr_nzcvqg"; return; 836 case 5: 837 case 0x805: O << "ipsr"; return; 838 case 6: 839 case 0x806: O << "epsr"; return; 840 case 7: 841 case 0x807: O << "iepsr"; return; 842 case 8: 843 case 0x808: O << "msp"; return; 844 case 9: 845 case 0x809: O << "psp"; return; 846 case 0x10: 847 case 0x810: O << "primask"; return; 848 case 0x11: 849 case 0x811: O << "basepri"; return; 850 case 0x12: 851 case 0x812: O << "basepri_max"; return; 852 case 0x13: 853 case 0x813: O << "faultmask"; return; 854 case 0x14: 855 case 0x814: O << "control"; return; 856 } 857 } 858 859 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as 860 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. 861 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { 862 O << "APSR_"; 863 switch (Mask) { 864 default: llvm_unreachable("Unexpected mask value!"); 865 case 4: O << "g"; return; 866 case 8: O << "nzcvq"; return; 867 case 12: O << "nzcvqg"; return; 868 } 869 } 870 871 if (SpecRegRBit) 872 O << "SPSR"; 873 else 874 O << "CPSR"; 875 876 if (Mask) { 877 O << '_'; 878 if (Mask & 8) O << 'f'; 879 if (Mask & 4) O << 's'; 880 if (Mask & 2) O << 'x'; 881 if (Mask & 1) O << 'c'; 882 } 883} 884 885void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, 886 raw_ostream &O) { 887 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 888 // Handle the undefined 15 CC value here for printing so we don't abort(). 889 if ((unsigned)CC == 15) 890 O << "<und>"; 891 else if (CC != ARMCC::AL) 892 O << ARMCondCodeToString(CC); 893} 894 895void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, 896 unsigned OpNum, 897 raw_ostream &O) { 898 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 899 O << ARMCondCodeToString(CC); 900} 901 902void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, 903 raw_ostream &O) { 904 if (MI->getOperand(OpNum).getReg()) { 905 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && 906 "Expect ARM CPSR register!"); 907 O << 's'; 908 } 909} 910 911void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, 912 raw_ostream &O) { 913 O << MI->getOperand(OpNum).getImm(); 914} 915 916void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum, 917 raw_ostream &O) { 918 O << "p" << MI->getOperand(OpNum).getImm(); 919} 920 921void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum, 922 raw_ostream &O) { 923 O << "c" << MI->getOperand(OpNum).getImm(); 924} 925 926void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum, 927 raw_ostream &O) { 928 O << "{" << MI->getOperand(OpNum).getImm() << "}"; 929} 930 931void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, 932 raw_ostream &O) { 933 llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); 934} 935 936template<unsigned scale> 937void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum, 938 raw_ostream &O) { 939 const MCOperand &MO = MI->getOperand(OpNum); 940 941 if (MO.isExpr()) { 942 O << *MO.getExpr(); 943 return; 944 } 945 946 int32_t OffImm = (int32_t)MO.getImm() << scale; 947 948 O << markup("<imm:"); 949 if (OffImm == INT32_MIN) 950 O << "#-0"; 951 else if (OffImm < 0) 952 O << "#-" << -OffImm; 953 else 954 O << "#" << OffImm; 955 O << markup(">"); 956} 957 958void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, 959 raw_ostream &O) { 960 O << markup("<imm:") 961 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4) 962 << markup(">"); 963} 964 965void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, 966 raw_ostream &O) { 967 unsigned Imm = MI->getOperand(OpNum).getImm(); 968 O << markup("<imm:") 969 << "#" << formatImm((Imm == 0 ? 32 : Imm)) 970 << markup(">"); 971} 972 973void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, 974 raw_ostream &O) { 975 // (3 - the number of trailing zeros) is the number of then / else. 976 unsigned Mask = MI->getOperand(OpNum).getImm(); 977 unsigned Firstcond = MI->getOperand(OpNum-1).getImm(); 978 unsigned CondBit0 = Firstcond & 1; 979 unsigned NumTZ = countTrailingZeros(Mask); 980 assert(NumTZ <= 3 && "Invalid IT mask!"); 981 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 982 bool T = ((Mask >> Pos) & 1) == CondBit0; 983 if (T) 984 O << 't'; 985 else 986 O << 'e'; 987 } 988} 989 990void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, 991 raw_ostream &O) { 992 const MCOperand &MO1 = MI->getOperand(Op); 993 const MCOperand &MO2 = MI->getOperand(Op + 1); 994 995 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 996 printOperand(MI, Op, O); 997 return; 998 } 999 1000 O << markup("<mem:") << "["; 1001 printRegName(O, MO1.getReg()); 1002 if (unsigned RegNum = MO2.getReg()) { 1003 O << ", "; 1004 printRegName(O, RegNum); 1005 } 1006 O << "]" << markup(">"); 1007} 1008 1009void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, 1010 unsigned Op, 1011 raw_ostream &O, 1012 unsigned Scale) { 1013 const MCOperand &MO1 = MI->getOperand(Op); 1014 const MCOperand &MO2 = MI->getOperand(Op + 1); 1015 1016 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 1017 printOperand(MI, Op, O); 1018 return; 1019 } 1020 1021 O << markup("<mem:") << "["; 1022 printRegName(O, MO1.getReg()); 1023 if (unsigned ImmOffs = MO2.getImm()) { 1024 O << ", " 1025 << markup("<imm:") 1026 << "#" << formatImm(ImmOffs * Scale) 1027 << markup(">"); 1028 } 1029 O << "]" << markup(">"); 1030} 1031 1032void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI, 1033 unsigned Op, 1034 raw_ostream &O) { 1035 printThumbAddrModeImm5SOperand(MI, Op, O, 1); 1036} 1037 1038void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI, 1039 unsigned Op, 1040 raw_ostream &O) { 1041 printThumbAddrModeImm5SOperand(MI, Op, O, 2); 1042} 1043 1044void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI, 1045 unsigned Op, 1046 raw_ostream &O) { 1047 printThumbAddrModeImm5SOperand(MI, Op, O, 4); 1048} 1049 1050void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, 1051 raw_ostream &O) { 1052 printThumbAddrModeImm5SOperand(MI, Op, O, 4); 1053} 1054 1055// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 1056// register with shift forms. 1057// REG 0 0 - e.g. R5 1058// REG IMM, SH_OPC - e.g. R5, LSL #3 1059void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, 1060 raw_ostream &O) { 1061 const MCOperand &MO1 = MI->getOperand(OpNum); 1062 const MCOperand &MO2 = MI->getOperand(OpNum+1); 1063 1064 unsigned Reg = MO1.getReg(); 1065 printRegName(O, Reg); 1066 1067 // Print the shift opc. 1068 assert(MO2.isImm() && "Not a valid t2_so_reg value!"); 1069 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), 1070 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup); 1071} 1072 1073template <bool AlwaysPrintImm0> 1074void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, 1075 raw_ostream &O) { 1076 const MCOperand &MO1 = MI->getOperand(OpNum); 1077 const MCOperand &MO2 = MI->getOperand(OpNum+1); 1078 1079 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 1080 printOperand(MI, OpNum, O); 1081 return; 1082 } 1083 1084 O << markup("<mem:") << "["; 1085 printRegName(O, MO1.getReg()); 1086 1087 int32_t OffImm = (int32_t)MO2.getImm(); 1088 bool isSub = OffImm < 0; 1089 // Special value for #-0. All others are normal. 1090 if (OffImm == INT32_MIN) 1091 OffImm = 0; 1092 if (isSub) { 1093 O << ", " 1094 << markup("<imm:") 1095 << "#-" << formatImm(-OffImm) 1096 << markup(">"); 1097 } 1098 else if (AlwaysPrintImm0 || OffImm > 0) { 1099 O << ", " 1100 << markup("<imm:") 1101 << "#" << formatImm(OffImm) 1102 << markup(">"); 1103 } 1104 O << "]" << markup(">"); 1105} 1106 1107template<bool AlwaysPrintImm0> 1108void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, 1109 unsigned OpNum, 1110 raw_ostream &O) { 1111 const MCOperand &MO1 = MI->getOperand(OpNum); 1112 const MCOperand &MO2 = MI->getOperand(OpNum+1); 1113 1114 O << markup("<mem:") << "["; 1115 printRegName(O, MO1.getReg()); 1116 1117 int32_t OffImm = (int32_t)MO2.getImm(); 1118 bool isSub = OffImm < 0; 1119 // Don't print +0. 1120 if (OffImm == INT32_MIN) 1121 OffImm = 0; 1122 if (isSub) { 1123 O << ", " 1124 << markup("<imm:") 1125 << "#-" << -OffImm 1126 << markup(">"); 1127 } else if (AlwaysPrintImm0 || OffImm > 0) { 1128 O << ", " 1129 << markup("<imm:") 1130 << "#" << OffImm 1131 << markup(">"); 1132 } 1133 O << "]" << markup(">"); 1134} 1135 1136template<bool AlwaysPrintImm0> 1137void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, 1138 unsigned OpNum, 1139 raw_ostream &O) { 1140 const MCOperand &MO1 = MI->getOperand(OpNum); 1141 const MCOperand &MO2 = MI->getOperand(OpNum+1); 1142 1143 if (!MO1.isReg()) { // For label symbolic references. 1144 printOperand(MI, OpNum, O); 1145 return; 1146 } 1147 1148 O << markup("<mem:") << "["; 1149 printRegName(O, MO1.getReg()); 1150 1151 int32_t OffImm = (int32_t)MO2.getImm(); 1152 bool isSub = OffImm < 0; 1153 1154 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 1155 1156 // Don't print +0. 1157 if (OffImm == INT32_MIN) 1158 OffImm = 0; 1159 if (isSub) { 1160 O << ", " 1161 << markup("<imm:") 1162 << "#-" << -OffImm 1163 << markup(">"); 1164 } else if (AlwaysPrintImm0 || OffImm > 0) { 1165 O << ", " 1166 << markup("<imm:") 1167 << "#" << OffImm 1168 << markup(">"); 1169 } 1170 O << "]" << markup(">"); 1171} 1172 1173void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI, 1174 unsigned OpNum, 1175 raw_ostream &O) { 1176 const MCOperand &MO1 = MI->getOperand(OpNum); 1177 const MCOperand &MO2 = MI->getOperand(OpNum+1); 1178 1179 O << markup("<mem:") << "["; 1180 printRegName(O, MO1.getReg()); 1181 if (MO2.getImm()) { 1182 O << ", " 1183 << markup("<imm:") 1184 << "#" << formatImm(MO2.getImm() * 4) 1185 << markup(">"); 1186 } 1187 O << "]" << markup(">"); 1188} 1189 1190void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, 1191 unsigned OpNum, 1192 raw_ostream &O) { 1193 const MCOperand &MO1 = MI->getOperand(OpNum); 1194 int32_t OffImm = (int32_t)MO1.getImm(); 1195 O << ", " << markup("<imm:"); 1196 if (OffImm == INT32_MIN) 1197 O << "#-0"; 1198 else if (OffImm < 0) 1199 O << "#-" << -OffImm; 1200 else 1201 O << "#" << OffImm; 1202 O << markup(">"); 1203} 1204 1205void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, 1206 unsigned OpNum, 1207 raw_ostream &O) { 1208 const MCOperand &MO1 = MI->getOperand(OpNum); 1209 int32_t OffImm = (int32_t)MO1.getImm(); 1210 1211 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 1212 1213 O << ", " << markup("<imm:"); 1214 if (OffImm == INT32_MIN) 1215 O << "#-0"; 1216 else if (OffImm < 0) 1217 O << "#-" << -OffImm; 1218 else 1219 O << "#" << OffImm; 1220 O << markup(">"); 1221} 1222 1223void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, 1224 unsigned OpNum, 1225 raw_ostream &O) { 1226 const MCOperand &MO1 = MI->getOperand(OpNum); 1227 const MCOperand &MO2 = MI->getOperand(OpNum+1); 1228 const MCOperand &MO3 = MI->getOperand(OpNum+2); 1229 1230 O << markup("<mem:") << "["; 1231 printRegName(O, MO1.getReg()); 1232 1233 assert(MO2.getReg() && "Invalid so_reg load / store address!"); 1234 O << ", "; 1235 printRegName(O, MO2.getReg()); 1236 1237 unsigned ShAmt = MO3.getImm(); 1238 if (ShAmt) { 1239 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); 1240 O << ", lsl " 1241 << markup("<imm:") 1242 << "#" << ShAmt 1243 << markup(">"); 1244 } 1245 O << "]" << markup(">"); 1246} 1247 1248void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 1249 raw_ostream &O) { 1250 const MCOperand &MO = MI->getOperand(OpNum); 1251 O << markup("<imm:") 1252 << '#' << ARM_AM::getFPImmFloat(MO.getImm()) 1253 << markup(">"); 1254} 1255 1256void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, 1257 raw_ostream &O) { 1258 unsigned EncodedImm = MI->getOperand(OpNum).getImm(); 1259 unsigned EltBits; 1260 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); 1261 O << markup("<imm:") 1262 << "#0x"; 1263 O.write_hex(Val); 1264 O << markup(">"); 1265} 1266 1267void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, 1268 raw_ostream &O) { 1269 unsigned Imm = MI->getOperand(OpNum).getImm(); 1270 O << markup("<imm:") 1271 << "#" << formatImm(Imm + 1) 1272 << markup(">"); 1273} 1274 1275void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum, 1276 raw_ostream &O) { 1277 unsigned Imm = MI->getOperand(OpNum).getImm(); 1278 if (Imm == 0) 1279 return; 1280 O << ", ror " 1281 << markup("<imm:") 1282 << "#"; 1283 switch (Imm) { 1284 default: assert (0 && "illegal ror immediate!"); 1285 case 1: O << "8"; break; 1286 case 2: O << "16"; break; 1287 case 3: O << "24"; break; 1288 } 1289 O << markup(">"); 1290} 1291 1292void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum, 1293 raw_ostream &O) { 1294 O << markup("<imm:") 1295 << "#" << 16 - MI->getOperand(OpNum).getImm() 1296 << markup(">"); 1297} 1298 1299void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum, 1300 raw_ostream &O) { 1301 O << markup("<imm:") 1302 << "#" << 32 - MI->getOperand(OpNum).getImm() 1303 << markup(">"); 1304} 1305 1306void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 1307 raw_ostream &O) { 1308 O << "[" << MI->getOperand(OpNum).getImm() << "]"; 1309} 1310 1311void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum, 1312 raw_ostream &O) { 1313 O << "{"; 1314 printRegName(O, MI->getOperand(OpNum).getReg()); 1315 O << "}"; 1316} 1317 1318void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum, 1319 raw_ostream &O) { 1320 unsigned Reg = MI->getOperand(OpNum).getReg(); 1321 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1322 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1323 O << "{"; 1324 printRegName(O, Reg0); 1325 O << ", "; 1326 printRegName(O, Reg1); 1327 O << "}"; 1328} 1329 1330void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, 1331 unsigned OpNum, 1332 raw_ostream &O) { 1333 unsigned Reg = MI->getOperand(OpNum).getReg(); 1334 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1335 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1336 O << "{"; 1337 printRegName(O, Reg0); 1338 O << ", "; 1339 printRegName(O, Reg1); 1340 O << "}"; 1341} 1342 1343void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum, 1344 raw_ostream &O) { 1345 // Normally, it's not safe to use register enum values directly with 1346 // addition to get the next register, but for VFP registers, the 1347 // sort order is guaranteed because they're all of the form D<n>. 1348 O << "{"; 1349 printRegName(O, MI->getOperand(OpNum).getReg()); 1350 O << ", "; 1351 printRegName(O, MI->getOperand(OpNum).getReg() + 1); 1352 O << ", "; 1353 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1354 O << "}"; 1355} 1356 1357void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum, 1358 raw_ostream &O) { 1359 // Normally, it's not safe to use register enum values directly with 1360 // addition to get the next register, but for VFP registers, the 1361 // sort order is guaranteed because they're all of the form D<n>. 1362 O << "{"; 1363 printRegName(O, MI->getOperand(OpNum).getReg()); 1364 O << ", "; 1365 printRegName(O, MI->getOperand(OpNum).getReg() + 1); 1366 O << ", "; 1367 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1368 O << ", "; 1369 printRegName(O, MI->getOperand(OpNum).getReg() + 3); 1370 O << "}"; 1371} 1372 1373void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI, 1374 unsigned OpNum, 1375 raw_ostream &O) { 1376 O << "{"; 1377 printRegName(O, MI->getOperand(OpNum).getReg()); 1378 O << "[]}"; 1379} 1380 1381void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI, 1382 unsigned OpNum, 1383 raw_ostream &O) { 1384 unsigned Reg = MI->getOperand(OpNum).getReg(); 1385 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1386 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1387 O << "{"; 1388 printRegName(O, Reg0); 1389 O << "[], "; 1390 printRegName(O, Reg1); 1391 O << "[]}"; 1392} 1393 1394void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI, 1395 unsigned OpNum, 1396 raw_ostream &O) { 1397 // Normally, it's not safe to use register enum values directly with 1398 // addition to get the next register, but for VFP registers, the 1399 // sort order is guaranteed because they're all of the form D<n>. 1400 O << "{"; 1401 printRegName(O, MI->getOperand(OpNum).getReg()); 1402 O << "[], "; 1403 printRegName(O, MI->getOperand(OpNum).getReg() + 1); 1404 O << "[], "; 1405 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1406 O << "[]}"; 1407} 1408 1409void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI, 1410 unsigned OpNum, 1411 raw_ostream &O) { 1412 // Normally, it's not safe to use register enum values directly with 1413 // addition to get the next register, but for VFP registers, the 1414 // sort order is guaranteed because they're all of the form D<n>. 1415 O << "{"; 1416 printRegName(O, MI->getOperand(OpNum).getReg()); 1417 O << "[], "; 1418 printRegName(O, MI->getOperand(OpNum).getReg() + 1); 1419 O << "[], "; 1420 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1421 O << "[], "; 1422 printRegName(O, MI->getOperand(OpNum).getReg() + 3); 1423 O << "[]}"; 1424} 1425 1426void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI, 1427 unsigned OpNum, 1428 raw_ostream &O) { 1429 unsigned Reg = MI->getOperand(OpNum).getReg(); 1430 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1431 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1432 O << "{"; 1433 printRegName(O, Reg0); 1434 O << "[], "; 1435 printRegName(O, Reg1); 1436 O << "[]}"; 1437} 1438 1439void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI, 1440 unsigned OpNum, 1441 raw_ostream &O) { 1442 // Normally, it's not safe to use register enum values directly with 1443 // addition to get the next register, but for VFP registers, the 1444 // sort order is guaranteed because they're all of the form D<n>. 1445 O << "{"; 1446 printRegName(O, MI->getOperand(OpNum).getReg()); 1447 O << "[], "; 1448 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1449 O << "[], "; 1450 printRegName(O, MI->getOperand(OpNum).getReg() + 4); 1451 O << "[]}"; 1452} 1453 1454void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI, 1455 unsigned OpNum, 1456 raw_ostream &O) { 1457 // Normally, it's not safe to use register enum values directly with 1458 // addition to get the next register, but for VFP registers, the 1459 // sort order is guaranteed because they're all of the form D<n>. 1460 O << "{"; 1461 printRegName(O, MI->getOperand(OpNum).getReg()); 1462 O << "[], "; 1463 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1464 O << "[], "; 1465 printRegName(O, MI->getOperand(OpNum).getReg() + 4); 1466 O << "[], "; 1467 printRegName(O, MI->getOperand(OpNum).getReg() + 6); 1468 O << "[]}"; 1469} 1470 1471void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI, 1472 unsigned OpNum, 1473 raw_ostream &O) { 1474 // Normally, it's not safe to use register enum values directly with 1475 // addition to get the next register, but for VFP registers, the 1476 // sort order is guaranteed because they're all of the form D<n>. 1477 O << "{"; 1478 printRegName(O, MI->getOperand(OpNum).getReg()); 1479 O << ", "; 1480 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1481 O << ", "; 1482 printRegName(O, MI->getOperand(OpNum).getReg() + 4); 1483 O << "}"; 1484} 1485 1486void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, 1487 unsigned OpNum, 1488 raw_ostream &O) { 1489 // Normally, it's not safe to use register enum values directly with 1490 // addition to get the next register, but for VFP registers, the 1491 // sort order is guaranteed because they're all of the form D<n>. 1492 O << "{"; 1493 printRegName(O, MI->getOperand(OpNum).getReg()); 1494 O << ", "; 1495 printRegName(O, MI->getOperand(OpNum).getReg() + 2); 1496 O << ", "; 1497 printRegName(O, MI->getOperand(OpNum).getReg() + 4); 1498 O << ", "; 1499 printRegName(O, MI->getOperand(OpNum).getReg() + 6); 1500 O << "}"; 1501} 1502