gen7_misc_state.c revision 206eca631b596154e8a9bf6a2d0de9fdb644b3cc
1/* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include "intel_batchbuffer.h" 25#include "intel_mipmap_tree.h" 26#include "intel_regions.h" 27#include "intel_fbo.h" 28#include "brw_context.h" 29#include "brw_state.h" 30#include "brw_defines.h" 31 32static void emit_depthbuffer(struct brw_context *brw) 33{ 34 struct intel_context *intel = &brw->intel; 35 struct gl_context *ctx = &intel->ctx; 36 struct gl_framebuffer *fb = ctx->DrawBuffer; 37 38 /* _NEW_BUFFERS */ 39 struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH); 40 struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL); 41 struct intel_mipmap_tree *depth_mt = NULL, 42 *stencil_mt = NULL, 43 *hiz_mt = NULL; 44 45 /* Amount by which drawing should be offset in order to draw to the 46 * appropriate miplevel/zoffset/cubeface. We will extract these values 47 * from depth_irb or stencil_irb once we determine which is present. 48 */ 49 uint32_t draw_x = 0, draw_y = 0; 50 51 /* Masks used to determine how much of the draw_x and draw_y offsets should 52 * be performed using the fine adjustment of "depth coordinate offset X/Y" 53 * (dw5 of 3DSTATE_DEPTH_BUFFER). Any remaining coarse adjustment will be 54 * performed by changing the base addresses of the buffers. 55 * 56 * Since the HiZ, depth, and stencil buffers all use the same "depth 57 * coordinate offset X/Y" values, we need to make sure that the coarse 58 * adjustment will be possible to apply to all three buffers. Since coarse 59 * adjustment can only be applied in multiples of the tile size, we will OR 60 * together the tile masks of all the buffers to determine which offsets to 61 * perform as fine adjustments. 62 */ 63 uint32_t tile_mask_x = 0, tile_mask_y = 0; 64 65 if (drb) 66 depth_mt = drb->mt; 67 68 if (depth_mt) { 69 hiz_mt = depth_mt->hiz_mt; 70 71 intel_region_get_tile_masks(depth_mt->region, 72 &tile_mask_x, &tile_mask_y); 73 74 if (hiz_mt) { 75 uint32_t hiz_tile_mask_x, hiz_tile_mask_y; 76 intel_region_get_tile_masks(hiz_mt->region, 77 &hiz_tile_mask_x, &hiz_tile_mask_y); 78 79 /* Each HiZ row represents 2 rows of pixels */ 80 hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1; 81 82 tile_mask_x |= hiz_tile_mask_x; 83 tile_mask_y |= hiz_tile_mask_y; 84 } 85 } 86 87 if (srb) { 88 stencil_mt = srb->mt; 89 if (stencil_mt->stencil_mt) 90 stencil_mt = stencil_mt->stencil_mt; 91 92 assert(stencil_mt->format == MESA_FORMAT_S8); 93 94 /* Stencil buffer uses 64x64 tiles. */ 95 tile_mask_x |= 63; 96 tile_mask_y |= 63; 97 } 98 99 /* Gen7 doesn't support packed depth/stencil */ 100 assert(stencil_mt == NULL || depth_mt != stencil_mt); 101 assert(!depth_mt || !_mesa_is_format_packed_depth_stencil(depth_mt->format)); 102 103 intel_emit_depth_stall_flushes(intel); 104 105 if (depth_mt == NULL) { 106 uint32_t dw1 = BRW_DEPTHFORMAT_D32_FLOAT << 18; 107 uint32_t dw3 = 0; 108 uint32_t tile_x = 0, tile_y = 0; 109 110 if (stencil_mt == NULL) { 111 dw1 |= (BRW_SURFACE_NULL << 29); 112 } else { 113 /* _NEW_STENCIL: enable stencil buffer writes */ 114 dw1 |= ((ctx->Stencil.WriteMask != 0) << 27); 115 116 draw_x = srb->draw_x; 117 draw_y = srb->draw_y; 118 tile_x = draw_x & tile_mask_x; 119 tile_y = draw_y & tile_mask_y; 120 121 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 122 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth 123 * Coordinate Offset X/Y": 124 * 125 * "The 3 LSBs of both offsets must be zero to ensure correct 126 * alignment" 127 * 128 * We have no guarantee that tile_x and tile_y are correctly aligned, 129 * since they are determined by the mipmap layout, which is only 130 * aligned to multiples of 4. 131 * 132 * So, to avoid hanging the GPU, just smash the low order 3 bits of 133 * tile_x and tile_y to 0. This is a temporary workaround until we 134 * come up with a better solution. 135 */ 136 tile_x &= ~7; 137 tile_y &= ~7; 138 139 /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */ 140 dw1 |= (BRW_SURFACE_2D << 29); 141 dw3 = ((srb->Base.Base.Width + tile_x - 1) << 4) | 142 ((srb->Base.Base.Height + tile_y - 1) << 18); 143 } 144 145 BEGIN_BATCH(7); 146 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); 147 OUT_BATCH(dw1); 148 OUT_BATCH(0); 149 OUT_BATCH(dw3); 150 OUT_BATCH(0); 151 OUT_BATCH(tile_x | (tile_y << 16)); 152 OUT_BATCH(0); 153 ADVANCE_BATCH(); 154 } else { 155 struct intel_region *region = depth_mt->region; 156 uint32_t tile_x, tile_y, offset; 157 158 draw_x = drb->draw_x; 159 draw_y = drb->draw_y; 160 tile_x = draw_x & tile_mask_x; 161 tile_y = draw_y & tile_mask_y; 162 163 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 164 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth 165 * Coordinate Offset X/Y": 166 * 167 * "The 3 LSBs of both offsets must be zero to ensure correct 168 * alignment" 169 * 170 * We have no guarantee that tile_x and tile_y are correctly aligned, 171 * since they are determined by the mipmap layout, which is only aligned 172 * to multiples of 4. 173 * 174 * So, to avoid hanging the GPU, just smash the low order 3 bits of 175 * tile_x and tile_y to 0. This is a temporary workaround until we come 176 * up with a better solution. 177 */ 178 tile_x &= ~7; 179 tile_y &= ~7; 180 181 offset = intel_region_get_aligned_offset(region, 182 draw_x & ~tile_mask_x, 183 draw_y & ~tile_mask_y); 184 185 assert(region->tiling == I915_TILING_Y); 186 187 /* _NEW_DEPTH, _NEW_STENCIL */ 188 BEGIN_BATCH(7); 189 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); 190 OUT_BATCH(((region->pitch * region->cpp) - 1) | 191 (brw_depthbuffer_format(brw) << 18) | 192 ((hiz_mt ? 1 : 0) << 22) | /* hiz enable */ 193 ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) | 194 ((ctx->Depth.Mask != 0) << 28) | 195 (BRW_SURFACE_2D << 29)); 196 OUT_RELOC(region->bo, 197 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 198 offset); 199 OUT_BATCH((((drb->Base.Base.Width + tile_x) - 1) << 4) | 200 (((drb->Base.Base.Height + tile_y) - 1) << 18)); 201 OUT_BATCH(0); 202 OUT_BATCH(tile_x | (tile_y << 16)); 203 OUT_BATCH(0); 204 ADVANCE_BATCH(); 205 } 206 207 if (hiz_mt == NULL) { 208 BEGIN_BATCH(3); 209 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); 210 OUT_BATCH(0); 211 OUT_BATCH(0); 212 ADVANCE_BATCH(); 213 } else { 214 uint32_t hiz_offset = 215 intel_region_get_aligned_offset(hiz_mt->region, 216 draw_x & ~tile_mask_x, 217 (draw_y & ~tile_mask_y) / 2); 218 BEGIN_BATCH(3); 219 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); 220 OUT_BATCH(hiz_mt->region->pitch * hiz_mt->region->cpp - 1); 221 OUT_RELOC(hiz_mt->region->bo, 222 I915_GEM_DOMAIN_RENDER, 223 I915_GEM_DOMAIN_RENDER, 224 hiz_offset); 225 ADVANCE_BATCH(); 226 } 227 228 if (stencil_mt == NULL) { 229 BEGIN_BATCH(3); 230 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); 231 OUT_BATCH(0); 232 OUT_BATCH(0); 233 ADVANCE_BATCH(); 234 } else { 235 const int enabled = intel->is_haswell ? HSW_STENCIL_ENABLED : 0; 236 237 /* Note: We can't compute the stencil offset using 238 * intel_region_get_aligned_offset(), because the stencil region claims 239 * that the region is untiled; in fact it's W tiled. 240 */ 241 uint32_t stencil_offset = 242 (draw_y & ~tile_mask_y) * stencil_mt->region->pitch + 243 (draw_x & ~tile_mask_x) * 64; 244 245 BEGIN_BATCH(3); 246 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); 247 /* The stencil buffer has quirky pitch requirements. From the Graphics 248 * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing 249 * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+], 250 * field "Surface Pitch": 251 * 252 * The pitch must be set to 2x the value computed based on width, as 253 * the stencil buffer is stored with two rows interleaved. 254 * 255 * (Note that it is not 100% clear whether this intended to apply to 256 * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would 257 * imply that it doesn't), however the comment appears on a "DevIVB+" 258 * page (which would imply that it does). Experiments with the hardware 259 * indicate that it does. 260 */ 261 OUT_BATCH(enabled | 262 (2 * stencil_mt->region->pitch * stencil_mt->region->cpp - 1)); 263 OUT_RELOC(stencil_mt->region->bo, 264 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 265 stencil_offset); 266 ADVANCE_BATCH(); 267 } 268 269 BEGIN_BATCH(3); 270 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); 271 OUT_BATCH(0); 272 OUT_BATCH(0); 273 ADVANCE_BATCH(); 274} 275 276/** 277 * \see brw_context.state.depth_region 278 */ 279const struct brw_tracked_state gen7_depthbuffer = { 280 .dirty = { 281 .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL), 282 .brw = BRW_NEW_BATCH, 283 .cache = 0, 284 }, 285 .emit = emit_depthbuffer, 286}; 287