| 68da5dfc2c2e9c0aca47431076be0cd43406d4aa |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
This patch modifies intel_region_get_aligned_offset() to make the
appropriate calculation when the blorp engine sets up a W-tiled
stencil buffer using a Y-tiled SURFACE_STATE.
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit b760c9913dcff848a2aa0e60abeb48e596ae8fee)
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 96fd94ba9421c7c3072988f999ee869534f2bc2a |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
When the blorp engine is performing a blit from one stencil buffer to
another, it sets up the surface state for these buffers as Y-tiled, so
it needs to be able to force intel_region_get_tile_masks() to return
the appropriate masks for a Y-tiled region.
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 50dec7fc2d5ba813aaa822596d124098a22db301)
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 68216f35814ab8d292f37b8c0fa0a5f181b7f20d |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for fast depth clears.
Improves citybench high-res performance 3.0% +- 0.4%, n=10. Improves
Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78). No
significant difference on openarena (n=5, didn't fast clear) or nexuiz
(n=3).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 206eca631b596154e8a9bf6a2d0de9fdb644b3cc |
|
10-May-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Set tile_x/y to 0 in the no-stencil case.
Fixes compiler warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 714b4f6184db84a738cf2d063980f0e19ab03b4b |
|
26-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.
In i965 Gen7, Mesa has for a long time used the "depth coordinate
offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
render to miplevels other than 0. Unfortunately, this doesn't work,
because these offsets must be aligned to multiples of 8, and miplevels
in the depth buffer are only guaranteed to be aligned to multiples of
4. When the offsets aren't aligned to a multiple of 8, the GPU
sometimes hangs.
As a temporary measure, to avoid GPU hangs, this patch smashes the 3
LSB's of "depth coordinate offset X/Y" to 0. This results in
incorrect rendering to mipmapped depth textures, but that seems like a
reasonable stopgap while we figure out a better solution.
Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at
texture sizes that are not powers of 2.
Reviewed-by: Chad Verace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 3ec0e55b63db3c1067f3bbf4563beb3b98a19288 |
|
15-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix mipmap offsets for HiZ and separate stencil buffers.
When rendering to a miplevel other than 0 within a color, depth,
stencil, or HiZ buffer, we need to tell the GPU to render to an offset
within the buffer, so that the data is written into the correct
miplevel. We do this using a coarse offset (in pages), and a fine
adjustment (the so-called "tile_x" and "tile_y" values, which are
measured in pixels).
We have always computed the coarse offset and fine adjustment using
intel_renderbuffer_tile_offsets() function. This worked fine for
color and combined depth/stencil buffers, but failed to work properly
when HiZ and separate stencil were in use. It failed to work because
there is only one set of fine adjustment controls shared by the HiZ,
depth, and stencil buffers, so we need to choose tile_x and tile_y
values that are compatible with the tiling of all three buffers, and
then compute separate coarse offsets for each buffer.
This patch fixes the HiZ and separate stencil case by replacing the
call to intel_renderbuffer_tile_offsets() with calls to two functions:
intel_region_get_tile_masks(), which determines how much of the
adjustment can be performed using offsets and how much can be
performed using tile_x and tile_y, and
intel_region_get_aligned_offset(), which computes the coarse offset.
intel_region_get_tile_offsets() is still used for color renderbuffers,
so to avoid code duplication, I've re-worked it to use
intel_region_get_tile_masks() and intel_region_get_aligned_offset().
On i965 Gen6, fixes piglit tests
"texturing/depthstencil-render-miplevels 1024 X" where X is one of
(depth, depth_and_stencil, depth_stencil_single_binding, depth_x,
depth_x_and_stencil, stencil, stencil_and_depth, stencil_and_depth_x).
On i965 Gen7, the variants of
"texturing/depthstencil-render-miplevels" that contain a stencil
buffer still fail, due to another problem: Gen7 seems to ignore the 3
LSB's of the tile_y adjustment (and possibly also tile_x).
v2: Removed spurious comments. Added assertions to check
preconditions of intel_region_get_aligned_offset().
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| a27c7d80afc3160a0face4b8781bf921229bc3cc |
|
06-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Stop lying about cpp and height of a stencil buffer.
When using a separate stencil buffer, i965 requires that the pitch of
the buffer (in the 3DSTATE_STENCIL_BUFFER command) be specified as 2x
the actual pitch.
Previously this was accomplished by doubling the "cpp" and "pitch"
values stored in the intel_region data structure, and halving the
height. However, this was confusing, and it led to a subtle (but
benign) bug: since a stencil buffer is W-tiled, its true height must
be aligned to a multiple of 64; we were accidentally aligning its faux
height to a multiple of 64, causing memory to be wasted.
Note that for window system stencil buffers, the DDX also doubles the
cpp and pitch values. To facilitate fixing this DDX server bug in the
future, we fix the cpp and pitch values we receive from the X server
only if cpp has the "incorrect" value of 2.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
v2: Clarify comments about the DDX.
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| fc8edbe016348a22e4631fb1e1c7f7b87301c5ec |
|
24-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set "Stencil Buffer Enable" bit on Haswell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 9f8ed9d66298e2dc5dff508e3ea723469fe06d93 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: derive intel_renderbuffer from swrast_renderbuffer
Drivers that rely on swrast need to do this, as with swrast_texture_image.
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| e6d6a10c5a2962f93d4adcd251b9a47a4e438121 |
|
12-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Fix depth buffer rendering to tile offsets.
Previously, we were saying that everything from the starting tile to
region width+height was part of the limits of our depthbuffer, even if
the tile was near the bottom of the depthbuffer. This mean that our
range was not clipping to buffer buonds if the start tile was anything
but the start of the buffer.
In bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9, this was changed to
saying that we're just rendering to a region of the size of the
renderbuffer. This is great -- we get a range that should actually
match what we want. However, the hardware's range checking occurs
after the X/Y offset addition, so we were clipping out rendering to
small depth mip levels when an X/Y offset was present. Just add
tile_x/y to the width in that case -- the WM won't produce negative
x/y values pre-offset, so we just need to get the left/bottom sides of
the region to cover our buffer.
Fixes the following Piglit regressions on gen7:
spec/ARB_depth_buffer_float/fbo-clear-formats
spec/ARB_depth_texture/fbo-clear-formats
spec/EXT_packed_depth_stencil/fbo-clear-formats
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 254b24f19511014cdf4741b73d69349ac9e931a2 |
|
11-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965: Fix compiler warnings from hiz changes.
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| f7cbd80028247b83ca6835a3f68b8d5bd28b6f70 |
|
11-Jan-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965/gen7: Fix batch length for 3DSTATE_HIER_DEPTH_BUFFER
Change from 5 to 3.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 06ad9adcb031b97af2ce9cd22b919b8befcec43b |
|
22-Dec-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965/gen7: Enable HiZ
This patch modifies all batches needed for HiZ. The batch length for
3DSTATE_HIER_DEPTH_BUFFER is also corrected from 4 to 3.
Performance +6.7% on Citybench.
num-frames: 400
resolution: 1918x1031
avg-hiz-off: 127.90 fps
avg-hiz-on: 136.50 fps
kernel: git://people.freedesktop.org/~anholt/linux.git branch=gen7-reset-sol sha=23360e4
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9 |
|
22-Dec-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Replace references to stencil region size with buffer size
It is unwise to use a stencil region's size to determine its
renderbuffer's size, because at region creation we fudge the width and
height to accomodate interleaved rows. (See the comment for MESA_FORMAT_S8
in intel_miptree_create()). Most users of stencil_region->{width,height}
should be converted to use stencil_rb->{Width,Height}.
We have already done the replacement in several locations. This patch
continues the replacement in {brw,gen7}_emit_depthbuffer(). To make those
functions look consistent, I've also done the equivalent replacement for
the depth buffer.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| fdf18b323156098ba5fb2881aa1a7888d2e0667f |
|
15-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Properly demote the depth mt format for fake packed depth/stencil.
gen7 only supports the non-packed formats, even if you associate a
real separate stencil buffer -- otherwise it's as if the depth test
always fails.
This requires a little bit of care in the match_texture_image case,
since the miptree format no longer matches the texture image format.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 0b8b6c7e974930daf12e97fb8f0b2a2cc29396d9 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Stop creating the wrapped stencil irb.
There were only two places it was really used at this point, which was
in the batchbuffer emit of the separate stencil packets for gen6/7.
Just write in the ->stencil_mt reference in those two places and ditch
all this flailing around with allocation and refcounts.
v2: Fix separate stencil on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| d84a180417d1eabd680554970f1eaaa93abcd41e |
|
17-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
This will make handling new formats (like actually exposing Z32F)
easier and more reliable.
v2: Remove the check for hiz buffer -- the MESA_FORMAT should really
be giving us the value we want even for hiz.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| da2816a45e6e3a33246a341fee72e6f893f315d9 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_renderbuffer::region with a miptree [v3]
Essentially, this patch just globally substitutes `irb->region` with
`irb->mt->region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
v2:
- Return early in intel_process_dri2_buffer_*() if region allocation
fails.
- Fix double semicolon.
- Fix miptree reference leaks in the following functions:
intel_process_dri2_buffer_with_separate_stencil()
intel_image_target_renderbuffer_storage()
v3:
- [anholt] Fix check for hiz allocation failure. Replace
``if (!irb->mt)` with ``if(!irb->mt->hiz_region)``.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| eaf4d3e6e2493a6e0b20d1205a5fb33ce500c9c2 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove the validated BO list, now that it's unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 8004a1cb95b8a195f3f4bbaa8d39d2f3297167de |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Rename region->buffer to region->bo, and remove accessor function.
We call all the other drm_intel_bo pointers in intel/*.h "bo", so this
one was rather out of place.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 8bd27a5b080157cb1d5fc0383ce45574c7b16aa5 |
|
01-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit depth stalls and flushes before changing depth state on Gen6+.
Fixes OpenArena on Gen7. Technically, adding only the first depth stall
fixes it, but the documentation says to do all three, and the Windows
driver seems to do it.
Not observed to fix anything on Gen6 yet.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38863
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| b17aab5753a6d14c9e757bedb186963b2dae8823 |
|
31-May-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move the draw_x/draw_y to the renderbuffer where it belongs.
It was originally located in the region because the tracking of
depth/color buffers was on the regions, and getting back to the irb
would have been tricky. Now, we're keying off of the renderbuffer in
more places, which means we can move these fields where they belong.
This could fix potential rendering failure with a single texture
having multiple images attached to different renderbuffers across
shareCtx (as far as I can tell, this was the only failure we could
cause, since anything else should trigger intel_render_texture in
between, for example a BindFramebuffer).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 626440add567174342d421a39252067c6a6fb901 |
|
23-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Program stencil buffers on Ivybridge.
Thanks to Chad's hard work implementing separate stencil and HiZ
support, this is entirely straightforward.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 53b53a141ee4da9bf03b42d6381823520cd2e980 |
|
23-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Add a prepare_depthbuffer function.
We need to call add_validated_bo to do proper aperture space accounting.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| a00ca90815d8df3c087c49a2a7685f739d2d5c0a |
|
23-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: gen7_emit_depthbuffer needs the _NEW_DEPTH dirty bit.
For ctx->Depth.Mask.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| bd265201da44093ce9c583fe04aa7db94f61453c |
|
23-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Remove stencil renderbuffer from gen7_depth_format.
Since Gen7 doesn't support packed depth/stencil, the stencil buffer
can't possibly be relevant for determining the depth format.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 5e48560926d43dfa8fbc148d0f1f6a3063fede48 |
|
19-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Add support for rendering to depthbuffer mipmap levels > 0.
The same as 3e43adef95ee24dd218279d2de56939b90edcb4c but for Gen7.
This doesn't quite fix GL_ARB_depth_texture/fbo-clear-formats; there's
still a 1 pixel wide black line on the right edge of the smaller squares.
The results were entirely wrong before, and are at least close now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| a98dd64af750fb6dae54b2dc02e0c5a3711156af |
|
13-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Stop caching the combined depth/stencil region in brw_context.c.
This was going to get in the way of separate depth/stencil (which
wants to know about both, and whether they are the same rb), and also
wasn't a sufficient flag for the fix in the following commit.
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|
| 8c8985bdd714f43a96ce922a7c0284d50aec3d1a |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add depth buffer support on Ivybridge.
This also disables the HiZ and separate stencil buffers. We still need
to implement stencil.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_misc_state.c
|