gen7_misc_state.c revision b17aab5753a6d14c9e757bedb186963b2dae8823 
1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "intel_batchbuffer.h"
25#include "intel_regions.h"
26#include "intel_fbo.h"
27#include "brw_context.h"
28#include "brw_state.h"
29#include "brw_defines.h"
30
31unsigned int
32gen7_depth_format(struct brw_context *brw)
33{
34   struct intel_context *intel = &brw->intel;
35   struct gl_context *ctx = &intel->ctx;
36   struct gl_framebuffer *fb = ctx->DrawBuffer;
37   struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
38   struct intel_region *region = NULL;
39
40   if (drb)
41      region = drb->region;
42   else
43      return BRW_DEPTHFORMAT_D32_FLOAT;
44
45   switch (region->cpp) {
46   case 2:
47      return BRW_DEPTHFORMAT_D16_UNORM;
48   case 4:
49      if (intel->depth_buffer_is_float)
50	 return BRW_DEPTHFORMAT_D32_FLOAT;
51      else
52	 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
53   default:
54      assert(!"Should not get here.");
55   }
56   return 0;
57}
58
59static void prepare_depthbuffer(struct brw_context *brw)
60{
61   struct intel_context *intel = &brw->intel;
62   struct gl_context *ctx = &intel->ctx;
63   struct gl_framebuffer *fb = ctx->DrawBuffer;
64   struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
65   struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
66
67   if (drb)
68      brw_add_validated_bo(brw, drb->region->buffer);
69   if (srb)
70      brw_add_validated_bo(brw, srb->region->buffer);
71}
72
73static void emit_depthbuffer(struct brw_context *brw)
74{
75   struct intel_context *intel = &brw->intel;
76   struct gl_context *ctx = &intel->ctx;
77   struct gl_framebuffer *fb = ctx->DrawBuffer;
78
79   /* _NEW_BUFFERS */
80   struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
81   struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
82
83   /* Gen7 doesn't support packed depth/stencil */
84   assert(srb == NULL || srb != drb);
85
86   if (drb == NULL) {
87      uint32_t dw1 = BRW_DEPTHFORMAT_D32_FLOAT << 18;
88      uint32_t dw3 = 0;
89
90      if (srb == NULL) {
91	 dw1 |= (BRW_SURFACE_NULL << 29);
92      } else {
93	 struct intel_region *region = srb->region;
94
95	 /* _NEW_STENCIL: enable stencil buffer writes */
96	 dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
97
98	 /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
99	 dw1 |= (BRW_SURFACE_2D << 29);
100	 dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18);
101      }
102
103      BEGIN_BATCH(7);
104      OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
105      OUT_BATCH(dw1);
106      OUT_BATCH(0);
107      OUT_BATCH(dw3);
108      OUT_BATCH(0);
109      OUT_BATCH(0);
110      OUT_BATCH(0);
111      ADVANCE_BATCH();
112   } else {
113      struct intel_region *region = drb->region;
114      uint32_t tile_x, tile_y, offset;
115
116      offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y);
117
118      assert(region->tiling == I915_TILING_Y);
119
120      /* _NEW_DEPTH, _NEW_STENCIL */
121      BEGIN_BATCH(7);
122      OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
123      OUT_BATCH(((region->pitch * region->cpp) - 1) |
124		(gen7_depth_format(brw) << 18) |
125		(0 << 22) /* no HiZ buffer */ |
126		((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) |
127		((ctx->Depth.Mask != 0) << 28) |
128		(BRW_SURFACE_2D << 29));
129      OUT_RELOC(region->buffer,
130	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
131		offset);
132      OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
133      OUT_BATCH(0);
134      OUT_BATCH(tile_x | (tile_y << 16));
135      OUT_BATCH(0);
136      ADVANCE_BATCH();
137   }
138
139   BEGIN_BATCH(4);
140   OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2));
141   OUT_BATCH(0);
142   OUT_BATCH(0);
143   OUT_BATCH(0);
144   ADVANCE_BATCH();
145
146   if (srb == NULL) {
147      BEGIN_BATCH(3);
148      OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
149      OUT_BATCH(0);
150      OUT_BATCH(0);
151      ADVANCE_BATCH();
152   } else {
153      BEGIN_BATCH(3);
154      OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
155      OUT_BATCH(srb->region->pitch * srb->region->cpp - 1);
156      OUT_RELOC(srb->region->buffer,
157	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
158		0);
159      ADVANCE_BATCH();
160   }
161
162   BEGIN_BATCH(3);
163   OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
164   OUT_BATCH(0);
165   OUT_BATCH(0);
166   ADVANCE_BATCH();
167}
168
169/**
170 * \see brw_context.state.depth_region
171 */
172const struct brw_tracked_state gen7_depthbuffer = {
173   .dirty = {
174      .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
175      .brw = BRW_NEW_BATCH,
176      .cache = 0,
177   },
178   .prepare = prepare_depthbuffer,
179   .emit = emit_depthbuffer,
180};
181