1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ****************************************************************************
11 ****************************************************************************/
12#ifndef __ASM_ARCH_OMAP_MCBSP_H
13#define __ASM_ARCH_OMAP_MCBSP_H
14
15#include <asm/hardware.h>
16
17#define OMAP730_MCBSP1_BASE 0xfffb1000
18#define OMAP730_MCBSP2_BASE 0xfffb1800
19
20#define OMAP1510_MCBSP1_BASE 0xe1011800
21#define OMAP1510_MCBSP2_BASE 0xfffb1000
22#define OMAP1510_MCBSP3_BASE 0xe1017000
23
24#define OMAP1610_MCBSP1_BASE 0xe1011800
25#define OMAP1610_MCBSP2_BASE 0xfffb1000
26#define OMAP1610_MCBSP3_BASE 0xe1017000
27
28#define OMAP24XX_MCBSP1_BASE 0x48074000
29#define OMAP24XX_MCBSP2_BASE 0x48076000
30
31#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
32#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
33
34#define RRST 0x0001
35#define RRDY 0x0002
36#define RFULL 0x0004
37#define RSYNC_ERR 0x0008
38#define RINTM(value) ((value)<<4)
39#define ABIS 0x0040
40#define DXENA 0x0080
41#define CLKSTP(value) ((value)<<11)
42#define RJUST(value) ((value)<<13)
43#define DLB 0x8000
44
45#define XRST 0x0001
46#define XRDY 0x0002
47#define XEMPTY 0x0004
48#define XSYNC_ERR 0x0008
49#define XINTM(value) ((value)<<4)
50#define GRST 0x0040
51#define FRST 0x0080
52#define SOFT 0x0100
53#define FREE 0x0200
54
55#define CLKRP 0x0001
56#define CLKXP 0x0002
57#define FSRP 0x0004
58#define FSXP 0x0008
59#define DR_STAT 0x0010
60#define DX_STAT 0x0020
61#define CLKS_STAT 0x0040
62#define SCLKME 0x0080
63#define CLKRM 0x0100
64#define CLKXM 0x0200
65#define FSRM 0x0400
66#define FSXM 0x0800
67#define RIOEN 0x1000
68#define XIOEN 0x2000
69#define IDLE_EN 0x4000
70
71#define RWDLEN1(value) ((value)<<5)
72#define RFRLEN1(value) ((value)<<8)
73
74#define XWDLEN1(value) ((value)<<5)
75#define XFRLEN1(value) ((value)<<8)
76
77#define RDATDLY(value) (value)
78#define RFIG 0x0004
79#define RCOMPAND(value) ((value)<<3)
80#define RWDLEN2(value) ((value)<<5)
81#define RFRLEN2(value) ((value)<<8)
82#define RPHASE 0x8000
83
84#define XDATDLY(value) (value)
85#define XFIG 0x0004
86#define XCOMPAND(value) ((value)<<3)
87#define XWDLEN2(value) ((value)<<5)
88#define XFRLEN2(value) ((value)<<8)
89#define XPHASE 0x8000
90
91#define CLKGDV(value) (value)
92#define FWID(value) ((value)<<8)
93
94#define FPER(value) (value)
95#define FSGM 0x1000
96#define CLKSM 0x2000
97#define CLKSP 0x4000
98#define GSYNC 0x8000
99
100#define RMCM 0x0001
101#define RCBLK(value) ((value)<<2)
102#define RPABLK(value) ((value)<<5)
103#define RPBBLK(value) ((value)<<7)
104
105#define XMCM(value) (value)
106#define XCBLK(value) ((value)<<2)
107#define XPABLK(value) ((value)<<5)
108#define XPBBLK(value) ((value)<<7)
109
110struct omap_mcbsp_reg_cfg {
111 u16 spcr2;
112 u16 spcr1;
113 u16 rcr2;
114 u16 rcr1;
115 u16 xcr2;
116 u16 xcr1;
117 u16 srgr2;
118 u16 srgr1;
119 u16 mcr2;
120 u16 mcr1;
121 u16 pcr0;
122 u16 rcerc;
123 u16 rcerd;
124 u16 xcerc;
125 u16 xcerd;
126 u16 rcere;
127 u16 rcerf;
128 u16 xcere;
129 u16 xcerf;
130 u16 rcerg;
131 u16 rcerh;
132 u16 xcerg;
133 u16 xcerh;
134};
135
136typedef enum {
137 OMAP_MCBSP1 = 0,
138 OMAP_MCBSP2,
139 OMAP_MCBSP3,
140} omap_mcbsp_id;
141
142typedef int __bitwise omap_mcbsp_io_type_t;
143#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
144#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
145
146typedef enum {
147 OMAP_MCBSP_WORD_8 = 0,
148 OMAP_MCBSP_WORD_12,
149 OMAP_MCBSP_WORD_16,
150 OMAP_MCBSP_WORD_20,
151 OMAP_MCBSP_WORD_24,
152 OMAP_MCBSP_WORD_32,
153} omap_mcbsp_word_length;
154
155typedef enum {
156 OMAP_MCBSP_CLK_RISING = 0,
157 OMAP_MCBSP_CLK_FALLING,
158} omap_mcbsp_clk_polarity;
159
160typedef enum {
161 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
162 OMAP_MCBSP_FS_ACTIVE_LOW,
163} omap_mcbsp_fs_polarity;
164
165typedef enum {
166 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
167 OMAP_MCBSP_CLK_STP_MODE_DELAY,
168} omap_mcbsp_clk_stp_mode;
169
170typedef enum {
171 OMAP_MCBSP_SPI_MASTER = 0,
172 OMAP_MCBSP_SPI_SLAVE,
173} omap_mcbsp_spi_mode;
174
175struct omap_mcbsp_spi_cfg {
176 omap_mcbsp_spi_mode spi_mode;
177 omap_mcbsp_clk_polarity rx_clock_polarity;
178 omap_mcbsp_clk_polarity tx_clock_polarity;
179 omap_mcbsp_fs_polarity fsx_polarity;
180 u8 clk_div;
181 omap_mcbsp_clk_stp_mode clk_stp_mode;
182 omap_mcbsp_word_length word_length;
183};
184
185#endif
186