| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 59d3ae6cdc4316ad338cd848251f33a236ccb36c |
|
15-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add addrspacecast instruction.
Patch by Michele Scandale!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 268c743a3ba44ada364938bc5ff9b1be219df54f |
|
26-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 41418d17cced656f91038b2482bc9d173b4974b0 |
|
08-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add ISD::FROUND for libm round()
All libm floating-point rounding functions, except for round(), had their own
ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm
adding ISD::FROUND so that round() can be custom lowered as well.
For the most part, this is straightforward. I've added an intrinsic
and a matching ISD node just like those for nearbyint() and friends. The
SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed
fround).
This will be used by the PowerPC backend in a follow-up commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| c18f4efc5dd24adcc653806455fc7ae8508e9c66 |
|
28-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 6265d5c91a18b2fb6499eb581c488315880c044d |
|
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| a6b20ced765b67a85d9219d0c8547fc9c133e14f |
|
01-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
but TLI.getShiftAmountTy() so far only return scalar type. As a
result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
return target-specificed scalar type or the same vector type as the
1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 94c22716d60ff5edf6a98a3c67e0faa001be1142 |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 7e2c793a2b5c746344652b6579e958ee42fafdcc |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| c05d30601ced172b55be81bb529df6be91d6ae15 |
|
06-Sep-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 74500bdba3eae36a1a8a17d8bad0b971b9c212ec |
|
08-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add SelectionDAG::getTargetIndex.
This adds support for TargetIndex operands during isel. The meaning of
these (index, offset, flags) operands is entirely defined by the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| f4341e4155e272ec7e72ff61e100bafb50fc8bd8 |
|
23-Jul-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Doxygenify the comments of ISD nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| f54469f7fc505e15db48b20a902dacd9809f6529 |
|
20-Jun-2012 |
Chad Rosier <mcrosier@apple.com> |
Typo. Patch by Cameron McInally <cameron.mcinally@nyu.edu>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| d9b0b025612992a0b724eeca8bdf10b1d7a5c355 |
|
02-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix typos found by http://github.com/lyda/misspell-check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| a6063c6e29746d9425bdf46d680e28a48dcf58f9 |
|
14-May-2012 |
Dan Gohman <gohman@apple.com> |
Rename @llvm.debugger to @llvm.debugtrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| d4347e1af9141ec9f8e3e527367bfd16c0cc4ffb |
|
11-May-2012 |
Dan Gohman <gohman@apple.com> |
Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
but it generates int3 on x86 instead of ud2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 9cf37e8b48732fccd4c301ed51aafed7074bd84e |
|
19-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a RegisterMaskSDNode class.
This SelectionDAG node will be attached to call nodes by LowerCall(),
and eventually becomes a MO_RegisterMask MachineOperand on the
MachineInstr representing the call instruction.
LowerCall() will attach a register mask that depends on the calling
convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| a402271351ba498a5d2bcae99a502c78a6fb15e1 |
|
18-Jan-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Document the fact that the selection dag changes the vselect condition type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 63974b2144c87c962effdc0508c27643c8ad98b6 |
|
13-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| c80383095e1fd6a5567a0126b3ee551df8a2aacd |
|
28-Nov-2011 |
Bill Wendling <isanbard@gmail.com> |
Remove dead llvm.eh.sjlj.dispatchsetup intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| ce370cfd891386d613d4bd0d28449d2705705d16 |
|
07-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
do. This will be useful later on with the new SJLJ stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 4a544a79bd735967f1d33fe675ae4566dbd17813 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 327236cd6c211e54fc6288b0ac2b413901cc0611 |
|
24-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Basic x86 code generation for atomic load and store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 14648468011c92a4210f8118721d58c25043daf8 |
|
28-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 33390848a7eca75301d04a59b89b516d83e19ee0 |
|
08-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 9a767330f555f21d6ef311d3a348d3a44f306d35 |
|
14-Jun-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 1cfac8c5348e5f079b3f8e04397c753524a34fb8 |
|
11-May-2011 |
Bill Wendling <isanbard@gmail.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| d8c7ff00191c6e585db96df55748b06cdfa207c8 |
|
13-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
fix thinko :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| e075118489baf15a7cea2e7f155b4799b93d6d02 |
|
13-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
Revisit my fix for PR9028: the issue is that DAGCombine was
generating i8 shift amounts for things like i1024 types. Add
an assert in getNode to prevent this from occuring in the future,
fix the buggy transformation, revert my previous patch, and
document this gotcha in ISDOpcodes.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| cfe33c46aa50f04adb0431243e7d25f79b719ac6 |
|
26-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR. Eventually this
will get matched to VINSERTF128 if AVX is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| c36b7069b42bece963b7e6adf020353ce990ef76 |
|
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.
This allows memory instructions to be moved around INLINEASM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 7c7e2da4aa0b0a710b22a823f744ffad6021035c |
|
07-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment. INLINEASM node operand #3 is IsAlignStack bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 6736e19f4c9af1181cedca54ba6e3a1420454928 |
|
07-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Change EXTRACT_SUBVECTOR to require a constant index.
We were never generating any of these nodes with variable indices, and there
was one legalizer function asserting on a non-constant index. If we ever have
a need to support variable indices, we can add this back again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122993 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
|
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| df7ec2083fad548d0e2bf8797f9d0ef67823c06b |
|
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Spelling typo fix. s/incput/input/. Thanks, Bob!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| e4ad387a5a88dae20f0f7578e55170bbc8eee2a9 |
|
20-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 3157ef1c13376f669a32bc152f2c3000480cedd3 |
|
21-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This is the first step towards refactoring the x86 vector shuffle code. The
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.
The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 79976e9ff18265c5b8c991db0c2ff6d2edad94fe |
|
20-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Update comment to remove special case for vector extending loads. An
extending vector load should extend each element in the same way as the
corresponding scalar extending load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 72d13ff755fe8484c89468252f945ba23fe98f71 |
|
26-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
When splitting a VAARG, remember its alignment.
This produces terrible but correct code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 2bff8abbf2c02065556332d50c4e4cf86a09034d |
|
18-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| a65850230af7f13d9111450f645886b968dea2a2 |
|
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
back out 104862/104869. Can reuse stacksave after all. Very cool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| ad9aaf038e1886013ef7118608182c479c986a97 |
|
27-May-2010 |
Jim Grosbach <grosbach@apple.com> |
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
to update the jmpbuf in the presence of VLAs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 23ff7cff52702a8bff904d8ab4c9ca67cc19d6ca |
|
26-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
ISD::. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 5eb195153950bc7ebfc30649494a78b2096b5ef8 |
|
22-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 5768ea9ca1409d7686b64607d6e0ad87d9d84c23 |
|
29-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Elaborate on a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102637 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|
| 4031d59685cef09fad651dd39020ccca4c13ef89 |
|
14-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Split ISD::NodeType and a few related items out of SelectionDAGNodes.h
into a separate header to allow clients to use them without pulling in
SelectionDAG-specific declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/CodeGen/ISDOpcodes.h
|