| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 3d478aee8e2480661cb0d98b10da8ad2ebf59fcf |
|
28-Oct-2013 |
Lang Hames <lhames@gmail.com> |
Return early from getUnconditionalBranchTargetOpValue if the branch target is
an MCExpr, in order to avoid writing an encoded zero value in the immediate
field.
When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we
don't know what the final immediate field value should be. We shouldn't
explicitly set the immediate field to an encoded zero value as zero is encoded
with a non-zero bit pattern. This leads to bits being set that pollute the
final immediate value. The nature of the encoding is such that the polluted
bits only affect very large immediate values, explaining why this hasn't
caused problems earlier.
Fixes <rdar://problem/15155975>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193535 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 441c557708b5dbe91f1799baf790ad418c23ea70 |
|
29-Aug-2013 |
Cameron Esfahani <dirty@apple.com> |
Clean up some usage of Triple. The base class has methods for determining if the target is iOS and Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| e97fc44045732de9fc4715241013f9238ec007dc |
|
16-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Add support for Thumb2 literal loads with negative zero offset
Thumb2 literal loads use an offset encoding which allows for
negative zero. This fixes parsing and encoding so that #-0
is correctly processed. The parser represents #-0 as INT32_MIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| ea8ddd86b1e364a799e57fc0ac468a9c4a8f8bcf |
|
13-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix signed overflow in when computing encodings for ADR instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| e921f323533ee751b3fa34bd00d10fa72096ffd3 |
|
09-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.
Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.
Due to this, for any mnemonic there are really 4 encodings to choose for.
The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that
order is governed by the lexicographical ordering of the names of operand
classes...
To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 19c14abf1c4ccebfa7d07bdd6ea8462a15c0b749 |
|
17-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add support for the NEON instructions vmaxnm/vminnm.
This adds a new class for non-predicable NEON instructions and a
new DecoderNamespace for v8 NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| beb920fce6ccc89b4735f280f94cb8c227f4ef5e |
|
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix literal load with positive offset encoding
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly
This patch also makes the assembler look at the .w/.n specifier for
loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 99cb622041a0839c7dfcf0263c5102a305a0fdb5 |
|
18-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
|
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| d65dfd83421f4d26e6dc20476718d7d9b6ba3f3b |
|
27-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: permit full range of valid ADR immediates.
This fixes an issue where trying to assemlbe valid ADR instructions would cause
LLVM to hit a failed assertion.
Patch by Keith Walker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 93c7c449a1351542fa5a275587187154dbedb8e0 |
|
22-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Fix the handling of edge cases in ARM shifted operands.
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 86a1c32e67b23c5e9e42dff9eb86e99ba15bb42f |
|
15-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| aaf217953bef3b2cc0e0f26bf474616cc20cf7f0 |
|
24-Aug-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix undefined behavior (negation of INT_MIN) in ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| df1c637ac4b6f6587c037be55cafed665c732d8f |
|
10-Aug-2012 |
Eric Christopher <echristo@apple.com> |
Remove getARMRegisterNumbering and replace with calls into
the register info for getEncodingValue. This builds on the
small patch of yesterday to set HWEncoding in the register
file.
One (deprecated) use was turned into a hard number to avoid
needing register info in the old JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 1fb27eccf5b7eabde9678d84411eb1df8a693683 |
|
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 918f55fe239f00651e396be841f2b3b6e242f98d |
|
15-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.
Patch by Tom Stellard <Tom.Stellard@amd.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 94b590f8faf4dbba406f263e6a839882b0c68a94 |
|
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.
rdar://10550147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| b56e4115ed33dae56108ed4ce88ee3a0e0392bfc |
|
25-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| cb0809b82b126e79b99755ae4fc3d9733faea038 |
|
30-Mar-2012 |
James Molloy <james.molloy@arm.com> |
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
Patch by Tim Northover!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 7b25ecf6adbf3c4709c48033acfeb6ebbb4452ab |
|
27-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM BL/BLX instruction fixups should use relocations.
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
|
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 42e6bd38e02e2e1c2cc50d2f12036c38c4ea3ab0 |
|
27-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Keep source information, if available, around for ARM Fixups.
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 4f8dc7b17accf4f2ec953b80b2cc79786207492e |
|
24-Jan-2012 |
Owen Anderson <resistor@mac.com> |
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 0b4c6738868e11ba06047a406f79489cb1db8c5a |
|
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 2bd335470f8939782f3df7f6180282d3825d4f09 |
|
10-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
Remove unnecessary default cases in switches that cover all enum values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 2f196747f15240691bd4e622f7995edfedf90f61 |
|
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| eeaf1c1636c664c707fd9ecc96916fd20ddf137a |
|
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 204aa64f30911f28c11e05ba2acf475d25c45fa0 |
|
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoder method needs the physical register number, not the enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 12c7e90d369b4605aac0ddbd252231beacb2aabb |
|
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb2 shifted register operands with RRX shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 885f1a0c048e07fca56bc256702c58eae50ae71f |
|
13-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Zap some junk from the ARM instruction descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| fd92d2e106acfbf13ed29b5d15f3a690cd8699b2 |
|
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative LDRSHW with an immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 08fef885eb39339a47e3be7f0842b1db33683003 |
|
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| a77295db19527503d6b290e4f34f273d0a789365 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 721cb1fde07423fd1905338d443172a8028ad634 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding for tBcc with immediate offset operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 559c277aa9242dd5b32d2f2ccc353d938f886ee9 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 21df36c57afc588c8073a070a47e3ba45fa87270 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| a7710edd98d71a81c43f8e3889cf0c790885d1b8 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 391ac65377f2ad5e48a796e75120959e22430605 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 10096dbdef22a10a6a4444437c935ab428545525 |
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30-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Clean up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 0da10cf44d0f22111dae728bb535ade2283d976b |
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29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| f1eab597b2316c6cfcabfcee98895fedb2071722 |
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27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| d7568e1c355f5e364eddafc15c6d5553559f32a5 |
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27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct encoding of BL with immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 96425c846494c1c20a4c931f4783571295ab170c |
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26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 70939ee1415722d7f39f13faf9b3644b96007996 |
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17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 3dac0bec7e7874ffb378385b6160bd2117184ca9 |
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11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 6d74631062e4464326eb5c680a4d62d340fa42eb |
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08-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 16578b50889329eb62774148091ba0f38b681a09 |
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05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
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04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 354712c5a506449676e6fcac6b623af4092e7100 |
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28-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 5de728cfe1a922ac9b13546dca94526b2fa693b6 |
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28-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| fb8989e64024547e4ad5ab6fe4d94fe146a7899f |
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27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| 85bfd3b023d4d70936006eadd86588b03e5f40c0 |
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26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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| be74029f44c32efc09274a16cbff588ad10dc5ea |
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23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARM mc routines into MCTargetDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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