| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
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18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/MSP430/MSP430InstrFormats.td
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| fddb7667ca4d8fe83f96b388295849281ddaa5b4 |
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05-Apr-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/MSP430/MSP430InstrFormats.td
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| 05011a8aba3a4e8f011ac92990423947f8cbb15b |
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15-Jan-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide instruction sizes & encoding. No opcodes yet (but not needed so far).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/MSP430/MSP430InstrFormats.td
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| 3af4a0b4cb5439d09332a04ee98a3be86a3e3e1e |
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15-Jan-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add instruction formats & support stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/MSP430/MSP430InstrFormats.td
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| f2c3e179ecc2a6ebc259382828a5e5dc5a61d2f8 |
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03-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Dummy MSP430 backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/MSP430/MSP430InstrFormats.td
|