| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| bb47fd04c9b1616c0371eb2c488c5f0f665c25f8 |
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12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| 6ff1ef9931b50763a40e9ae8696cfab9e25cf4de |
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30-Oct-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.
It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().
Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| c8a1fa77a73e7c885035421712ceba951f9024cb |
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27-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 |
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24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp
This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).
There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.
compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| 2fd3e67dc6438cee5e32e0d7d7d42891df7edd96 |
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28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added load/store intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| da0860f78e6e43aca3333a7815b2f9bc0f8dfac0 |
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13-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| f283512d72757aac5bedcb270f9199194e6a12c0 |
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14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename functions and variables to start with proper case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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| 1d905668ddaab127eb6f9668b6314afbef7bee20 |
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14-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Add header file MipsISelDAGToDAG.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
|