| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| fe16848601bdde6e3a5e0860199169dd171222a4 |
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19-Oct-2013 |
Nadav Rotem <nrotem@apple.com> |
Mark some command line flags as hidden
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 3e84ad28d4d3ceee25771b1e30315c20b7608c39 |
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22-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 0ff1190888f5b24f64a196392c452800447186d8 |
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15-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Replace getValueType().getSimpleVT() with getSimpleValueType().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 3a8ee4ffd783bd0cf2d83089edb43ec546b49d0d |
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22-Jul-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Use approximate FP ops when unsafe-fp-math is used, and append
.ftz to instructions if the nvptx-f32ftz attribute is set to "true"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| be08c60533d27f2714a4a88ba91125bcede32a1e |
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01-Jul-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 9bc8feeb4fd15883949900194c93fd1704c404b4 |
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01-Jul-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| ef0ccc93203e99077632cec7a0a15b8e1b704aee |
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28-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Clean up comparison/select/convert patterns and factor out PTX instructions from their patterns
Test case is no breakage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 1c07dae9fcd04469779edf7b86fef37fecc9466c |
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28-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 7c32502a7f81dfaddb79c9c8e5b1acc759e19af9 |
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10-Jun-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| d5c52f1d760cd2f6f347733a02bf666fc1d50662 |
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30-May-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Fix case where a sext load of an i1 type may produce an
ld.u1 instead of an ld.u8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
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25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| b9c26dcb2438266567ce94570bf294d00d10cc87 |
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21-May-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 |
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20-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 3639ce2575660a0e6938d2e84e8bd9a738fd7051 |
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30-Mar-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Run clang-format on all NVPTX sources.
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 7eacad03efda36e09ebd96e95d7891cadaaa9087 |
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12-Feb-2013 |
Justin Holewinski <jholewinski@nvidia.com> |
[NVPTX] Disable vector registers
Vectors were being manually scalarized by the backend. Instead,
let the target-independent code do all of the work. The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
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02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
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03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
|
| af878315192a9fa5b534364e327c24aeb8d73b5a |
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05-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
NVPTX: Initialize the UseF32FTZ flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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| 49683f3c961379fbc088871a5d6304950f1f1cbc |
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04-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.
The new target machines are:
nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX
The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
|