| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 50019d8f7e1af96b85098ba501acbb9845682e4a |
|
22-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Correct the pre-increment load latencies in the PPC A2 itinerary
Pre-increment loads are microcoded on the A2, and the address increment occurs
only after the load completes. As a result, the latency of the GPR address
update is an additional 2 cycles on top of the load latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| d24ba9ff6e7ffc64c0597171b1980cc4e9556eb0 |
|
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Greatly simplify the PPC A2 scheduling itinerary
As Andy pointed out to me a long time ago, there are no structural hazards in
the later pipeline stages of the A2, and so modeling them is useless. Also,
modeling the top pre-dispatch stages is deceiving because, when multiple
hardware threads are active, those resources are shared among the threads. The
bypass definitions were mostly wrong, and so those have been removed. The
resulting itinerary is much simpler, and more accurate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| de80951ae9bb86ab6b4183f0d482d426c02ab708 |
|
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Correct the PPC A2 misprediction penalty
The manual states that there is a minimum of 13 cycles from when the
mispredicted branch is issued to when the correct branch target is
issued.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 575e9229bd2053e6887ec4253f29b570d90d80c9 |
|
05-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a SchedMachineModel for the PPC A2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 8dc440a46a5153a1640a3050480cceca9b8af05d |
|
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split several PPC instruction classes.
Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
- Clearly separate load/store-with-update instructions from regular loads and stores.
- Split IntRotateD -> IntRotateD and IntRotateDI
- Split out fsub and fadd from FPGeneral -> FPAddSub
- Update existing itineraries
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 79248299f6ca12926088a4adebbbbe00b05a2642 |
|
13-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add another missing 64-bit itinerary definition for the PPC A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 04dccea2c352e752e2823fac51051dd4ae0d8e67 |
|
12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add some missing 64-bit itinerary definitions for the PPC A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 16803097fbefa313fdadc3adede659bd0e52cec1 |
|
12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 77a9e0f318a5454ee86bbf64858860fb6548d7d2 |
|
04-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix a copy-and-paste duplication error in the PPC 440 and A2 schedules (no functionality change).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157912 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| b66e943d4cfa4a48ad028898d232754ecd3202c1 |
|
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix some 80-col. violations I introduced with the A2 PPC64 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 730acfb413849f05e9735145d6634c4429467ab7 |
|
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add LdStSTD* itin. for the PPC64 A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|
| 4d989ac93ce608057fb6b13a4068264ab037ecd5 |
|
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add instruction itinerary for the PPC64 A2 core.
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleA2.td
|