| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 19a99df130f5747da950faf4ca5170d71f05594c |
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15-Nov-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Fix scheduling of instructions that use the LDS output queue
The LDS output queue is accessed via the OQAP register. The OQAP
register cannot be live across clauses, so if value is written to the
output queue, it must be retrieved before the end of the clause.
With the machine scheduler, we cannot statisfy this constraint, because
it lacks proper alias analysis and it will mark some LDS accesses as
having a chain dependency on vertex fetches. Since vertex fetches
require a new clauses, the dependency may end up spiltting OQAP uses and
defs so the end up in different clauses. See the lds-output-queue.ll
test for a more detailed explanation.
To work around this issue, we now combine the LDS read and the OQAP
copy into one instruction and expand it after register allocation.
This patch also adds some checks to the EmitClauseMarker pass, so that
it doesn't end a clause with a value still in the output queue and
removes AR.X and OQAP handling from the scheduler (AR.X uses and defs
were already being expanded post-RA, so the scheduler will never see
them).
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| ac779b8494ad3d2f2ea40cb566552c0fb1b17363 |
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12-Sep-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Don't use trans slot for instructions that read LDS source registers
This fixes some regressions in the piglit local memory store tests
introduced by recent commits which made the scheduler aware of the trans
slot.
It's not possible to test this using lit, because there is no way to
determine from the assembly dumps whether or not an instruction is in
the trans slot.
Even if this were possible, the test would be highly sensitive to
changes in the scheduler and might generate confusing false negatives.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| bb25a01d232257b134f1f6a5810116cbb04b95b1 |
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04-Sep-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 6b3f6a744a6d16c5d62dc3477186035e8a74a8e9 |
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31-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 98ce62780ea7185ba710868bf83c8077e8d7f6d6 |
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31-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 8f9fbd67c3f803f7397843fdf4b2a7b7ca10189e |
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29-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Support schedule and packetization of trans-only inst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| e3d4cbc7d25061441adafa47450a31571c87bf85 |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| cedcfee405a22b245e869abe8609f094df34085a |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for GROUP_BARRIER instruction
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 843c6c2d0e83bcd52a215d768bacaa7b5ffe16a4 |
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08-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Use a refined heuristic to choose when switching clause
This is using a hint from AMD APP OpenCL Programming Guide with
empirically tweaked parameters.
I used Unigine Heaven 3.0 to determine best parameters on my system
(i7 2600/Radeon 6950/Kernel 3.9.4) the benchmark :
it went from 38.8 average fps to 39.6, which is ~3% gain.
(Lightmark 2008.2 gain is much more marginal: from 537 to 539)
There is no lit test provided as the parameter were determined
empirically and it it would be nearly impossiblet to find a test
program that check for optimal behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 3ff0abfaabc2c7f604d490be587b9c27e7c91ac0 |
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07-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Rework subtarget info and remove AMDILDevice classes
This should simplify the subtarget definitions and make it easier to
add new ones.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 5f035d048e4ae04a30075e75d919fe023452ab0b |
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06-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Remove leftover code in R600MachineScheduler.cpp
Spotted by Benjamin Kramer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
|
| 512119770e9c32eb0b9e6196ce51917fb2e30d9f |
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05-Jun-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Schedule copy from phys register at beginning of block
It allows regalloc pass to remove them by trivially assigning associated reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| ad7ecc65b1b1d6466ff035168c86f208a91aa1b4 |
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05-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Make sure to schedule AR register uses and defs in the same clause
Reviewed-by: vljn at ovi.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 5c35290fa35ae234fed02496404cb0fc37e1c8a5 |
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23-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 76fc2d077f955174c14e658bf179620ef49dd792 |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Use bottom up scheduling algorithm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 21ca0b3ea45549f6f16c5b2d0e96ad49256baa1d |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Use depth first scheduling algorithm
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| f63f85affa943d3257f91640b15d4e0d1e4a22d1 |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Replace big texture opcode switch in scheduler by usesTC/usesVC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 4ed9917147b1d1f2616f7c941bbe6999b979f510 |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Relax some vector constraints on Dot4.
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| dcfcf1d1ffe72d9c25564a2b8b53763a28648e97 |
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17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Factorize Fetch size limit inside AMDGPUSubTarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| dae2a20a56b28b4685249982a80a0043b7673e09 |
|
03-Apr-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Factorize maximum alu per clause in a single location
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 3ab0ba3cd8a499ebcc7eda3d7585c5ab4e7f0711 |
|
14-Mar-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Factorize code handling Const Read Port limitation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 3f179b59e53a8a6d5dfb509857d972461027b809 |
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11-Mar-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
R600MachineScheduler.cpp: Fix use cases of dbgs(). Don't include <iostream> here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176797 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
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| 62f38ca141f87ff3ed9334fbe6a5e1c45d40ca86 |
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05-Mar-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: initial scheduler code
This is a skeleton for a pre-RA MachineInstr scheduler strategy. Currently
it only tries to expose more parallelism for ALU instructions (this also
makes the distribution of GPR channels more uniform and increases the
chances of ALU instructions to be packed together in a single VLIW group).
Also it tries to reduce clause switching by grouping instruction of the
same kind (ALU/FETCH/CF) together.
Vincent Lejeune:
- Support for VLIW4 Slot assignement
- Recomputation of ScheduleDAG to get more parallelism opportunities
Tom Stellard:
- Fix assertion failure when trying to determine an instruction's slot
based on its destination register's class
- Fix some compiler warnings
Vincent Lejeune: [v2]
- Remove recomputation of ScheduleDAG (will be provided in a later patch)
- Improve estimation of an ALU clause size so that heuristic does not emit cf
instructions at the wrong position.
- Make schedule heuristic smarter using SUnit Depth
- Take constant read limitations into account
Vincent Lejeune: [v3]
- Fix some uninitialized values in ConstPair
- Add asserts to ensure an ALU slot is always populated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600MachineScheduler.cpp
|