| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| bc2160f7c90efffdd62587f1c978ba68b809ef35 |
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04-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Stop leaking register infos in the disassemblers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 49a6a8d8f2994249c81b7914b07015714748a55c |
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24-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the Copied parameter from MemoryObject::readBytes.
There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.
Defines away PR16132.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 1114b0ec15aaa22dfc0ce582820cea556600d103 |
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05-May-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Remove '-' from back branch asm syntax.
Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 6ffbf6ea8fe7fbe2166b07a88004baac163aa3c5 |
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04-May-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Make use of the target independent global address offset folding.
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| c6ff29713d69b4a41c225cbde9c82e4a350dbfac |
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04-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] The RRegs register class is a superset of GRRegs.
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 8dc741e400213ea8183e09626f0d1f45f14e044f |
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17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 763c858edeb76173ee4ef5ab9bf7d750db5d8c4f |
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17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 970a479c02a418726950580e13136acd2a2dc13f |
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27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| c47bd9899b639c3384268f871009259c2a94fba4 |
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25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l4r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 1f375e5bc78647f9b29564eafdc907250ccd91ed |
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25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Use the correct format in the STW / SETPSC instruction names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 3b6a5eefe0ab2199bc69094b390b736ae332b905 |
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25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l5r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b |
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23-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l6r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 9b709f8b3f3fa6e9bfb5007b70e096f6192f3ef8 |
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21-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encoding / disassembly support for ru6 / lru6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| b853c415c663c752c669cb191cea95542c1d21f6 |
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20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| c78ec6b6bc05572aed6af1eee4349d76a68ded18 |
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20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l3r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| a68c64fbb2f1bee7f9313f3ee19c35677563f974 |
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20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembler support for 2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 62b8786d12ceacafd665d4a1fbb6e90af0ec368c |
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20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| c47793c62c434bd27fee1d243c2081a34d4f3817 |
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17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 6e43b7f6b20b39b041cf24d732ddb802bbd6471a |
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17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Fix parameter name in prototypes in XCoreDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 35150cbf4166ae8d69032d355f1e8d83b4a6eb3c |
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17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 1ffe48a84b398e8cebbdc7a47bedb57e1e67e63f |
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17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for 2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| b4d40a04f0639fdec8329a8708565411fa53b5bc |
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17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Update comments to match recommended doxygen style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 54d6266e9baa8c2796c4a95c35897b5c67d8d910 |
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16-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings and disassembly for 1r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 881e3cca66c64a57ff431a4f6d1136dd6017c137 |
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16-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add XCore disassembler.
Currently there is no instruction encoding info and
XCoreDisassembler::getInstruction() always returns Fail. I intend to add
instruction encodings and tests in follow on commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|