36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/ARM/arm-ldrd.s
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2f184eaf89bb155b423603fa827976b6d2fa5df4 |
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30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Use FileCheck instead of grep for ARM LDRD negative tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-ldrd.s
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9724873c317d2b170cfea87cdf2a402fcd7c6c7d |
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30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-ldrd.s
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6206a132a76d407fd276de17147d8c9c2c9e9e9d |
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30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Assembler: Add more negative tests for ARM LDRD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-ldrd.s
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cca114611945332852094fcadfaa4ffbd012bfb3 |
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27-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-ldrd.s
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