| 0f156af8312a0f3ce88e5c006bf2a52691039ceb |
|
30-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| ca3cd419a52c1dedee133d79772ef97f30e5d20b |
|
11-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 2dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31 |
|
05-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 71d3d67508176091575714dddf008b77db4089c9 |
|
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM update tests for CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 19b9d6912ab4d61666d5eed0a9c7d407d564ce1d |
|
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 36711e4a3c0b53000ea594233bd619dbf252558c |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for load/store exclusive instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 8409f047312da0318af2a2fce162810ca3a95da3 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for SBC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| f790193aec11747bb35206d2c79e0c5ffbc6dc7f |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 86fdff0fa79b2c00cb68a2961cca0466eb50d666 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| a4c34ab54485f64d3b962a499526825a7a0d4bbc |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encodings tests for saturating arithmetic insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 88d1bc832ca5b458c8460929227be8eae6c6bdc3 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add parsing/encoding tests for ARM ORR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| a67851445902d1fc01fa2a37a3dfc347af949f84 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Consolidate ARM NOP encoding test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| b29b4dd988c50d5c4a15cd196e7910bf46f30b83 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 80d01dd3d19a84621324ac444c6749602df7a513 |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 2317fe1584e02582c616c1c4d15954999ff5525a |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Move mr[r]c[2] ARM tests and tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 70d8fcfaa04eb20541b006a8fb97cbc1d3033cc4 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some testcases for ARM MLA/MLS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| c8ae39e746a20dc326def0ccfc052df3e21f16d3 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| e540c7422ca13c950f0e8f6f93af7225bb7742a9 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 1134be2428f0f26314ae25020f0081b860a0084d |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable some tests we now handle correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 3b14a5c5469176effb921d91d4494f0aa2919fd0 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 791feea10071223886e2fe2bfa0e1f4cb2c0ce74 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM ISB assembly parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 9dec507ecb212a7c94659e9b5a9da66cb4b39ea3 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 6a86feafa8c26ffd4b9edb3a3eab946724842051 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove duplicate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 032434d622b6cd030a60bb9045a520c93b0d7d68 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| d986bc66bc56251c2b7d5b9a89df14c4760568fc |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle ARM assembly tests a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| fbd01783a67dd2bedd8197308ef00d4ad767fcd3 |
|
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for ldmfd/stmfd mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 895c1e2deea3e6118b159c26b3f86d40a37e8501 |
|
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 56926a39619bd644c83c4128f0b55189e52707d7 |
|
25-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR9762
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 505f3cd2965e65b6b7ad023eaba0e3dc89b67409 |
|
24-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 0082830cb26248178fe5cc9bbdbd00881556c33d |
|
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 584bf7bb03e4cf1475b26851edcc1ddb66b85028 |
|
18-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| a2b6e4151b75248f9dbf8067186cba673520f8f4 |
|
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 706d946cfe44fa93f482c3a56ed42d52ca81b257 |
|
07-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing dmb/dsb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 1b10d5be40313b4e246e85cf375dfa3452ab306b |
|
26-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 030160073d8ec7d5fc1d928d9c8b6173d3a5e0cc |
|
21-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 1115c472038b19dfcc3ff44b8bf6711ebcfc3dc4 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add testcases for clz encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| e47f3751d7770916f250a00a84316d412e959c00 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding and parsing of clrex instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| b32f7a5f4bc678c052db40cbb4ac8617c134aa24 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 3abd75bf1dc96ee0cd7e8c1b8331e27672437b8b |
|
19-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| e7255a80e308c7f67d25b0b247ed791a99ea3a4e |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix MRS encoding for arm and thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 892fc6d7b64364b230261daa967518a71748c01b |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of t2ISB by using the right class and also parse it correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| fdcee77887372dbf6589d47cc33094965b679f24 |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| a461d4222877f43588da38c466145f38dd74e229 |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing and encoding ARM's official syntax for the BFI instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 352e148cbe6498a6dd31b7fc71df7cd23c4b4d10 |
|
11-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the
carry setting flag from the mnemonic.
Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 53ef11884ff273715f1924ea13853ec18510dae1 |
|
15-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes. These come from my test generator and are just
the ones that MC currently assembles correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 193c3acbe5cdb60767d114016970e898c7502d7a |
|
09-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Add support for parsing ARM arithmetic instructions that update or don't update
the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| af2b573614c7d853879ff24eb9a86d1c36acc198 |
|
21-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for ARM "trap" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 50d0f5894448aff6eb02ad63da55ecf26b54aeb8 |
|
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for parsing the writeback ("!") token.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| a295eb34a5c8bffa66ffd46b6f9b8e960930eae3 |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Test encodings for LDM and STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 5df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0ad |
|
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 833c93c7958dbbd9d648f331091fbfbeabf342e6 |
|
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark ARM subtarget features that are available for the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 14b93851cc7611ae6c2000f1c162592ead954420 |
|
29-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add simple support for addrmode5 operands, allowing
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 94074a5e4dc8c8a4338a08a93f9d2d03e1bf0b00 |
|
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
most simple arm instructions match correctly now,
it looks like we're not handling [] operands though
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 4e692ab5eeb6cf49dbb9ec9ade21cd91b081ba10 |
|
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix the asmmatcher generator to handle targets with no RegisterPrefix
(like ARM) correctly. With this change, we can now match "bx lr"
because we recognize lr as a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|
| 9ab044f20b85597cdaed6849dfc2b55af023906a |
|
02-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move ARM MC tests up one level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115414 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm_instructions.s
|