| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 16ad92ad3cd0cbbaa4d0524d9f201dd5dbefa15a |
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11-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 242c9f4615feeee2fbdd1f29cd9a8e8ffd43c075 |
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31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add fstmx and fldmx instructions for assembly
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.
Patch by Amaury de la Vieuville.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| fae96f17b4b022fccd94a143698112a17d8ddf05 |
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10-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 270e3625b23174688aa5b6f1e1d0cd42086541de |
|
09-Jul-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r159938 (and r159945) to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 2e7e34ba5485320a84ca69c83d242e24433f7acd |
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09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 181b14797518e714e1b6112db849ca53192b8f23 |
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20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM some VFP tblgen'erated two-operand aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| bfb3c5a50c0c01073658ec9d3504532c6eeb2115 |
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20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 9426ac7b575de9e1297a01f27307d858343ac4ed |
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16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM vmrs system registers mvfr0 and mvfr1 handling.
rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| b84ad4aa7dacfba5337520740d47770f2200201c |
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15-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM case-insensitive checking for APSR_nzcv.
rdar://11056591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 8a6bcc3722729803a16b5885de1ff85a3752e6a0 |
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15-Mar-2012 |
Kristof Beyls <kristof.beyls@arm.com> |
Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 51222d1551383dd7b95ba356b1a5ed89df69e789 |
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20-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 4050bc4cab61f8d3c7583a9b60f17c7da47bbf69 |
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22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| af33a0cfe092afd327e1b8b05c655d9eab689eed |
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22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP optional data type on VMOV GPR<-->SPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| a68e90c36e6a53fb1889b608f44d6244a36b3e97 |
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15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
Yet more of rdar://10435076.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| bfb0a1717bb140c418e070042e852f925e92de01 |
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15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| ffc658b056b7cc0b3f6a2626694b6a4216ed728d |
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15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| c7352f8ca0fc716c38cb3d81e63e943d47d578b3 |
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12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM optional size suffix for VLDR/VSTR syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| ce485e7f70faed6d19daafff91bb20509403d432 |
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11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM allow Q registers in vldm/vstm register lists.
rdar://9672822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 9d39036f62674606565217a10db28171b9594bc7 |
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04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 68259145d9ac1f8d4e2cc9fc73626254fcc5cf08 |
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04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing/encoding for VCMP/VCMPE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 5cd5ac6ad455880395e34ac647f1e962a83763a0 |
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03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMRS/FMSTAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 694e0ffb8aa3a8651003e448135aba0e663782bd |
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30-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add missing encoding information for some of the GPR<->FP register moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 0da10cf44d0f22111dae728bb535ade2283d976b |
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29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| b9db0c50d84b06b4b567c29375b7db92b5dab077 |
|
10-Feb-2011 |
Jim Grosbach <grosbach@apple.com> |
Do AsmMatcher operand classification per-opcode.
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 106df6da366c0abc6a3937767fe008d02cacef4c |
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26-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add encoding testcases for ARM vcvtr variations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 6cd0b17ba7f7efae41966c4a36ee725523d38575 |
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19-Jan-2011 |
Owen Anderson <resistor@mac.com> |
When matching asm operands, always try to match the most restricted type first.
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous. This
is tricky to resolve since neither is a subset of the other.
XFAIL the test for now. The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 61505907f54d4e7df2f9d90b1ed3a4caa0469d26 |
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18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Create two new generic classes to represent the following VMRS/VMSR variations:
vmrs reg, fpexc
vmrs reg, fpsid
vmsr fpexc, reg
vmsr fpsid, reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 0f6307561359fac4425a0b9e512931cf96c1ec5b |
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17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 2f46f1f59c17040f7a2c970342f2f1dcc9b78319 |
|
04-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 92b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4 |
|
03-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
|
| 5df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0ad |
|
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 933b314c761f3338ebc59aa089983681274054bd |
|
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Use ARM-style comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 833c93c7958dbbd9d648f331091fbfbeabf342e6 |
|
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark ARM subtarget features that are available for the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
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| 52925b60f1cd4cf810524ca05b00a207a926ab9f |
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30-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/simple-fp-encoding.s
|