| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/test/MC/X86/intel-syntax.s
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/X86/intel-syntax.s
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| d7f5fac1117613ff6dd0e49308d2954ac10b4f1f |
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27-Sep-2013 |
Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> |
Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 7cde9d0286a8976feebb20e61612fb999527f630 |
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27-Aug-2013 |
David Majnemer <david.majnemer@gmail.com> |
[ms-inline asm] Support offsets after segment registers
Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20'
Reviewers: craig.topper, rnk
Reviewed By: rnk
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 6ee1464ba599f1afbed502fa1b3ac18c8577fd97 |
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26-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 19b30d56b224ab3507f7a93743eac2b01c5861dd |
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13-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Make the cmov aliases work with intel syntax too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| a70d02ff2841d535875fe80bd3d3c25ba90613da |
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10-May-2013 |
Chad Rosier <mcrosier@apple.com> |
[x86AsmParser] It's valid to stop parsing an operand at an immediate.
rdar://13854369 and PR15944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| f74d82d8e49ec54953c106a89e0a5951466d4e6b |
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23-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
Add test case for PR15779, which has previously been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 3f1f9c37986953250cbda7a7bfb7123571449be7 |
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19-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Apply the condition code mnemonic aliases to both the Intel and
AT&T dialect. Test case for r179804 as well.
rdar://13674398 and PR13340.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| d58f773b96fdb5539d9da2192b8cf2ff6112239f |
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17-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for the minus unary operator. Previously, we were
unable to handle cases such as __asm mov eax, 8*-8.
This patch also attempts to simplify the state machine. Further, the error
reporting has been improved. Test cases included, but more will be added to
the clang side shortly.
rdar://13668445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| e112453fc39b97147ea3f23bf0b1973cd9f739b1 |
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05-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for numeric displacement expressions in bracketed
memory operands.
Essentially, this layers an infix calculator on top of the parsing state
machine. The scale on the index register is still expected to be an immediate
__asm mov eax, [eax + ebx*4]
and will not work with more complex expressions. For example,
__asm mov eax, [eax + ebx*(2*2)]
The plus and minus binary operators assume the numeric value of a register is
zero so as to not change the displacement. Register operands should never
be an operand for a multiply or divide operation; the scale*indexreg
expression is always replaced with a zero on the operand stack to prevent
such a case.
rdar://13521380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| dd2e8950222ab74157b1c083ffa77b0fbaf1d210 |
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14-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Extend support for parsing Intel bracketed memory operands that
have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 75dc33a60b65bbbf2253b0b916df1d36a4da4237 |
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18-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| a28101e61aa3aeed5baf3d5b91d0f8bcb4e9e12a |
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27-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| f2d213745e07e884c1616f2f3d0b78f9e918e5db |
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23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify parsing of memory operand's displacement experssion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 3e08131185d5b3245065eb027900aed56b607970 |
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23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 7c64fe651ad4581ac66b6407116144442a8a7f03 |
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23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 1aea430b8834f7bed3a14eda5027eac2133d6496 |
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20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify register parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| b8ba13f0096b560ee618512019ca86969a9fa772 |
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18-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Process instructions after match to select alternative encoding which may be more desirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 2f8af1d643cde711b292117e50b30452877432ef |
|
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Fix parser match class to check memory operand size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 6220fea2a877e5cff559ed38e98c59a076ea9825 |
|
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
|
| 9a3d293cf3f72b3c0ed5d4474fc5d4d12fd36be2 |
|
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 40bced0306e953c3d0fec19db4c4770b0e3c787e |
|
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Ignore mnemonic aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
|
| d37ad247cc04c2a436e537767ac1aec709901594 |
|
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify memory operand parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 4a5c0fd70e7a2001b682c8972dab6b0127313c8f |
|
13-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Add new test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
|