| 05113fd2662eeb0d17fd1074001b7405eeeca43c |
|
29-Aug-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Create a register class for the M0 register
The Common Subexpression Elimination pass will not operate on
instructions with physical register defs, so we end up with
several redundant copies to M0 when using interpolation.
Adding a register class that only contains the M0 register allows
use to use a virtual register to represent M0, and makes it possible
for the Common Subexpression Elimination pass to remove the extra
copies.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 73a2c4b9db638cad83e412097ed3433649aab47b |
|
28-Aug-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Mark M0 as a def when lowering interpolation instructions
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 70f9dbe298043f0e3914e6956ddcc0a098f7eca3 |
|
28-Aug-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon/llvm: Handle TGSI KIL opcode for SI.
Fixes piglit fp-kil and glBitmap() with radeonsi.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 3aaa209293a281e103ef71e3578fad042972e092 |
|
26-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 40c41fe890e53d99afb4e2c3fbf10043081edd9e |
|
25-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Add live-in registers during DAG lowering
Psuedo instructions emulating live-in registers have been removed
and their corresponding intrinsics are now being lowered during DAG
lowering.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| a35eea786823f0130b925cb25486d7d162f2d68c |
|
02-Aug-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Add support for fneg on SI
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 27ae41c83dafcec09e870b3cf08b060064dbb122 |
|
30-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLowering
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163 |
|
26-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Fix VOPC and V_CNDMASK encoding
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| fd1f19a191c648e7c6fdaac3167e900e4fed4a6d |
|
25-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Add SI DAG optimizations for setcc, select_cc
These are needed for correctly lowering branch instructions in some
cases.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 50ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48 |
|
25-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Add special nodes for SALU operations on VCC
The VCC register is tricky because the SALU views it as 64-bit, but the
VALU views it as 1-bit. In order to deal with this we've added some
special bitcast and binary operations to help convert from the 64-bit
SALU view to the 1-bit VALU view and vice versa.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| c424975572af2edd46863e5bb9fe3c51c96b4f9b |
|
25-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Add i1 registers for SI.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 4cab682184640242d1e6f034f2b6bd7c4378c162 |
|
19-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Add custom lowering for SELECT_CC nodes on SI
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| d36455ba2c3febe5da6fc6f53e4acd98f771532a |
|
25-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Implement getSetCCResultType for SI
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218 |
|
18-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Custom lower BR_CC for SI
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 76b44034b9b234d3db4012342f0fae677d4f10f6 |
|
08-Jul-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Rename namespace from AMDIL to AMDGPU
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 440ab9ea02690008b4d8da11494fd1e9cd86e57e |
|
15-Jun-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Remove deadcode from AMDILISelLowering.cpp
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 83169900fb96f1a51d8292e66c203c64a82e204d |
|
29-May-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Update and fix some comments
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 89ece086bcd2186ab53cb6a69d53005893cab0ea |
|
29-May-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeonsi: Remove use.sgpr* intrinsics, use load instructions instead
We now model loading uses sgpr values with LLVM IR load instructions that
use the USER_SGPR address space.
The definition of the sgpr parameter to the use_sgpr() helper function
in radeonsi_shader.c has changed so that you can pass raw sgpr values
rather than having to divide the sgpr value you want to use by the dword
width of the type you want to load.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 467f51613eb1f2cdaa8624bbbb3d5fae2abca4f2 |
|
16-May-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeonsi: Handle TGSI CONST registers
We now emit LLVM load instructions for TGSI CONST register reads,
which are lowered in the backend to S_LOAD_DWORD* instructions.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| d784bc77405012b442ae9d68f200e9d115030b3c |
|
25-May-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Use a custom inserter to lower CLAMP
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| 17f852892346fdf3b1e9eec56b7a55c470279bc8 |
|
25-May-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Use a custom inserter to lower FABS
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| cc7a6d269170cc3668caa4f5af29228920e8d7a7 |
|
24-May-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter()
We need to return immediately after inserting instructions that require
S_WAITCNT so that the parent class' custom inserter won't try to insert
them again.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| bcfc97dbf40c256ed59c2424e0c55b845f0f2569 |
|
11-May-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: More comments and cleanups
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| fa63f976522bd4faf19249e8c9ac4d3edda498d9 |
|
09-May-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/llvm: Add some comments
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|
| a75c6163e605f35b14f26930dd9227e4f337ec9e |
|
06-Jan-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeonsi: initial WIP SI code
This commit adds initial support for acceleration
on SI chips. egltri is starting to work.
The SI/R600 llvm backend is currently included in mesa
but that may change in the future.
The plan is to write a single gallium driver and
use gallium to support X acceleration.
This commit contains patches from:
Tom Stellard <thomas.stellard@amd.com>
Michel Dänzer <michel.daenzer@amd.com>
Alex Deucher <alexander.deucher@amd.com>
Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The following commits were squashed in:
======================================================================
radeonsi: Remove unused winsys pointer
This was removed from r600g in commit:
commit 96d882939d612fcc8332f107befec470ed4359de
Author: Marek Olšák <maraeo@gmail.com>
Date: Fri Feb 17 01:49:49 2012 +0100
gallium: remove unused winsys pointers in pipe_screen and pipe_context
A winsys is already a private object of a driver.
======================================================================
radeonsi: Copy color clamping CAPs from r600
Not sure if the values of these CAPS are correct for radeonsi, but the
same changed were made to r600g in commit:
commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc
Author: Marek Olšák <maraeo@gmail.com>
Date: Mon Jan 23 03:11:17 2012 +0100
st/mesa: do vertex and fragment color clamping in shaders
For ARB_color_buffer_float. Most hardware can't do it and st/mesa is
the perfect place for a fallback.
The exceptions are:
- r500 (vertex clamp only)
- nv50 (both)
- nvc0 (both)
- softpipe (both)
We also have to take into account that r300 can do CLAMPED vertex colors only,
while r600 can do UNCLAMPED vertex colors only. The difference can be expressed
with the two new CAPs.
======================================================================
radeonsi: Remove PIPE_CAP_OUTPUT_READ
This CAP was dropped in commit:
commit 04e324008759282728a95a1394bac2c4c2a1a3f9
Author: Marek Olšák <maraeo@gmail.com>
Date: Thu Feb 23 23:44:36 2012 +0100
gallium: remove PIPE_SHADER_CAP_OUTPUT_READ
r600g is the only driver which has made use of it. The reason the CAP was
added was to fix some piglit tests when the GLSL pass lower_output_reads
didn't exist.
However, not removing output reads breaks the fallback for glClampColorARB,
which assumes outputs are not readable. The fix would be non-trivial
and my personal preference is to remove the CAP, considering that reading
outputs is uncommon and that we can now use lower_output_reads to fix
the issue that the CAP was supposed to workaround in the first place.
======================================================================
radeonsi: Add missing parameters to rws->buffer_get_tiling() call
This was changed in commit:
commit c0c979eebc076b95cc8d18a013ce2968fe6311ad
Author: Jerome Glisse <jglisse@redhat.com>
Date: Mon Jan 30 17:22:13 2012 -0500
r600g: add support for common surface allocator for tiling v13
Tiled surface have all kind of alignment constraint that needs to
be met. Instead of having all this code duplicated btw ddx and
mesa use common code in libdrm_radeon this also ensure that both
ddx and mesa compute those alignment in the same way.
v2 fix evergreen
v3 fix compressed texture and workaround cube texture issue by
disabling 2D array mode for cubemap (need to check if r7xx and
newer are also affected by the issue)
v4 fix texture array
v5 fix evergreen and newer, split surface values computation from
mipmap tree generation so that we can get them directly from the
ddx
v6 final fix to evergreen tile split value
v7 fix mipmap offset to avoid to use random value, use color view
depth view to address different layer as hardware is doing some
magic rotation depending on the layer
v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
evergreen, align bytes per pixel to a multiple of a dword
v9 fix handling of stencil on evergreen, half fix for compressed
texture
v10 fix evergreen compressed texture proper support for stencil
tile split. Fix stencil issue when array mode was clear by
the kernel, always program stencil bo. On evergreen depth
buffer bo need to be big enough to hold depth buffer + stencil
buffer as even with stencil disabled things get written there.
v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
old ddx overestimate those. Fix linear case when pitch*height < 64.
Fix r300g.
v12 Fix linear case when pitch*height < 64 for old path, adapt to
libdrm API change
v13 add libdrm check
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
======================================================================
radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY
This was removed in commit:
commit 62f44f670bb0162e89fd4786af877f8da9ff607c
Author: Marek Olšák <maraeo@gmail.com>
Date: Mon Mar 5 13:45:00 2012 +0100
Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY"
This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc.
It was decided to refactor the transfer API instead of adding workarounds
to address the performance issues.
======================================================================
radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT.
Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90.
======================================================================
radeonsi: nuke the fallback for vertex and fragment color clamping
Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853.
======================================================================
radeonsi: don't expose transform_feedback2 without kernel support
Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48.
======================================================================
radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL.
Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f.
======================================================================
radeonsi: set minimum point size to 1.0 for non-sprite non-aa points.
Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc.
======================================================================
radeonsi: rework and consolidate stencilref state setting.
Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070.
======================================================================
radeonsi: cleanup setting DB_SHADER_CONTROL.
Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b.
======================================================================
radeonsi: Get rid of register masks.
Ported from r600g commits
3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2.
======================================================================
radeonsi: get rid of r600_context_reg.
Ported from r600g commits
9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f.
======================================================================
radeonsi: Fix regression from 'Get rid of register masks'.
======================================================================
radeonsi: optimize r600_resource_va.
Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174.
======================================================================
radeonsi: remove u8,u16,u32,u64 types.
Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5.
======================================================================
radeonsi: merge r600_context with r600_pipe_context.
Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0.
======================================================================
radeonsi: Miscellaneous context cleanups.
Ported from r600g commits
e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888.
======================================================================
radeonsi: add a new simple API for state emission.
Ported from r600g commits
621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e.
======================================================================
radeonsi: Also remove sbu_flags member of struct r600_reg.
Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions,
so some code needs to be disabled for now.
======================================================================
radeonsi: Miscellaneous simplifications.
Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and
b0337b679ad4c2feae59215104cfa60b58a619d5.
======================================================================
radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION.
Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a.
======================================================================
radeonsi: Use a fake reloc to sleep for fences.
Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4.
======================================================================
radeonsi: adapt to get_query_result interface change.
Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
/external/mesa3d/src/gallium/drivers/radeon/SIISelLowering.cpp
|