| a56a732c6991f47d63f5ccbb27a45467541c43f8 |
|
08-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correct _NEW_TRANSOFORM typos.
Using the proper spelling, _NEW_TRANSFORM, makes searching work better.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 7a874d04a8410a2b778b29ba85797eaf45d96c84 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move CC VP to emit() time, since it's only needed by CC's emit().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 2836aab2031d5b6926923fbc70f867ec638301bd |
|
09-Sep-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Use ColorLogicOpEnabled instead of _LogicOpEnabled
Since GL_EXT_blend_logic_op is removed, _LogicOpEnabled and
ColorLogicOpEnabled always have the same value.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| d375df220fae47f38944c4832bcbd5f5d568884c |
|
23-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a type argument to brw_state_batch().
I want to make brw_state_dump.c handle more than just the last
statechange, so I want to keep track of what's in the batch state. By
using AUB file numbering for most of these packets, this may be
reusable for aub dumping.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| d67c08319fda7d0f2df98d60b64c8cc2f3e06c44 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move the CC VP to state streaming.
This is in a way a revert of f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f.
The tiny win that had will be overwhelmed by the win of using the gen6
dynamic state base address.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| d22e2ebe35ef9d33ec5f7a67f903f36bcd9fbc91 |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_color_buffer_float.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| f19439940c43aa9d937716c6f1ee70cc26799e08 |
|
24-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Remember to pack the constant blend color as floats into the batch
Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| aac120977d1ead319141d48d65c9bba626ec03b8 |
|
20-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Move repeat-instruction-suppression to batchbuffer core
Move the tracking of the last emitted instructions into the core
batchbuffer routines and take advantage of the shadow batch copy to
avoid extra memory allocations and copies.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 3f55683927278e57f3ef8a151d15f4cffdc060dc |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: drop state_bo references to batch_bo
As we use state relocations and we know that all the state belongs to
the same bo, we can drop the multiple references to the same bo.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| df156549e7ce284f0cf887eec1bad9aa1392ebbf |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: write cc straight to batch
As we write directly into the batch in system memory, we do not need to
write first to the stack (as was to avoid read back through the GTT)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 74713e2d293f9e796a4053a5a99ee5cb7df5c740 |
|
11-Jan-2011 |
Brian Paul <brianp@vmware.com> |
mesa: begin implementation of GL_ARB_draw_buffers_blend
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 1feee7b1b39e54c279ffdc3c27f3911c04658430 |
|
10-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.
Again, this makes it match the documentation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 7720bfffa3fd537789b5ded30ecc23afa21dc410 |
|
19-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move gen4 blend constant color to the gen4 blending file.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 4a0bc4716db7bbcbcd65c0f993704733f47d41f7 |
|
21-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Also enable CC statistics when doing OQs.
This is required by the spec, so respect that.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 7ad26b0030f6b14e6ec069eafdec6faf75e8007c |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Stream out CC unit state.
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 31.791 32.287 1.11% 6/6
after:
[ 0] gl firefox-talos-gfx 31.198 31.675 0.96% 6/6
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 8ad3fdc9678866b40f3d9faaaf7c6333d388907f |
|
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: GC the last two arguments to brw_cache_data.
Now that the binding table is streamed indirect state, they were
always NULL/0.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f |
|
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the CC VP state immediately on state change.
The cache lookup of these two little floats was .12% of total CPU time
on firefox-talos-gfx because we did it any time commonly-changed state
changed. On the other hand, updating the CC VP bo immediately whenver
CC VP state changes is a .07% overhead due to putting a driver hoook
in glEnable().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| df3c1a563f3d76b07ab82c7b230b0030452f36ff |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.
The new API makes so much more sense, I'd like to forget how the old
one worked.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache.
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| b90f7f3ad324b1e4c39e334cdeb9556c3eb808ab |
|
15-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Use current draw buffer instead of drawable visual to get alpha bits
Use the currently bound draw buffer instead of the visual from the
drawable used to create the context. This cause problems generating
mipmaps for an RGBA texture in an RGB context.
This fixes the failure in piglit's glsl-lod-bias test reported in bug #25614.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| eadd9b8e16e3b1ad35fec54f780a0f94ac43988f |
|
09-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Fix handling of drawing to MESA_FORMAT_XRGB8888
It turns out that 965 and friends cannot actually render to an xRGB
surfaces. Instead, the surface has to be RGBA with writes to alpha
disabled and the blend function modified to always use 1.0 for
destination alpha.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 8395da2e8af40367714c70afe299568272f36cc8 |
|
05-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Always pass the size argument to brw_cache_data.
This keeps the individual state files from having to export their
structures for brw_state_cache initialization.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 92e7c6a2581b5f612a84587500399bb00318c6f0 |
|
29-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix fallout from ARB_depth_clamp enablement that broke glDepthRange.
If a backwards glDepthRange was supplied (as with the old Quake no-z-clearing
hack), the hardware would have always clamped because we weren't clamping to
the min of near/far and the max of near/far. Also, we shouldn't be clamping
to near/far at all when not in depth clamp mode (this usually didn't matter
since near/far are usually the same as the 0.0, 1.0 clamping you do for
fixed-point depth).
This should fix funny depth issues in PlaneShift, and fixes piglit
depth-clamp-range
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 0310aafd9ea502e07a86b355cfca902102b9117c |
|
26-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add support for ARB_depth_clamp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 91e61f435a71436c209934a0ece165b540aba3e0 |
|
02-Mar-2009 |
Brian Paul <brianp@vmware.com> |
mesa: use Stencil._Enabled field instead of Stencil.Enabled
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| dde7cb962860e72e1bf3175069767358cc5b3f3c |
|
10-Jan-2009 |
Ian Romanick <idr@freedesktop.org> |
Track two sets of back-face stencil state
Track separate back-face stencil state for OpenGL 2.0 /
GL_ATI_separate_stencil and GL_EXT_stencil_two_side. This allows all
three to be enabled in a driver. One set of state is set via the 2.0
or ATI functions and is used when STENCIL_TEST_TWO_SIDE_EXT is
disabled. The other is set by StencilFunc and StencilOp when the
active stencil face is set to BACK. The GL_EXT_stencil_two_side spec has
more details.
http://opengl.org/registry/specs/EXT/stencil_two_side.txt
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 527e1cf172cb0a4d1f2891a351498669be1620cd |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
965: cleanups to state emission from aperture checking and state ordering.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
|
11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| ab50ddaa9173ae108833db0edb209045788efc41 |
|
07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 6a5e86b3444b4228c5232bf5a297159e66f02077 |
|
16-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Rename depth_mask in CC key to depth_write, since it's a boolean enable.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 93ec89e565cbdc9dab010d1a1d259f2348ac7459 |
|
16-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Fix the type of alpha_ref in CC key, fixing ppracer rendering.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 8abffada70fcd62e3c2dcbcdc6d00d258805326b |
|
03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert relocations to not be cleared out on buffer submit.
We have two consumers of relocations. One is static state buffers, which
want the same relocation every time. The other is the batchbuffer, which gets
thrown out immediately after submit. This lets us reduce repeated computation
for static state buffers, and clean up the code by moving relocations nearer
to where the state buffer is computed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| b35811e1b38e8fd454f369aefc0b3b3c50ecb8bc |
|
02-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert CC unit to use a cache key instead of brw_cache_data.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 9136e1f2c80ce891fb6270341a4316f219c89d49 |
|
21-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Fix and enable separate stencil.
Note that this does not enable GL_EXT_stencil_two_side, because Mesa's computed
_TestTwoSide ends up respecting only STENCIL_TEST_TWO_SIDE_EXT (defaults to
GL_FALSE), even if the application uses only GL 2.0 / ATI entrypoints.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 121533defb48abddbf796aed62c1282cfa5234f9 |
|
03-May-2007 |
Brian <brian@yutani.localnet.net> |
add some #includes to silence warnings
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_cc.c
|