| 849a3d243d8a0d951202515c06d9b17daf59d2f2 |
|
19-Sep-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Don't spill "smeared" registers.
Fixes an assertion failure when compiling certain shaders that need both
pull constants and register spilling:
brw_eu_emit.c:204: validate_reg: Assertion `execsize >= width' failed.
NOTE: This is a candidate for the 8.0 release branch.
Signed-off-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit ab5ce2789fe9e5f2789ee22fdb02bcfed42a7125)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| d72ff03e699e78381049e29d89163519e6730dd4 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add INTEL_DEBUG=perf for failure to compile 16-wide shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| a40c1f95229915214be061fbbf9a02e5225fbf01 |
|
07-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Make register spill/unspill only do the regs for that instruction.
Previously, if we were spilling the result of a texture call, we would store
all 4 regs, then for each use of one of those regs as the source of an
instruction, we would unspill all 4 regs even though only one was needed.
In both lightsmark and l4d2 with my current graphics config, the shaders that
produce spilling do so on split GRFs, so this doesn't help them out. However,
in a capture of the l4d2 shaders with a different snapshot and playing the
game instead of using a demo, it reduced one shader from 2817 instructions to
2179, due to choosing a now-cheaper texture result to spill instead of piles
of texcoords.
v2: Fix comment noted by Ken, and fix the if condition associated with it for
the current state of what constitutes a partial write of the destination.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| a6411520b40d59a8806289c7aaea4a6b26a54443 |
|
06-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Rename virtual_grf_next to virtual_grf_count.
"count" is a more useful name, since most of the time we're using it for
looping over the variables.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 93831a54c7d4e74f353e0029164b1b3262e98806 |
|
10-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Enable register spilling on gen7 too.
It turns out the same messages work on gen7, we were just being paranoid.
Fixes the penumbra shadows mode of Lightsmark since the register
allocation fix.
NOTE: This is a candidate for release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| a1bfafc5a96012c14db9b0d28223ab54feae131c |
|
07-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add missing register allocation for 3rd sources.
Our only instruction with a 3rd source so far was linterp, and that
value was never register-allocated.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| e910241e9754b6e673ed0fc3133c8b1de56e76c7 |
|
27-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix rendering corruption in unigine tropics.
We were allocating registers into the MRF hack region, resulting in
sparkly renering in a few of the scenes. We could do better
allocation by making an MRF class, having MRFs conflict with the
corresponding GRFs, and tracking the live intervals of the "MRF"s and
setting up the conflicts. But this is way easier for the moment.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| b972744c78e45928876ea781b9eeef09b3baf083 |
|
12-Jan-2012 |
Eric Anholt <eric@anholt.net> |
mesa: Make the register allocator allocation take a ralloc context.
This fixes a memory leak on i965 context destruction.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| e04bdeae82797dbdcf6f544a997a4626fdfd4aee |
|
22-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Parameterize barycentric interpolation modes.
This patch modifies the fragment shader back-end so that instead of
using a single delta_x/delta_y register pair to store barycentric
coordinates, it uses an array of such register pairs, one for each
possible intepolation mode.
When setting up the WM, we intstruct it to only provide the
barycentric coordinates that are actually needed by the fragment
shader--that is computed by brw_compute_barycentric_interp_modes().
Currently this function returns just
BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because this is the only
interpolation mode we support. However, that will change in a later
patch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 6034b9a5124475d300d0678bd2fb6160865fa972 |
|
03-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Create a shared enum for hardware and compiler-internal opcodes.
This should make gdbing more pleasant, and it might be used in sharing
part of the codegen between the VS and FS backends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| c9e81fe14f36933617c862efb15ae09194485eab |
|
15-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop the reg/hw_reg distinction.
"reg" was set in only one case, virtual GRFs pre register allocation,
and would be unset and have hw_reg set after allocation. Since we
never bothered with looking at virtual GRF number after allocation
anyway, just use the same storage and avoid confusion.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| b1f0bffd399f377a19b0541e1d834afad8b9dad0 |
|
09-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Factor out the register allocator setup to a separate function.
Besides separating out a logical step of the giant register allocator
function, this now communicates a bunch of the allocator information
through entries in brw_context, which will make this code partially
reusable for caching the expensive allocator setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 4e10d5825b31d2c58c0af3e29b7fc2eacb2b4709 |
|
06-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Simplify the register allocator using a map from RA reg to GRF.
It's fewer pointers to track, and when we start caching the register
set, should be algorithmically better in the cache hit case (lookup in
a byte-per-register array, instead of a linear walk through
desctiption of register classes to find how to translate that class).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| b76378d46a211521582cfab56dc05031a57502a6 |
|
04-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Eliminate the magic nature of virtual GRF 0.
This was a debugging aid at one point -- virtual grf 0 should never be
allocated, and it would be used if undefined register access occurred
in codegen. However, it made the confusing register allocation code
even more confusing by indexing things off of 1 all over.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| bbcf13adbe525bd389a65ba15dd7831a56b8b13c |
|
04-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Use the new convenience interface for setting up reg conflicts.
That code I wrote was impenetrable, and hard to write the first time.
This makes things a lot more obvious.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 44ffb4ae207e48f78fae55925601b8708ed09c1d |
|
29-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Stop using the exec_list iterator.
The old style has gone out of favor in the project, but I kept copy
and pasting from existing iterator code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 773556e0f537eba82d9d68d618e229140f413620 |
|
25-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen5: Fix grf_used calculation for 16-wide.
If we happened to allocate a texture result (or other vector) to the
highest hardware register slot, and we were in 16-wide, we would
under-count the registers used and potentially wrap around to g0 if
that allocation crossed a 16-register block boundary. Bad rendering
and hangs ensued.
Tested-by: Ian Romanick <idr@freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 7f5e0d2a908d4f7ba781d70731172a07b640f401 |
|
13-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable register spilling on Ivybridge for now.
The data port messages for this are rather different. For now, fail to
compile rather than hanging the GPU.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 2ac1cb8b83ad1f7700cc40519a82c3cf698b543b |
|
13-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for 16-wide dispatch to the register allocator.
Note that the virtual grfs are in increments of the dispatch_width,
not hardware registers -- this makes the 16-wide emit and 8-wide emit
mostly the same.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 59c6b775a6aacfe03c84dae62c2fd45d4af9d70b |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add gen6 register spilling support.
Most of this is code movement to get the scratch space allocated in a
shared location. Other than that, the only real changes are that the
old oword block messages now operate on oword-aligned areas (with new
messages for unaligned access, which we don't do), and that the
caching control is in the SFID part of the descriptor instead of
message control.
Fixes glsl-fs-convolution-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 2911fa0cca86f7acbc5423cab4dd328a412253cd |
|
13-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Make compile failure more verbose with INTEL_DEBUG=wm.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| d3073f58c17d8675a2ecdd5dfa83e5520c78e1a8 |
|
21-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
Convert everything from the talloc API to the ralloc API.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| e256e4743c3f8f924f0d191759d9428f33f3e329 |
|
19-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
glsl, i965: Remove unnecessary talloc includes.
These are already picked up by ir.h or glsl_types.h.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| e880a57a71bbd5152ed26367dcc7051f21c20981 |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Clarify when we need to (re-)calculate live intervals.
The ad-hoc placement of recalculation somewhere between when they got
invalidated and when they were next needed was confusing. This should
clarify what's going on here.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| bb4f12f53875707a0d3c1eb254745b6250c42951 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Disable register spilling on gen6 until it's fixed.
Avoids GPU hang on glsl-fs-convolution-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 07cd8f46acc34b04308f81de2faf05ba33da264b |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for pull constants to the new FS backend.
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 99b2c8570ea6f46c6564681631f0e0750a0641cc |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for register spilling.
It can be tested with if (0) replaced with if (1) to force spilling for all
virtual GRFs. Some simple tests work, but large texturing tests fail.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|
| 5ac6c4ecfe77bf7e02ae61981b2c8b1fe73027cd |
|
20-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Split register allocation out of the ever-growing brw_fs.cpp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
|