| 4e35ffa762d763820b7defc14af564b2a02c61c8 |
|
03-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Try again when we've successfully spilled a reg.
Before, we'd spill one reg, then continue on without actually register
allocating, then assertion fail when we tried to use a vgrf number as a
register number.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit d4bcc6591812ebe72a363cf98371de5e5016f481)
This should have been picked when 9237f0e was picked.
Bugzill: https://bugs.freedesktop.org/show_bug.cgi?id=59700
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| b22de71c1bc2530e139d75d934e203f4eee89f41 |
|
02-Oct-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement register spilling.
To validate this code, I ran piglit -t vs quick.tests with the "go spill
everything" debugging code enabled. There was only one regression:
glsl-vs-unroll-explosion simply ran out of registers. This should be
fine in the real world, since no one actually spills every single
register.
NOTE: This is a candidate for the 9.0 branch. Even if it proves to have
bugs, it's likely better than simply failing to compile.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 9237f0ea8d176fb5dcd41868dcc723fe34f6b1f3)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| bb020d09c382285210a5aebe412ddabfad19e4a0 |
|
25-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add a surface index to VS_OPCODE_PULL_CONSTANT instructions.
Similar to the previous commit for the fragment shader, now we have a buffer
index and an offset.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| b2f5d4c3ec9ec2fec8b39c87eb00121a24107276 |
|
04-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Move class functions to brw_vec4.cpp.
This has less impact than for the FS (4k savings), because it was partially
done already, but makes things more consistent.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 9195191e50429d9cf25e6498f9fb108758ac2be6 |
|
27-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid allocating registers in to the gen7 MRF hack region.
This is the corresponding fix to the previous one for the FS, but I
don't have a particular test for it.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 8e34021099527868097b2c877fc32f29aa4d7bb6 |
|
07-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement EXT_texture_swizzle support for VS texturing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 328b693a199a67ce3a17d258f34d7bfd26790871 |
|
12-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Add support for texel offsets.
The visit() half computes the values to put in the header based on the
IR and simply stuffs that in the vec4_instruction; the emit() half uses
this to set up the message header. This works out well since emit() can
use brw_reg directly and access individual DWords without kludgery.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| ca182cd0fa338ad39d531cb1be6a5a1bbf455771 |
|
26-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement vec4_visitor::generate_tex().
This is the part that takes the vec4_instruction IR and turns it into
actual Gen ISA.
v2: Add Gen4 messages, don't retype m0 to UW.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| bdd76ebef126281d837f3a817a9f19fca7799a88 |
|
28-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Add a new dst_reg constructor for file, number, type, and mask.
This will be especially useful for loading texturing parameters, where I
need to (for example) reference m3.xz<D>.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 7e7c40ff98cc2b930bc3113609ace5430f2bdc95 |
|
26-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Add vec4_instruction::is_tex() query.
Copy and pasted from fs_inst::is_tex(), but without TXB.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| a73c65c5342bf41fa0dfefe7daa9197ce6a11db4 |
|
18-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable faster workaround-free math on Ivybridge.
According to the documentation, Ivybridge's math instruction works in
SIMD16 mode for the fragment shader, and no longer forbids align16 mode
for the vertex shader.
The documentation claims that SIMD16 mode isn't supported for INT DIV,
but empirical evidence shows that it works fine. Presumably the note
is trying to warn us that the variant that returns both quotient and
remainder in (dst, dst + 1) doesn't work in SIMD16 mode since dst + 1
would be sechalf(dst), trashing half your results. Since we don't use
that variant, we don't care and can just enable SIMD16 everywhere.
The documentation also still claims that source modifiers and
conditional modifiers aren't supported, but empirical evidence and
study of the simulator both show that they work just fine.
Goodbye workarounds. Math just works now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 31874f074c2eaf2a9421c57f0798c79078d296c4 |
|
04-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix comparisons with uint negation.
The condmod instruction ends up generating garbage condition codes,
because apparently the comparison happens on the accumulator value (33
bits for UD), not the truncated value that would be written.
Fixes vs-op-neg-*
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| cea946307f319cc7cf3e2cf730be34cd51047965 |
|
07-Oct-2011 |
Brian Paul <brianp@vmware.com> |
i965: make swizzle_for_size() return unsigned
Silences a warning about comparing to an unsigned variable. It looks like
the result of swizzle_for_size() is always assigned to unsigned vars.
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| e967c5b38fcde15a7e78910239735d851e7a7e40 |
|
07-Oct-2011 |
Brian Paul <brianp@vmware.com> |
i965: make size_swizzles[] static const
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| cc3a699e32bed62c38b3b2de280973f067962504 |
|
24-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 new VS: Fix src_reg(uint32_t) constructor.
This constructor was storing its argument in the wrong field of the
"imm" enum, resulting in it being converted to a float when it should
have remained an unsigned integer. This was preventing clipping from
working properly on pre-GEN6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| e7da40afe84349a640fe15e3af408a0dfe880e85 |
|
24-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 new VS: don't share clip plane constants in pre-GEN6
In pre-GEN6, when using clip planes, both the vertex shader and the
clipper need access to the client-supplied clip planes, since the
vertex shader needs them to set the clip flags, and the clipper needs
them to determine where to insert new vertices.
With the old VS backend, we used a clever optimization to avoid
placing duplicate copies of these planes in the CURBE: we used the
same block of memory for both the clipper and vertex shader constants,
with the clip planes at the front of it, and then we instructed the
clipper to read just the initial part of this block containing the
clip planes.
This optimization was tricky, of dubious value, and not completely
working in the new VS backend, so I've removed it. Now, when using
the new VS backend, separate parts of the CURBE are used for the
clipper and the vertex shader. Note that this doesn't affect the
number of push constants available to the vertex shader, it simply
causes the CURBE to occupy a few more bytes of URB memory.
The old VS backend is unaffected. GEN6+, which does clipping entirely
in hardware, is also unaffected.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 62bad54727690bff5ed42a74272e7822fd36cdb6 |
|
02-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Set up clip distance VUE slots appropriately for gl_ClipDistance.
When gl_ClipDistance is in use, the contents of the gl_ClipDistance
array just need to be copied directly into the clip distance VUE
slots, so we re-use the code that copies all other generic VUE slots
(this has been extracted to its own method). When gl_ClipDistance is
not in use, the vertex shader needs to calculate the clip distances
based on user-specified clipping planes.
This patch also removes the i965-specific enum values
BRW_VERT_RESULT_CLIP[01], since we now have generic Mesa enums that
serve the same purpose (VERT_RESULT_CLIP_DIST[01]).
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| c662764f4f9d9d0303fb2685dfdc93824fa15dca |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for compute-to-MRF.
Removes 1.8% of the instructions from 97% of the vertex shaders in
shader-db.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 160848d8ef96cf3a760c02cc576df7dbffc1f669 |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add a function for how many MRFs get written as part of a SEND.
This will be used for compute-to-mrf, which needs to know when MRFs
get overwritten.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 63bc443f8a026a2035ffd3122c8462c6fa36d20b |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Remove dead fields of src_reg.
These were copy and pasted from the FS, and are never used.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| f0c04e6c22babf2aee2ad1ee85dbd6f996be3712 |
|
03-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for simple algebraic optimizations.
We generate silly code for array access, and it's easier to generally
support the cleanup than to specifically avoid the bad code in each
place we might generate it.
Removes 4.6% of instructions from 41.6% of shaders in shader-db,
particularly savage2/hon and unigine.
v2: Fixes by Ken: Make is_zero/one member functions, and fix a
progress flag.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| cc9eb936c220267b6130b705fc696d05906a31df |
|
02-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for copy propagation of the UNIFORM and ATTR files.
Removes 2.0% of the instructions from 35.7% of vertex shaders in shader-db.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 42ce13195b94d0d51ca8e7fa5eed07fde8f37988 |
|
30-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add constant propagation to a few opcodes.
This differs from the FS in that we track constants in each
destination channel, and we we have to look at all the swizzled source
channels. Also, the instruction stream walk is done in an O(n) manner
instead of O(n^2).
Across shader-db, this reduces 8.0% of the instructions from 60.0% of
the vertex shaders, leaving us now behind the old backend by 11.1%
overall.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 87b51fc4a807616eaab0c4b38e41c328c08875e3 |
|
01-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Keep track of indices into a per-register array for virtual GRFs.
Tracking virtual GRFs has tension between using a packed array per
virtual GRF (which is good for register allocation), and sparse arrays
where there's an element per actual register (so the first and second
column of a mat2 can be distinguished inside of an optimization pass).
The FS mostly avoided the need for this second sparse array by doing
virtual GRF splitting, but that meant that instances where virtual GRF
splitting didn't work, instructions using those registers got much
less optimized.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| df35d691807656d3627b6fa6f51a08674bdc043e |
|
07-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for overflowing the number of available push constants.
Fixes glsl-vs-uniform-array-4.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33742
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 6af968b6736c87c05ea579df50e23b6f23b900d4 |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add annotation to more of the URB write.
While we had nice debug output for most of the instruction stream, it
was terminated by a series of anonymous MOVs and a send.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| bba910373fc6cdca939422d94adfe58b43e41b86 |
|
31-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for vector comparison ops resulting in bool cond codes.
Fixes a giant pile of VS tests on gen4.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| e604f98f580b74dd6c597ef492706ce74697443e |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: use the VUE map to write out vertex attributes.
Previously, the new VS backend used two functions,
emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed
parts of the VUE, and then a pair of carefully-constructed loops to
emit the rest of the VUE, leaving out the parts that were already
emitted as part of the header.
This patch changes the new VS backend to use the VUE map to emit the
entire VUE.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| d1435a49e9765ab4e988dd8b65a5599da34f3512 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: move clip distance computation (GEN5+) to a separate function.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| d9eca0b27903acef97f7b69a70dc791b433f1c98 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: Move PSIZ/flags computation to a separate function.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| f86d1976f81811aec0a555946e263295ed1403db |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: move NDC computation (GEN4-5) to a separate function.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 34fbab2125555ba0afffa361e1c74fb3359ef3a7 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: Use output_reg[] to find NDC and HPOS registers.
Previously, emit_vue_header_gen4() used local variables to keep track
of which registers were storing the NDC and HPOS. This patch uses the
output_reg[] array instead, so that the code that manipulates NDC and
HPOS can be more easily refactored.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 0c9ae24dbdfcfea06fb0e8cdfd7737da48fa4e31 |
|
27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions.
v2: Add generator instructions for the scratch opcodes.
Add emit_before() for handling ->ir and ->annotation inheritance.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| e45d0270c9f6f170e35ae39e95977b60f0f0be9a |
|
27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Move logic for weird CMP type handling to CMP generators.
v2: Don't bother with the no-dst-reg version of CMP()
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 2f12be5c952ec84eece74a321e5b0a92314aba3a |
|
27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Create instruction generators outside of the emit() functions.
v2: Fixed gen6 IF().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 72cfc6f3778d8297e52c254a5861a88eb62e4d67 |
|
23-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Pack live uniform vectors together in the push constant upload.
At some point we need to also move uniform accesses out to pull
constants when there are just too many in use, but we lack tests for
that at the moment.
Fixes glsl-vs-large-uniform-array.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 7c84b9d303345fa5075dba8c4ea7af449d93b0f8 |
|
23-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Track uniforms as separate vectors once we've done array access.
This will make it easier to figure out which elements are totally
unused and not upload them.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 483f5b348b0f3c0ca7082fd2047c354e8af285e7 |
|
22-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for pull constant loads for uniform arrays.
v2: reworked the instruction emit and made use of gen6_resolve_implied_move,
from Ken's review
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 88e08de8017b69591b37dafde9afd15f796fb404 |
|
27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Restructure emit() functions around a vec4_instruction constructor.
We sometimes want to put an instruction somewhere besides the end of
the instruction stream, and we also want per-opcode instruction
generation to enable compile-time checking of operands.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 8174945d3346dc049ae56dcb4bf1eab39f5c88aa |
|
17-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add simple dead code elimination.
This is copied right from the fragment shader. It is needed for real
register allocation to work correctly.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 3dadc1e3cceac80a1b63cad2e10f0e0f8904531b |
|
17-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Copy the live intervals calculation over from the FS.
This is a rather pessimistic calculation, since it doesn't distinguish
individual channels of a vec4, or elements of an array, but should be
a minimum start for register allocation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|
| 7642c1de6b65b7dfd9e39904291cc9737cd54b56 |
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11-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid generating a MOV for most ir_assignment handling.
Removes an average of 11.5% of instructions in 54% of vertex shaders
in shader-db.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
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| abf843a797876b5e3c5c91dbec25b6553d2cc281 |
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09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for ir_binop_pow.
Fixes vs-pow-float-float.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
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| 584ff407482fd3baf5ce081dbbf9653eb76c40f1 |
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07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for scratch read/write codegen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
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| d0e4d71070cd7fa197ed98612782484ec1f27123 |
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07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
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| 1ff4f11dd94711a498cde0330101c58636ef2741 |
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07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Track the variable index of array accesses.
This isn't used currently, as we lower all array accesses.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
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| 31ef2e3ec2f5837eea0899b4bda5ea15e335a6a2 |
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06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid generating extra moves when setting up large ir_constants.
We were also screwing up the types in the process, and just not
emitting moves was easier.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
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| 979072613139870f12e329e4b483c7f688b40560 |
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06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Handle assignment of structures/arrays/matrices better.
This gets the right types on the instructions, as well as emitting
minimal swizzles/writemasks.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
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| a070d5f363e99b0f846d555e9ca3a74ec807fdc0 |
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04-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Start adding support for uniforms
There's no clever packing here, no pull constants, and no array support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
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| af3c9803d818fd33139f1247a387d64b967b8992 |
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02-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Start adding the VS visitor and codegen.
The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's
currently controlled by the INTEL_NEW_VS=1 environment variable, and
only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4.h
|