Lines Matching refs:chan
509 * Assert that none of the float values in 'chan' are infinite or NaN.
515 check_inf_or_nan(const union tgsi_exec_channel *chan)
517 assert(!util_is_inf_or_nan((chan)->f[0]));
518 assert(!util_is_inf_or_nan((chan)->f[1]));
519 assert(!util_is_inf_or_nan((chan)->f[2]));
520 assert(!util_is_inf_or_nan((chan)->f[3]));
526 print_chan(const char *msg, const union tgsi_exec_channel *chan)
529 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
583 uint i, chan;
605 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
608 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
613 channelsWritten |= (1 << chan);
1050 union tgsi_exec_channel *chan)
1063 chan->u[i] = 0;
1078 chan->u[i] = 0;
1081 chan->u[i] = buf[pos];
1097 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1106 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1115 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1124 chan->u[i] =
1134 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1142 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1151 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1160 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1170 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1177 chan->u[i] = 0;
1184 union tgsi_exec_channel *chan,
1330 chan);
1334 micro_abs(chan, chan);
1336 micro_iabs(chan, chan);
1342 micro_neg(chan, chan);
1344 micro_ineg(chan, chan);
1351 const union tgsi_exec_channel *chan,
1367 check_inf_or_nan(chan);
1493 fprintf(stderr, "%f, ", chan->f[i]);
1576 dst->i[i] = chan->i[i];
1582 if (chan->f[i] < 0.0f)
1584 else if (chan->f[i] > 1.0f)
1587 dst->i[i] = chan->i[i];
1594 if (chan->f[i] < -1.0f)
1596 else if (chan->f[i] > 1.0f)
1599 dst->i[i] = chan->i[i];
1757 uint chan;
1907 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1908 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1909 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1920 uint chan;
1986 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1987 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1988 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2002 uint chan;
2058 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2059 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2060 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2073 uint chan;
2087 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2088 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2089 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2105 uint chan;
2199 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2200 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2201 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2213 uint chan;
2262 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2263 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2264 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2278 unsigned chan )
2283 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2295 unsigned chan )
2299 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2300 const float dady = mach->InterpCoefs[attrib].dady[chan];
2301 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2302 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2303 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2304 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2305 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2316 unsigned chan )
2320 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2321 const float dady = mach->InterpCoefs[attrib].dady[chan];
2322 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2325 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2326 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2327 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2328 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2335 unsigned chan );
2421 unsigned int chan;
2423 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2424 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2428 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2443 unsigned int chan;
2449 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2450 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2451 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2463 unsigned int chan;
2466 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2467 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2470 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2471 op(&dst.xyzw[chan], &src);
2474 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2475 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2476 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2492 unsigned int chan;
2499 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2500 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2501 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2513 unsigned int chan;
2516 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2517 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2520 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2521 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2522 op(&dst.xyzw[chan], &src[0], &src[1]);
2525 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2526 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2527 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2544 unsigned int chan;
2547 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2548 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2551 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2552 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2553 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2554 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2557 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2558 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2559 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2568 unsigned int chan;
2575 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2576 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2577 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2581 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2582 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2583 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2592 unsigned int chan;
2599 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2600 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2601 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2605 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2607 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2616 unsigned int chan;
2630 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2631 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2632 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2641 unsigned int chan;
2659 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2660 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2661 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2670 unsigned int chan;
2681 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2682 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2683 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2692 unsigned int chan;
2699 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2702 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2703 micro_mul(&product, &arg[chan], &arg[chan]);
2709 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2710 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2711 micro_mul(&arg[chan], &arg[chan], &scale);
2712 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2722 unsigned int chan;
2729 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2732 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2733 micro_mul(&product, &arg[chan], &arg[chan]);
2739 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2740 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2741 micro_mul(&arg[chan], &arg[chan], &scale);
2742 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);