Lines Matching refs:prog
39 struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
44 prog->in[i].id = i;
45 prog->in[i].sn = info->in[i].sn;
46 prog->in[i].si = info->in[i].si;
47 prog->in[i].hw = n;
48 prog->in[i].mask = info->in[i].mask;
50 prog->vp.attrs[(4 * i) / 32] |= info->in[i].mask << ((4 * i) % 32);
56 prog->in_nr = info->numInputs;
61 prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID;
64 prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID;
65 prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_UNK12;
77 if (prog->vp.attrs[0] == 0 &&
78 prog->vp.attrs[1] == 0 &&
79 prog->vp.attrs[2] == 0)
80 prog->vp.attrs[0] |= 0xf;
92 prog->vp.psiz = i;
95 prog->vp.clpd[info->out[i].si] = n;
98 prog->vp.edgeflag = i;
101 prog->vp.bfc[info->out[i].si] = i;
106 prog->out[i].id = i;
107 prog->out[i].sn = info->out[i].sn;
108 prog->out[i].si = info->out[i].si;
109 prog->out[i].hw = n;
110 prog->out[i].mask = info->out[i].mask;
116 prog->out_nr = info->numOutputs;
117 prog->max_out = n;
119 if (prog->vp.psiz < info->numOutputs)
120 prog->vp.psiz = prog->out[prog->vp.psiz].hw;
128 struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
145 /* careful: id may be != i in info->in[prog->in[i].id] */
147 /* Fill prog->in[] so that non-flat inputs are first and
152 prog->fp.interp |= info->in[i].mask << 24;
163 prog->vp.bfc[info->in[i].si] = j;
165 prog->in[j].id = i;
166 prog->in[j].mask = info->in[i].mask;
167 prog->in[j].sn = info->in[i].sn;
168 prog->in[j].si = info->in[i].si;
169 prog->in[j].linear = info->in[i].linear;
171 prog->in_nr++;
174 if (!(prog->fp.interp & (8 << 24))) {
176 prog->fp.interp |= 8 << 24;
179 for (i = 0; i < prog->in_nr; ++i) {
180 int j = prog->in[i].id;
182 prog->in[i].hw = nintp;
184 if (prog->in[i].mask & (1 << c))
188 nflat = (n < m) ? (nintp - prog->in[n].hw) : 0;
189 nintp -= bitcount4(prog->fp.interp >> 24); /* subtract position inputs */
192 prog->fp.interp |= nvary << NV50_3D_FP_INTERPOLANT_CTRL_COUNT_NONFLAT__SHIFT;
193 prog->fp.interp |= nintp << NV50_3D_FP_INTERPOLANT_CTRL_COUNT__SHIFT;
196 prog->fp.colors = 4 << NV50_3D_SEMANTIC_COLOR_FFC0_ID__SHIFT;
198 if (prog->vp.bfc[i] < 0xff)
199 prog->fp.colors += bitcount4(prog->in[prog->vp.bfc[i]].mask) << 16;
204 prog->fp.flags[0] |= NV50_3D_FP_CONTROL_MULTIPLE_RESULTS;
207 prog->out[i].id = i;
208 prog->out[i].sn = info->out[i].sn;
209 prog->out[i].si = info->out[i].si;
210 prog->out[i].mask = info->out[i].mask;
214 prog->out[i].hw = info->out[i].si * 4;
217 info->out[i].slot[c] = prog->out[i].hw + c;
219 prog->max_out = MAX2(prog->max_out, prog->out[i].hw + 4);
223 info->out[info->io.sampleMask].slot[0] = prog->max_out++;
226 info->out[info->io.fragDepth].slot[2] = prog->max_out++;
228 if (!prog->max_out)
229 prog->max_out = 4;
303 nv50_program_translate(struct nv50_program *prog, uint16_t chipset)
307 const uint8_t map_undef = (prog->type == PIPE_SHADER_VERTEX) ? 0x40 : 0x80;
313 info->type = prog->type;
316 info->bin.source = (void *)prog->pipe.tokens;
320 info->io.genUserClip = prog->vp.clpd_nr;
324 prog->vp.bfc[0] = 0xff;
325 prog->vp.bfc[1] = 0xff;
326 prog->vp.edgeflag = 0xff;
327 prog->vp.clpd[0] = map_undef;
328 prog->vp.clpd[1] = map_undef;
329 prog->vp.psiz = map_undef;
330 prog->gp.primid = 0x80;
332 info->driverPriv = prog;
349 prog->code = info->bin.code;
350 prog->code_size = info->bin.codeSize;
351 prog->fixups = info->bin.relocData;
352 prog->max_gpr = MAX2(4, (info->bin.maxGPR >> 1) + 1);
353 prog->tls_space = info->bin.tlsSpace;
355 if (prog->type == PIPE_SHADER_FRAGMENT) {
357 prog->fp.flags[0] |= NV50_3D_FP_CONTROL_EXPORTS_Z;
358 prog->fp.flags[1] = 0x11;
361 prog->fp.flags[0] |= NV50_3D_FP_CONTROL_USES_KIL;
364 if (prog->pipe.stream_output.num_outputs)
365 prog->so = nv50_program_create_strmout_state(info,
366 &prog->pipe.stream_output);
374 nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog)
378 uint32_t size = align(prog->code_size, 0x40);
380 switch (prog->type) {
389 ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
401 prog->code_base = prog->mem->start;
403 ret = nv50_tls_realloc(nv50->screen, prog->tls_space);
409 if (prog->fixups)
410 nv50_ir_relocate_code(prog->fixups, prog->code, prog->code_base, 0, 0);
413 (prog->type << NV50_CODE_BO_SIZE_LOG2) + prog->code_base,
414 NOUVEAU_BO_VRAM, prog->code_size, prog->code);