Lines Matching defs:rtex
1243 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1255 if (rtex->is_depth && !rtex->is_flushing_texture) {
1257 rtex = rtex->flushed_depth_texture;
1258 assert(rtex);
1261 offset = rtex->surface.level[level].offset;
1262 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1263 offset += rtex->surface.level[level].slice_size *
1266 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1267 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1272 switch (rtex->surface.level[level].mode) {
1279 tile_type = rtex->tile_type;
1283 tile_type = rtex->tile_type;
1291 tile_split = rtex->surface.tile_split;
1292 macro_aspect = rtex->surface.mtilea;
1293 bankw = rtex->surface.bankw;
1294 bankh = rtex->surface.bankh;
1295 fmask_bankh = rtex->fmask_bank_height;
1323 if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1324 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1350 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1379 if (rtex->is_rat) {
1401 if (rtex->fmask_size && rtex->cmask_size) {
1413 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1420 if (rtex->fmask_size && rtex->cmask_size) {
1421 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1422 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1428 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1438 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1448 offset += rtex->surface.level[level].offset;
1449 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1450 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1454 switch (rtex->surface.level[level].mode) {
1465 tile_split = rtex->surface.tile_split;
1466 macro_aspect = rtex->surface.mtilea;
1467 bankw = rtex->surface.bankw;
1468 bankh = rtex->surface.bankh;
1483 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1484 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1492 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1493 uint64_t stencil_offset = rtex->surface.stencil_offset;
1494 unsigned i, stile_split = rtex->surface.stencil_tile_split;
1498 stencil_offset += rtex->surface.level[level].offset / 4;
1506 if ((rtex->surface.level[i-1].offset / 4) >> 8 ==
1507 (rtex->surface.level[i].offset / 4) >> 8) {
1699 struct r600_texture *rtex;
1722 rtex = (struct r600_texture*)res;
1759 if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {