Lines Matching defs:bld_base
22 struct lp_build_tgsi_context * bld_base,
27 LLVMValueRef idx = lp_build_const_int32(bld_base->base.gallivm,
29 LLVMValueRef cval = build_intrinsic(bld_base->base.gallivm->builder,
30 "llvm.AMDGPU.load.const", bld_base->base.elem_type,
33 return bitcast(bld_base, type, cval);
50 ctx->soa.bld_base.base.gallivm, chan);
52 ctx->soa.bld_base.base.gallivm->builder,
54 ctx->soa.bld_base.base.elem_type, ®, 1,
59 struct lp_build_tgsi_context * bld_base,
64 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
66 return bitcast(bld_base, type, cval);
82 ctx->soa.bld_base.base.gallivm,
85 ctx->soa.bld_base.base.gallivm->builder,
87 ctx->soa.bld_base.base.elem_type, ®, 1,
92 static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
94 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
95 struct lp_build_context * base = &bld_base->base;
113 static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
115 struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
116 struct lp_build_context * base = &bld_base->base;
144 struct lp_build_tgsi_context * bld_base,
147 struct gallivm_state * gallivm = bld_base->base.gallivm;
169 struct lp_build_tgsi_context * bld_base,
172 struct lp_build_context * base = &bld_base->base;
179 elements[0][chan] = lp_build_emit_fetch(bld_base,
181 elements[1][chan] = lp_build_emit_fetch(bld_base,
195 emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
197 emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm,
217 struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
221 bld_base->info = &shader_info;
222 bld_base->userdata = ctx;
223 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = llvm_fetch_const;
224 bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = llvm_fetch_system_value;
225 bld_base->emit_prologue = llvm_emit_prologue;
226 bld_base->emit_epilogue = llvm_emit_epilogue;
231 bld_base->op_actions[TGSI_OPCODE_DP2] = dot_action;
232 bld_base->op_actions[TGSI_OPCODE_DP3] = dot_action;
233 bld_base->op_actions[TGSI_OPCODE_DP4] = dot_action;
234 bld_base->op_actions[TGSI_OPCODE_DPH] = dot_action;
235 bld_base->op_actions[TGSI_OPCODE_DDX].emit = llvm_emit_tex;
236 bld_base->op_actions[TGSI_OPCODE_DDY].emit = llvm_emit_tex;
237 bld_base->op_actions[TGSI_OPCODE_TEX].emit = llvm_emit_tex;
238 bld_base->op_actions[TGSI_OPCODE_TXB].emit = llvm_emit_tex;
239 bld_base->op_actions[TGSI_OPCODE_TXD].emit = llvm_emit_tex;
240 bld_base->op_actions[TGSI_OPCODE_TXL].emit = llvm_emit_tex;
241 bld_base->op_actions[TGSI_OPCODE_TXF].emit = llvm_emit_tex;
242 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = llvm_emit_tex;
243 bld_base->op_actions[TGSI_OPCODE_TXP].emit = llvm_emit_tex;
245 lp_build_tgsi_llvm(bld_base, tokens);