Lines Matching defs:DAG
1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
53 DebugLoc DL, SelectionDAG &DAG,
70 DebugLoc DL, SelectionDAG &DAG) const
72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
88 // AMDIL DAG lowering
89 case ISD::SDIV: return LowerSDIV(Op, DAG);
90 case ISD::SREM: return LowerSREM(Op, DAG);
91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
93 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
94 // AMDGPU DAG lowering
95 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
96 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
102 SelectionDAG &DAG) const
111 return LowerIntrinsicIABS(Op, DAG);
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
117 return LowerIntrinsicLRP(Op, DAG);
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
139 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
142 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
144 return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1));
150 SelectionDAG &DAG) const
155 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
158 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
164 SelectionDAG &DAG) const
168 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
169 DAG.getConstantFP(1.0f, MVT::f32),
171 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
173 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
181 SelectionDAG &DAG) const
193 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
196 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
199 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
202 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
206 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
211 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
214 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
217 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
220 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
224 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
227 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
230 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
233 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
234 DAG.getConstant(-1, VT),
235 DAG.getConstant(0, VT),
238 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
239 DAG.getConstant(0, VT),
240 DAG.getConstant(-1, VT),
241 DAG.getConstant(0, VT),
244 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
250 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
251 DAG.getConstant(1, VT));
254 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
255 DAG.getConstant(1, VT));
258 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
262 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
268 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
271 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
274 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
278 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
281 DAG.ReplaceAllUsesWith(Op.getValue(0).getNode(), &Div);
282 DAG.ReplaceAllUsesWith(Op.getValue(1).getNode(), &Rem);
313 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
316 MachineFunction &MF = DAG.getMachineFunction();
325 return DAG.getRegister(VirtualRegister, VT);
334 // AMDIL DAG nodes
343 // AMDGPU DAG nodes